1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <asm/semaphore.h>
6 #include <asm/processor.h>
10 #include <asm/mmu_context.h>
14 static int cachesize_override __initdata = -1;
15 static int disable_x86_fxsr __initdata = 0;
16 static int disable_x86_serial_nr __initdata = 1;
18 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
20 extern void mcheck_init(struct cpuinfo_x86 *c);
22 extern int disable_pse;
24 static void default_init(struct cpuinfo_x86 * c)
26 /* Not much we can do here... */
27 /* Check if at least it has cpuid */
28 if (c->cpuid_level == -1) {
29 /* No cpuid. It must be an ancient CPU */
31 strcpy(c->x86_model_id, "486");
33 strcpy(c->x86_model_id, "386");
37 static struct cpu_dev default_cpu = {
38 .c_init = default_init,
40 static struct cpu_dev * this_cpu = &default_cpu;
42 static int __init cachesize_setup(char *str)
44 get_option (&str, &cachesize_override);
47 __setup("cachesize=", cachesize_setup);
49 int __init get_model_name(struct cpuinfo_x86 *c)
54 if (cpuid_eax(0x80000000) < 0x80000004)
57 v = (unsigned int *) c->x86_model_id;
58 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
59 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
60 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
61 c->x86_model_id[48] = 0;
63 /* Intel chips right-justify this string for some dumb reason;
64 undo that brain damage */
65 p = q = &c->x86_model_id[0];
71 while ( q <= &c->x86_model_id[48] )
72 *q++ = '\0'; /* Zero-pad the rest */
79 void __init display_cacheinfo(struct cpuinfo_x86 *c)
81 unsigned int n, dummy, ecx, edx, l2size;
83 n = cpuid_eax(0x80000000);
85 if (n >= 0x80000005) {
86 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
87 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
88 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
89 c->x86_cache_size=(ecx>>24)+(edx>>24);
92 if (n < 0x80000006) /* Some chips just has a large L1. */
95 ecx = cpuid_ecx(0x80000006);
98 /* do processor-specific cache resizing */
99 if (this_cpu->c_size_cache)
100 l2size = this_cpu->c_size_cache(c,l2size);
102 /* Allow user to override all this if necessary. */
103 if (cachesize_override != -1)
104 l2size = cachesize_override;
107 return; /* Again, no L2 cache is possible */
109 c->x86_cache_size = l2size;
111 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
115 /* Naming convention should be: <Name> [(<Codename>)] */
116 /* This table only is used unless init_<vendor>() below doesn't set it; */
117 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
119 /* Look up CPU names by table lookup. */
120 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
122 struct cpu_model_info *info;
124 if ( c->x86_model >= 16 )
125 return NULL; /* Range check */
130 info = this_cpu->c_models;
132 while (info && info->family) {
133 if (info->family == c->x86)
134 return info->model_names[c->x86_model];
137 return NULL; /* Not found */
142 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
144 char *v = c->x86_vendor_id;
147 for (i = 0; i < X86_VENDOR_NUM; i++) {
149 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
150 (cpu_devs[i]->c_ident[1] &&
151 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
153 this_cpu = cpu_devs[i];
161 static int __init x86_fxsr_setup(char * s)
163 disable_x86_fxsr = 1;
166 __setup("nofxsr", x86_fxsr_setup);
169 /* Standard macro to see if a specific flag is changeable */
170 static inline int flag_is_changeable_p(u32 flag)
184 : "=&r" (f1), "=&r" (f2)
187 return ((f1^f2) & flag) != 0;
191 /* Probe for the CPUID instruction */
192 int __init have_cpuid_p(void)
194 return flag_is_changeable_p(X86_EFLAGS_ID);
197 void __init generic_identify(struct cpuinfo_x86 * c)
202 if (have_cpuid_p()) {
203 /* Get vendor name */
204 cpuid(0x00000000, &c->cpuid_level,
205 (int *)&c->x86_vendor_id[0],
206 (int *)&c->x86_vendor_id[8],
207 (int *)&c->x86_vendor_id[4]);
210 /* Initialize the standard set of capabilities */
211 /* Note that the vendor-specific code below might override */
213 /* Intel-defined flags: level 0x00000001 */
214 if ( c->cpuid_level >= 0x00000001 ) {
215 u32 capability, excap;
216 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
217 c->x86_capability[0] = capability;
218 c->x86_capability[4] = excap;
219 c->x86 = (tfms >> 8) & 15;
220 c->x86_model = (tfms >> 4) & 15;
222 c->x86 += (tfms >> 20) & 0xff;
223 c->x86_model += ((tfms >> 16) & 0xF) << 4;
225 c->x86_mask = tfms & 15;
227 /* Have CPUID level 0 only - unheard of */
231 /* AMD-defined flags: level 0x80000001 */
232 xlvl = cpuid_eax(0x80000000);
233 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
234 if ( xlvl >= 0x80000001 )
235 c->x86_capability[1] = cpuid_edx(0x80000001);
236 if ( xlvl >= 0x80000004 )
237 get_model_name(c); /* Default name */
242 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
244 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
245 /* Disable processor serial number */
247 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
249 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
250 printk(KERN_NOTICE "CPU serial number disabled.\n");
251 clear_bit(X86_FEATURE_PN, c->x86_capability);
253 /* Disabling the serial number may affect the cpuid level */
254 c->cpuid_level = cpuid_eax(0);
258 static int __init x86_serial_nr_setup(char *s)
260 disable_x86_serial_nr = 0;
263 __setup("serialnumber", x86_serial_nr_setup);
268 * This does the hard work of actually picking apart the CPU stuff...
270 void __init identify_cpu(struct cpuinfo_x86 *c)
274 c->loops_per_jiffy = loops_per_jiffy;
275 c->x86_cache_size = -1;
276 c->x86_vendor = X86_VENDOR_UNKNOWN;
277 c->cpuid_level = -1; /* CPUID not detected */
278 c->x86_model = c->x86_mask = 0; /* So far unknown... */
279 c->x86_vendor_id[0] = '\0'; /* Unset */
280 c->x86_model_id[0] = '\0'; /* Unset */
281 memset(&c->x86_capability, 0, sizeof c->x86_capability);
283 if (!have_cpuid_p()) {
284 /* First of all, decide if this is a 486 or higher */
285 /* It's a 486 if we can modify the AC flag */
286 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
294 printk(KERN_DEBUG "CPU: After generic identify, caps: %08lx %08lx %08lx %08lx\n",
295 c->x86_capability[0],
296 c->x86_capability[1],
297 c->x86_capability[2],
298 c->x86_capability[3]);
300 if (this_cpu->c_identify) {
301 this_cpu->c_identify(c);
303 printk(KERN_DEBUG "CPU: After vendor identify, caps: %08lx %08lx %08lx %08lx\n",
304 c->x86_capability[0],
305 c->x86_capability[1],
306 c->x86_capability[2],
307 c->x86_capability[3]);
311 * Vendor-specific initialization. In this section we
312 * canonicalize the feature flags, meaning if there are
313 * features a certain CPU supports which CPUID doesn't
314 * tell us, CPUID claiming incorrect flags, or other bugs,
315 * we handle them here.
317 * At the end of this section, c->x86_capability better
318 * indicate the features this CPU genuinely supports!
320 if (this_cpu->c_init)
323 /* Disable the PN if appropriate */
324 squash_the_stupid_serial_number(c);
327 * The vendor-specific functions might have changed features. Now
328 * we do "generic changes."
333 clear_bit(X86_FEATURE_TSC, c->x86_capability);
336 if (disable_x86_fxsr) {
337 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
338 clear_bit(X86_FEATURE_XMM, c->x86_capability);
342 clear_bit(X86_FEATURE_PSE, c->x86_capability);
344 /* If the model name is still unset, do table lookup. */
345 if ( !c->x86_model_id[0] ) {
347 p = table_lookup_model(c);
349 strcpy(c->x86_model_id, p);
352 sprintf(c->x86_model_id, "%02x/%02x",
353 c->x86_vendor, c->x86_model);
356 /* Now the feature flags better reflect actual CPU features! */
358 printk(KERN_DEBUG "CPU: After all inits, caps: %08lx %08lx %08lx %08lx\n",
359 c->x86_capability[0],
360 c->x86_capability[1],
361 c->x86_capability[2],
362 c->x86_capability[3]);
365 * On SMP, boot_cpu_data holds the common feature set between
366 * all CPUs; so make sure that we indicate which features are
367 * common between the CPUs. The first time this routine gets
368 * executed, c == &boot_cpu_data.
370 if ( c != &boot_cpu_data ) {
371 /* AND the already accumulated flags with these */
372 for ( i = 0 ; i < NCAPINTS ; i++ )
373 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
376 /* Init Machine Check Exception if available. */
377 #ifdef CONFIG_X86_MCE
382 * Perform early boot up checks for a valid TSC. See arch/i386/kernel/time.c
385 void __init dodgy_tsc(void)
387 get_cpu_vendor(&boot_cpu_data);
388 if (( boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX ) ||
389 ( boot_cpu_data.x86_vendor == X86_VENDOR_NSC ))
390 cpu_devs[X86_VENDOR_CYRIX]->c_init(&boot_cpu_data);
393 void __init print_cpu_info(struct cpuinfo_x86 *c)
397 if (c->x86_vendor < X86_VENDOR_NUM)
398 vendor = this_cpu->c_vendor;
399 else if (c->cpuid_level >= 0)
400 vendor = c->x86_vendor_id;
402 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
403 printk("%s ", vendor);
405 if (!c->x86_model_id[0])
406 printk("%d86", c->x86);
408 printk("%s", c->x86_model_id);
410 if (c->x86_mask || c->cpuid_level >= 0)
411 printk(" stepping %02x\n", c->x86_mask);
416 unsigned long cpu_initialized __initdata = 0;
419 * We're emulating future behavior.
420 * In the future, the cpu-specific init functions will be called implicitly
421 * via the magic of initcalls.
422 * They will insert themselves into the cpu_devs structure.
423 * Then, when cpu_init() is called, we can just iterate over that array.
426 extern int intel_cpu_init(void);
427 extern int cyrix_init_cpu(void);
428 extern int nsc_init_cpu(void);
429 extern int amd_init_cpu(void);
430 extern int centaur_init_cpu(void);
431 extern int transmeta_init_cpu(void);
432 extern int rise_init_cpu(void);
433 extern int nexgen_init_cpu(void);
434 extern int umc_init_cpu(void);
436 void __init early_cpu_init(void)
443 transmeta_init_cpu();
448 #ifdef CONFIG_DEBUG_PAGEALLOC
449 /* pse is not compatible with on-the-fly unmapping,
450 * disable it even if the cpus claim to support it.
452 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
457 * cpu_init() initializes state that is per-CPU. Some data is already
458 * initialized (naturally) in the bootstrap process, such as the GDT
459 * and IDT. We reload them nevertheless, this function acts as a
460 * 'CPU state barrier', nothing should get across.
462 void __init cpu_init (void)
464 int cpu = smp_processor_id();
465 struct tss_struct * t = init_tss + cpu;
466 struct thread_struct *thread = ¤t->thread;
468 if (test_and_set_bit(cpu, &cpu_initialized)) {
469 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
470 for (;;) local_irq_enable();
472 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
474 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
475 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
476 if (tsc_disable && cpu_has_tsc) {
477 printk(KERN_NOTICE "Disabling TSC...\n");
478 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
479 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
480 set_in_cr4(X86_CR4_TSD);
484 * Initialize the per-CPU GDT with the boot GDT,
485 * and set up the GDT descriptor:
488 memcpy(cpu_gdt_table[cpu], cpu_gdt_table[0], GDT_SIZE);
489 cpu_gdt_descr[cpu].size = GDT_SIZE - 1;
490 cpu_gdt_descr[cpu].address = (unsigned long)cpu_gdt_table[cpu];
493 * Set up the per-thread TLS descriptor cache:
495 memcpy(thread->tls_array, cpu_gdt_table[cpu], GDT_ENTRY_TLS_ENTRIES * 8);
497 __asm__ __volatile__("lgdt %0" : : "m" (cpu_gdt_descr[cpu]));
498 __asm__ __volatile__("lidt %0" : : "m" (idt_descr));
503 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
506 * Set up and load the per-CPU TSS and LDT
508 atomic_inc(&init_mm.mm_count);
509 current->active_mm = &init_mm;
512 enter_lazy_tlb(&init_mm, current);
514 load_esp0(t, thread);
516 cpu_gdt_table[cpu][GDT_ENTRY_TSS].b &= 0xfffffdff;
518 load_LDT(&init_mm.context);
520 /* Set up doublefault TSS pointer in the GDT */
521 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
522 cpu_gdt_table[cpu][GDT_ENTRY_DOUBLEFAULT_TSS].b &= 0xfffffdff;
524 /* Clear %fs and %gs. */
525 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
527 /* Clear all 6 debug registers: */
529 #define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
531 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
536 * Force FPU initialization:
538 current_thread_info()->status = 0;
539 current->used_math = 0;
540 mxcsr_feature_mask_init();