2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * Licensed under the terms of the GNU GPL License version 2.
6 * Library for common functions for Intel SpeedStep v.1 and v.2 support
8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/cpufreq.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
20 #include "speedstep-lib.h"
24 * Define it if you want verbose debug output, e.g. for bug reporting
26 //#define SPEEDSTEP_DEBUG
28 #ifdef SPEEDSTEP_DEBUG
29 #define dprintk(msg...) printk(msg)
31 #define dprintk(msg...) do { } while(0)
34 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
35 static int relaxed_check = 0;
37 #define relaxed_check 0
40 /*********************************************************************
41 * GET PROCESSOR CORE SPEED IN KHZ *
42 *********************************************************************/
44 static unsigned int pentium3_get_frequency (unsigned int processor)
46 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
48 unsigned int ratio; /* Frequency Multiplier (x10) */
49 u8 bitmap; /* power on configuration bits
50 [27, 25:22] (in MSR 0x2a) */
51 } msr_decode_mult [] = {
66 { 0, 0xff } /* error or unknown value */
69 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
71 unsigned int value; /* Front Side Bus speed in MHz */
72 u8 bitmap; /* power on configuration bits [18: 19]
74 } msr_decode_fsb [] = {
84 /* read MSR 0x2a - we only need the low 32 bits */
85 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
86 dprintk(KERN_DEBUG "speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
92 while (msr_tmp != msr_decode_fsb[i].bitmap) {
93 if (msr_decode_fsb[i].bitmap == 0xff)
98 /* decode the multiplier */
99 if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY)
100 msr_lo &= 0x03c00000;
102 msr_lo &= 0x0bc00000;
104 while (msr_lo != msr_decode_mult[j].bitmap) {
105 if (msr_decode_mult[j].bitmap == 0xff)
110 return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
114 static unsigned int pentiumM_get_frequency(void)
118 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
119 dprintk(KERN_DEBUG "speedstep-lib: PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
121 /* see table B-2 of 24547212.pdf */
122 if (msr_lo & 0x00040000) {
123 printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
127 msr_tmp = (msr_lo >> 22) & 0x1f;
128 dprintk(KERN_DEBUG "speedstep-lib: bits 22-26 are 0x%x\n", msr_tmp);
130 return (msr_tmp * 100 * 1000);
134 static unsigned int pentium4_get_frequency(void)
136 struct cpuinfo_x86 *c = &boot_cpu_data;
137 u32 msr_lo, msr_hi, mult;
138 unsigned int fsb = 0;
140 rdmsr(0x2c, msr_lo, msr_hi);
142 dprintk(KERN_DEBUG "speedstep-lib: P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
144 /* decode the FSB: see IA-32 Intel (C) Architecture Software
145 * Developer's Manual, Volume 3: System Prgramming Guide,
146 * revision #12 in Table B-1: MSRs in the Pentium 4 and
147 * Intel Xeon Processors, on page B-4 and B-5.
149 if (c->x86_model < 2)
152 u8 fsb_code = (msr_lo >> 16) & 0x7;
167 printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
172 dprintk(KERN_DEBUG "speedstep-lib: P4 - FSB %u kHz; Multiplier %u\n", fsb, mult);
178 unsigned int speedstep_get_processor_frequency(unsigned int processor)
181 case SPEEDSTEP_PROCESSOR_PM:
182 return pentiumM_get_frequency();
183 case SPEEDSTEP_PROCESSOR_P4D:
184 case SPEEDSTEP_PROCESSOR_P4M:
185 return pentium4_get_frequency();
186 case SPEEDSTEP_PROCESSOR_PIII_T:
187 case SPEEDSTEP_PROCESSOR_PIII_C:
188 case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
189 return pentium3_get_frequency(processor);
195 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
198 /*********************************************************************
199 * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
200 *********************************************************************/
202 unsigned int speedstep_detect_processor (void)
204 struct cpuinfo_x86 *c = cpu_data;
205 u32 ebx, msr_lo, msr_hi;
207 if ((c->x86_vendor != X86_VENDOR_INTEL) ||
208 ((c->x86 != 6) && (c->x86 != 0xF)))
212 /* Intel Mobile Pentium 4-M
213 * or Intel Mobile Pentium 4 with 533 MHz FSB */
214 if (c->x86_model != 2)
217 ebx = cpuid_ebx(0x00000001);
220 dprintk(KERN_INFO "ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
222 switch (c->x86_mask) {
225 * B-stepping [M-P4-M]
226 * sample has ebx = 0x0f, production has 0x0e.
228 if ((ebx == 0x0e) || (ebx == 0x0f))
229 return SPEEDSTEP_PROCESSOR_P4M;
233 * C-stepping [M-P4-M]
234 * needs to have ebx=0x0e, else it's a celeron:
235 * cf. 25130917.pdf / page 7, footnote 5 even
236 * though 25072120.pdf / page 7 doesn't say
237 * samples are only of B-stepping...
240 return SPEEDSTEP_PROCESSOR_P4M;
244 * D-stepping [M-P4-M or M-P4/533]
246 * this is totally strange: CPUID 0x0F29 is
247 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
248 * The latter need to be sorted out as they don't
250 * Celerons with CPUID 0x0F29 may have either
251 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
253 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
254 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
255 * also, M-P4M HTs have ebx=0x8, too
256 * For now, they are distinguished by the model_id string
258 if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
259 return SPEEDSTEP_PROCESSOR_P4M;
267 switch (c->x86_model) {
268 case 0x0B: /* Intel PIII [Tualatin] */
269 /* cpuid_ebx(1) is 0x04 for desktop PIII,
270 0x06 for mobile PIII-M */
271 ebx = cpuid_ebx(0x00000001);
278 /* So far all PIII-M processors support SpeedStep. See
279 * Intel's 24540640.pdf of June 2003
282 return SPEEDSTEP_PROCESSOR_PIII_T;
284 case 0x08: /* Intel PIII [Coppermine] */
286 /* all mobile PIII Coppermines have FSB 100 MHz
287 * ==> sort out a few desktop PIIIs. */
288 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
289 dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
291 if (msr_lo != 0x0080000)
295 * If the processor is a mobile version,
296 * platform ID has bit 50 set
297 * it has SpeedStep technology if either
298 * bit 56 or 57 is set
300 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
301 dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
302 if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
303 if (c->x86_mask == 0x01)
304 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
306 return SPEEDSTEP_PROCESSOR_PIII_C;
313 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
316 /*********************************************************************
317 * DETECT SPEEDSTEP SPEEDS *
318 *********************************************************************/
320 unsigned int speedstep_get_freqs(unsigned int processor,
321 unsigned int *low_speed,
322 unsigned int *high_speed,
323 void (*set_state) (unsigned int state))
325 unsigned int prev_speed;
326 unsigned int ret = 0;
329 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
332 /* get current speed */
333 prev_speed = speedstep_get_processor_frequency(processor);
337 local_irq_save(flags);
339 /* switch to low state */
340 set_state(SPEEDSTEP_LOW);
341 *low_speed = speedstep_get_processor_frequency(processor);
347 /* switch to high state */
348 set_state(SPEEDSTEP_HIGH);
349 *high_speed = speedstep_get_processor_frequency(processor);
355 if (*low_speed == *high_speed) {
360 /* switch to previous state, if necessary */
361 if (*high_speed != prev_speed)
362 set_state(SPEEDSTEP_LOW);
365 local_irq_restore(flags);
368 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
370 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
371 module_param(relaxed_check, int, 0444);
372 MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
375 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
376 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
377 MODULE_LICENSE ("GPL");