2 * linux/arch/i386/kernel/head.S -- the 32-bit startup code.
4 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Enhanced CPU detection and feature setting code by Mike Jagdis
7 * and Martin Mares, November 1997.
11 #include <linux/config.h>
12 #include <linux/threads.h>
13 #include <linux/linkage.h>
14 #include <asm/segment.h>
16 #include <asm/pgtable.h>
18 #include <asm/cache.h>
19 #include <asm/thread_info.h>
20 #include <asm/asm_offsets.h>
21 #include <asm/setup.h>
24 * References to members of the new_cpu_data structure.
27 #define CPU_PARAMS new_cpu_data
28 #define X86 CPU_PARAMS+0
29 #define X86_VENDOR CPU_PARAMS+1
30 #define X86_MODEL CPU_PARAMS+2
31 #define X86_MASK CPU_PARAMS+3
32 #define X86_HARD_MATH CPU_PARAMS+6
33 #define X86_CPUID CPU_PARAMS+8
34 #define X86_CAPABILITY CPU_PARAMS+12
35 #define X86_VENDOR_ID CPU_PARAMS+36 /* offset dependent on NCAPINTS */
38 * This is how much memory *in addition to the memory covered up to
39 * and including _end* we need mapped initially. We need one bit for
40 * each possible page, but only in low memory, which means
41 * 2^32/4096/8 = 128K worst case (4G/4G split.)
43 * Modulo rounding, each megabyte assigned here requires a kilobyte of
44 * memory, which is currently unreclaimed.
46 * This should be a multiple of a page.
48 #define INIT_MAP_BEYOND_END (128*1024)
52 * 32-bit kernel entrypoint; only used by the boot CPU. On entry,
53 * %esi points to the real-mode code as a 32-bit pointer.
54 * CS and DS must be 4 GB flat segments, but we don't depend on
55 * any particular GDT layout, because we load our own as soon as we
61 * Set segments to known values.
64 lgdt boot_gdt_descr - __PAGE_OFFSET
65 movl $(__BOOT_DS),%eax
72 * Clear BSS first so that there are no surprises...
73 * No need to cld as DF is already clear from cld above...
76 movl $__bss_start - __PAGE_OFFSET,%edi
77 movl $__bss_stop - __PAGE_OFFSET,%ecx
83 * Initialize page tables. This creates a PDE and a set of page
84 * tables, which are located immediately beyond _end. The variable
85 * init_pg_tables_end is set up to point to the first "safe" location.
86 * Mappings are created both at virtual address 0 (identity mapping)
87 * and PAGE_OFFSET for up to _end+sizeof(page tables)+INIT_MAP_BEYOND_END.
89 * Warning: don't use %esi or the stack in this code. However, %esp
90 * can be used as a GPR if you really need it...
92 page_pde_offset = (__PAGE_OFFSET >> 20);
94 movl $(pg0 - __PAGE_OFFSET), %edi
95 movl $(swapper_pg_dir - __PAGE_OFFSET), %edx
96 movl $0x007, %eax /* 0x007 = PRESENT+RW+USER */
98 leal 0x007(%edi),%ecx /* Create PDE entry */
99 movl %ecx,(%edx) /* Store identity PDE entry */
100 movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */
107 /* End condition: we must map up to and including INIT_MAP_BEYOND_END */
108 /* bytes beyond the end of our own page tables; the +0x007 is the attribute bits */
109 leal (INIT_MAP_BEYOND_END+0x007)(%edi),%ebp
112 movl %edi,(init_pg_tables_end - __PAGE_OFFSET)
115 xorl %ebx,%ebx /* This is the boot CPU (BSP) */
119 * Non-boot CPU entry point; entered from trampoline.S
120 * We can't lgdt here, because lgdt itself uses a data segment, but
121 * we know the trampoline has already loaded the boot_gdt_table GDT
124 ENTRY(startup_32_smp)
126 movl $(__BOOT_DS),%eax
133 incl %ebx /* This is a secondary processor (AP) */
136 * New page tables may be in 4Mbyte page mode and may
137 * be using the global pages.
139 * NOTE! If we are on a 486 we may have no cr4 at all!
140 * So we do not try to touch it unless we really have
141 * some bits in it to set. This won't work if the BSP
142 * implements cr4 but this AP does not -- very unlikely
143 * but be warned! The same applies to the pse feature
144 * if not equally supported. --macro
146 * NOTE! We have to correct for the fact that we're
147 * not yet offset PAGE_OFFSET..
149 #define cr4_bits mmu_cr4_features-__PAGE_OFFSET
153 movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
158 #endif /* CONFIG_SMP */
163 movl $swapper_pg_dir-__PAGE_OFFSET,%eax
164 movl %eax,%cr3 /* set the page table pointer.. */
167 movl %eax,%cr0 /* ..and set paging (PG) bit */
168 ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
170 /* Set up the stack pointer */
174 * Initialize eflags. Some BIOS's leave bits like NT set. This would
175 * confuse the debugger if this code is traced.
176 * XXX - best to initialize before switching to protected mode.
183 jz 1f /* Initial CPU cleans BSS */
186 #endif /* CONFIG_SMP */
189 * start system 32-bit setup. We need to re-do some of the things done
190 * in 16-bit mode for the "real" operations.
195 * Copy bootup parameters out of the way.
196 * Note: %esi still has the pointer to the real-mode data.
198 movl $boot_params,%edi
199 movl $(PARAM_SIZE/4),%ecx
203 movl boot_params+NEW_CL_POINTER,%esi
205 jnz 2f # New command line protocol
206 cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
208 movzwl OLD_CL_OFFSET,%esi
209 addl $(OLD_CL_BASE_ADDR),%esi
211 movl $saved_command_line,%edi
212 movl $(COMMAND_LINE_SIZE/4),%ecx
218 movl $-1,X86_CPUID # -1 for no CPUID initially
220 /* check if it is 486 or 386. */
222 * XXX - this does a lot of unnecessary setup. Alignment checks don't
223 * apply at our cpl of 0 and the stack ought to be aligned already, and
224 * we don't need to preserve eflags.
227 movb $3,X86 # at least 386
229 popl %eax # get EFLAGS
230 movl %eax,%ecx # save original EFLAGS
231 xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
232 pushl %eax # copy to EFLAGS
234 pushfl # get new EFLAGS
235 popl %eax # put it in eax
236 xorl %ecx,%eax # change in flags
237 pushl %ecx # restore original EFLAGS
239 testl $0x40000,%eax # check if AC bit changed
242 movb $4,X86 # at least 486
243 testl $0x200000,%eax # check if ID bit changed
246 /* get vendor info */
247 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
249 movl %eax,X86_CPUID # save CPUID level
250 movl %ebx,X86_VENDOR_ID # lo 4 chars
251 movl %edx,X86_VENDOR_ID+4 # next 4 chars
252 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
254 orl %eax,%eax # do we have processor info as well?
257 movl $1,%eax # Use the CPUID instruction to get CPU type
259 movb %al,%cl # save reg for future use
260 andb $0x0f,%ah # mask processor family
262 andb $0xf0,%al # mask model
265 andb $0x0f,%cl # mask mask revision
267 movl %edx,X86_CAPABILITY
269 is486: movl $0x50022,%ecx # set AM, WP, NE and MP
272 is386: movl $2,%ecx # set MP
274 andl $0x80000011,%eax # Save PG,PE,ET
282 ljmp $(__KERNEL_CS),$1f
283 1: movl $(__KERNEL_DS),%eax # reload all the segment registers
284 movl %eax,%ss # after changing gdt.
286 movl $(__USER_DS),%eax # DS/ES contains default USER segment
290 xorl %eax,%eax # Clear FS/GS and LDT
294 cld # gcc2 wants the direction flag cleared at all times
298 je 1f # the first CPU calls start_kernel
299 # all other CPUs call initialize_secondary
300 call initialize_secondary
303 #endif /* CONFIG_SMP */
306 jmp L6 # main should never return here, but
307 # just in case, we know what happens.
310 * We depend on ET to be correct. This checks for 287/387.
313 movb $0,X86_HARD_MATH
319 movl %cr0,%eax /* no coprocessor: have to set bits */
320 xorl $4,%eax /* set EM */
324 1: movb $1,X86_HARD_MATH
325 .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
331 * sets up a idt with 256 entries pointing to
332 * ignore_int, interrupt gates. It doesn't actually load
333 * idt - that can be done only after paging has been enabled
334 * and the kernel moved to PAGE_OFFSET. Interrupts
335 * are enabled elsewhere, when we can be relatively
336 * sure everything is ok.
338 * Warning: %esi is live across this function.
342 movl $(__KERNEL_CS << 16),%eax
343 movw %dx,%ax /* selector = 0x0010 = cs */
344 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
356 /* This is the default interrupt "handler" :-) */
365 movl $(__KERNEL_DS),%eax
383 * Real beginning of normal "text" segment
391 .section ".bss.page_aligned","w"
392 ENTRY(swapper_pg_dir)
394 ENTRY(empty_zero_page)
398 * This starts the data section.
403 .long init_thread_union+THREAD_SIZE
409 .asciz "Unknown interrupt or fault at EIP %p %p %p\n"
412 * The IDT and GDT 'descriptors' are a strange 48-bit object
413 * only used by the lidt and lgdt instructions. They are not
414 * like usual segment descriptors - they consist of a 16-bit
415 * segment size, and 32-bit linear address value:
418 .globl boot_gdt_descr
423 # early boot GDT descriptor (must use 1:1 address mapping)
424 .word 0 # 32 bit align gdt_desc.address
427 .long boot_gdt_table - __PAGE_OFFSET
429 .word 0 # 32-bit align idt_desc.address
431 .word IDT_ENTRIES*8-1 # idt contains 256 entries
434 # boot GDT descriptor (later on used by CPU#0):
435 .word 0 # 32 bit align gdt_desc.address
437 .word GDT_ENTRIES*8-1
440 .fill NR_CPUS-1,8,0 # space for the other GDT descriptors
443 * The boot_gdt_table must mirror the equivalent in setup.S and is
444 * used only for booting.
446 .align L1_CACHE_BYTES
447 ENTRY(boot_gdt_table)
448 .fill GDT_ENTRY_BOOT_CS,8,0
449 .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
450 .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */
453 * The Global Descriptor Table contains 28 quadwords, per-CPU.
457 .quad 0x0000000000000000 /* NULL descriptor */
458 .quad 0x0000000000000000 /* 0x0b reserved */
459 .quad 0x0000000000000000 /* 0x13 reserved */
460 .quad 0x0000000000000000 /* 0x1b reserved */
461 .quad 0x0000000000000000 /* 0x20 unused */
462 .quad 0x0000000000000000 /* 0x28 unused */
463 .quad 0x0000000000000000 /* 0x33 TLS entry 1 */
464 .quad 0x0000000000000000 /* 0x3b TLS entry 2 */
465 .quad 0x0000000000000000 /* 0x43 TLS entry 3 */
466 .quad 0x0000000000000000 /* 0x4b reserved */
467 .quad 0x0000000000000000 /* 0x53 reserved */
468 .quad 0x0000000000000000 /* 0x5b reserved */
470 .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */
471 .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */
472 .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */
473 .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */
475 .quad 0x0000000000000000 /* 0x80 TSS descriptor */
476 .quad 0x0000000000000000 /* 0x88 LDT descriptor */
478 /* Segments used for calling PnP BIOS */
479 .quad 0x00c09a0000000000 /* 0x90 32-bit code */
480 .quad 0x00809a0000000000 /* 0x98 16-bit code */
481 .quad 0x0080920000000000 /* 0xa0 16-bit data */
482 .quad 0x0080920000000000 /* 0xa8 16-bit data */
483 .quad 0x0080920000000000 /* 0xb0 16-bit data */
485 * The APM segments have byte granularity and their bases
486 * and limits are set at run time.
488 .quad 0x00409a0000000000 /* 0xb8 APM CS code */
489 .quad 0x00009a0000000000 /* 0xc0 APM CS 16 code (16 bit) */
490 .quad 0x0040920000000000 /* 0xc8 APM DS data */
492 .quad 0x0000000000000000 /* 0xd0 - unused */
493 .quad 0x0000000000000000 /* 0xd8 - unused */
494 .quad 0x0000000000000000 /* 0xe0 - unused */
495 .quad 0x0000000000000000 /* 0xe8 - unused */
496 .quad 0x0000000000000000 /* 0xf0 - unused */
497 .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */
500 .fill (NR_CPUS-1)*GDT_ENTRIES,8,0 /* other CPU's GDT */