1 #include <linux/config.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/smp_lock.h>
11 #include <linux/init.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/sysdev.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
19 #include <asm/bitops.h>
20 #include <asm/pgtable.h>
21 #include <asm/delay.h>
24 #include <asm/arch_hooks.h>
25 #include <asm/i8259.h>
27 #include <linux/irq.h>
32 * This is the 'legacy' 8259A Programmable Interrupt Controller,
33 * present in the majority of PC/AT boxes.
34 * plus some generic x86 specific things if generic specifics makes
36 * this file should become arch/i386/kernel/irq.c when the old irq.c
37 * moves to arch independent land
40 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
42 static void end_8259A_irq (unsigned int irq)
44 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
46 enable_8259A_irq(irq);
49 #define shutdown_8259A_irq disable_8259A_irq
51 void mask_and_ack_8259A(unsigned int);
53 unsigned int startup_8259A_irq(unsigned int irq)
55 enable_8259A_irq(irq);
56 return 0; /* never anything pending */
59 static struct hw_interrupt_type i8259A_irq_type = {
71 * 8259A PIC functions to handle ISA devices:
75 * This contains the irq mask for both 8259A irq controllers,
77 unsigned int cached_irq_mask = 0xffff;
80 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
81 * boards the timer interrupt is not really connected to any IO-APIC pin,
82 * it's fed to the master 8259A's IR0 line only.
84 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
85 * this 'mixed mode' IRQ handling costs nothing because it's only used
88 unsigned long io_apic_irqs;
90 void disable_8259A_irq(unsigned int irq)
92 unsigned int mask = 1 << irq;
95 spin_lock_irqsave(&i8259A_lock, flags);
96 cached_irq_mask |= mask;
98 outb(cached_slave_mask, PIC_SLAVE_IMR);
100 outb(cached_master_mask, PIC_MASTER_IMR);
101 spin_unlock_irqrestore(&i8259A_lock, flags);
104 void enable_8259A_irq(unsigned int irq)
106 unsigned int mask = ~(1 << irq);
109 spin_lock_irqsave(&i8259A_lock, flags);
110 cached_irq_mask &= mask;
112 outb(cached_slave_mask, PIC_SLAVE_IMR);
114 outb(cached_master_mask, PIC_MASTER_IMR);
115 spin_unlock_irqrestore(&i8259A_lock, flags);
118 int i8259A_irq_pending(unsigned int irq)
120 unsigned int mask = 1<<irq;
124 spin_lock_irqsave(&i8259A_lock, flags);
126 ret = inb(PIC_MASTER_CMD) & mask;
128 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
129 spin_unlock_irqrestore(&i8259A_lock, flags);
134 void make_8259A_irq(unsigned int irq)
136 disable_irq_nosync(irq);
137 io_apic_irqs &= ~(1<<irq);
138 irq_desc[irq].handler = &i8259A_irq_type;
143 * This function assumes to be called rarely. Switching between
144 * 8259A registers is slow.
145 * This has to be protected by the irq controller spinlock
146 * before being called.
148 static inline int i8259A_irq_real(unsigned int irq)
151 int irqmask = 1<<irq;
154 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
155 value = inb(PIC_MASTER_CMD) & irqmask;
156 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
159 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
160 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
161 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
166 * Careful! The 8259A is a fragile beast, it pretty
167 * much _has_ to be done exactly like this (mask it
168 * first, _then_ send the EOI, and the order of EOI
169 * to the two 8259s is important!
171 void mask_and_ack_8259A(unsigned int irq)
173 unsigned int irqmask = 1 << irq;
176 spin_lock_irqsave(&i8259A_lock, flags);
178 * Lightweight spurious IRQ detection. We do not want
179 * to overdo spurious IRQ handling - it's usually a sign
180 * of hardware problems, so we only do the checks we can
181 * do without slowing down good hardware unnecesserily.
183 * Note that IRQ7 and IRQ15 (the two spurious IRQs
184 * usually resulting from the 8259A-1|2 PICs) occur
185 * even if the IRQ is masked in the 8259A. Thus we
186 * can check spurious 8259A IRQs without doing the
187 * quite slow i8259A_irq_real() call for every IRQ.
188 * This does not cover 100% of spurious interrupts,
189 * but should be enough to warn the user that there
190 * is something bad going on ...
192 if (cached_irq_mask & irqmask)
193 goto spurious_8259A_irq;
194 cached_irq_mask |= irqmask;
198 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
199 outb(cached_slave_mask, PIC_SLAVE_IMR);
200 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
201 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
203 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
204 outb(cached_master_mask, PIC_MASTER_IMR);
205 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
207 spin_unlock_irqrestore(&i8259A_lock, flags);
212 * this is the slow path - should happen rarely.
214 if (i8259A_irq_real(irq))
216 * oops, the IRQ _is_ in service according to the
217 * 8259A - not spurious, go handle it.
219 goto handle_real_irq;
222 static int spurious_irq_mask;
224 * At this point we can be sure the IRQ is spurious,
225 * lets ACK and report it. [once per IRQ]
227 if (!(spurious_irq_mask & irqmask)) {
228 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
229 spurious_irq_mask |= irqmask;
231 atomic_inc(&irq_err_count);
233 * Theoretically we do not have to handle this IRQ,
234 * but in Linux this does not cause problems and is
237 goto handle_real_irq;
241 static int i8259A_resume(struct sys_device *dev)
247 static struct sysdev_class i8259_sysdev_class = {
248 set_kset_name("i8259"),
249 .resume = i8259A_resume,
252 static struct sys_device device_i8259A = {
254 .cls = &i8259_sysdev_class,
257 static int __init i8259A_init_sysfs(void)
259 int error = sysdev_class_register(&i8259_sysdev_class);
261 error = sysdev_register(&device_i8259A);
265 device_initcall(i8259A_init_sysfs);
267 void init_8259A(int auto_eoi)
271 spin_lock_irqsave(&i8259A_lock, flags);
273 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
274 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
277 * outb_p - this has to work on a wide range of PC hardware.
279 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
280 outb_p(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
281 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
282 if (auto_eoi) /* master does Auto EOI */
283 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
284 else /* master expects normal EOI */
285 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
287 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
288 outb_p(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
289 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
290 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
293 * in AEOI mode we just have to mask the interrupt
296 i8259A_irq_type.ack = disable_8259A_irq;
298 i8259A_irq_type.ack = mask_and_ack_8259A;
300 udelay(100); /* wait for 8259A to initialize */
302 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
303 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
305 spin_unlock_irqrestore(&i8259A_lock, flags);
309 * Note that on a 486, we don't want to do a SIGFPE on an irq13
310 * as the irq is unreliable, and exception 16 works correctly
311 * (ie as explained in the intel literature). On a 386, you
312 * can't use exception 16 due to bad IBM design, so we have to
313 * rely on the less exact irq13.
315 * Careful.. Not only is IRQ13 unreliable, but it is also
316 * leads to races. IBM designers who came up with it should
321 static irqreturn_t math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
323 extern void math_error(void __user *);
325 if (ignore_fpu_irq || !boot_cpu_data.hard_math)
327 math_error((void __user *)regs->eip);
332 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
333 * so allow interrupt sharing.
335 static struct irqaction fpu_irq = { math_error_irq, 0, CPU_MASK_NONE, "fpu", NULL, NULL };
337 void __init init_ISA_irqs (void)
341 #ifdef CONFIG_X86_LOCAL_APIC
346 for (i = 0; i < NR_IRQS; i++) {
347 irq_desc[i].status = IRQ_DISABLED;
348 irq_desc[i].action = NULL;
349 irq_desc[i].depth = 1;
353 * 16 old-style INTA-cycle interrupts:
355 irq_desc[i].handler = &i8259A_irq_type;
358 * 'high' PCI IRQs filled in on demand
360 irq_desc[i].handler = &no_irq_type;
365 static void setup_timer(void)
367 extern spinlock_t i8253_lock;
370 spin_lock_irqsave(&i8253_lock, flags);
371 outb_p(0x34,PIT_MODE); /* binary, mode 2, LSB/MSB, ch 0 */
373 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
375 outb(LATCH >> 8 , PIT_CH0); /* MSB */
376 spin_unlock_irqrestore(&i8253_lock, flags);
379 static int timer_resume(struct sys_device *dev)
385 static struct sysdev_class timer_sysclass = {
386 set_kset_name("timer"),
387 .resume = timer_resume,
390 static struct sys_device device_timer = {
392 .cls = &timer_sysclass,
395 static int __init init_timer_sysfs(void)
397 int error = sysdev_class_register(&timer_sysclass);
399 error = sysdev_register(&device_timer);
403 device_initcall(init_timer_sysfs);
405 void __init init_IRQ(void)
409 /* all the set up before the call gates are initialised */
410 pre_intr_init_hook();
413 * Cover the whole vector space, no vector can escape
414 * us. (some of these will be overridden and become
415 * 'special' SMP interrupts)
417 for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
418 int vector = FIRST_EXTERNAL_VECTOR + i;
421 if (vector != SYSCALL_VECTOR)
422 set_intr_gate(vector, interrupt[i]);
425 /* setup after call gates are initialised (usually add in
426 * the architecture specific gates)
431 * Set the clock to HZ Hz, we already have a valid
437 * External FPU? Set up irq13 if so, for
438 * original braindamaged IBM FERR coupling.
440 if (boot_cpu_data.hard_math && !cpu_has_fpu)
441 setup_irq(FPU_IRQ, &fpu_irq);
443 irq_ctx_init(smp_processor_id());