arch/i386/kernel/io_apic-xen.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/compiler.h>
  32 #include <linux/acpi.h>
  33 #include <linux/module.h>
  34 #include <linux/sysdev.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41
  42 #include <mach_apic.h>
  43
  44 #include "io_ports.h"
  45
  46 #ifdef CONFIG_XEN
  47
  48 #include <xen/interface/xen.h>
  49 #include <xen/interface/physdev.h>
  50
  51 /* Fake i8259 */
  52 #define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
  53 #define disable_8259A_irq(_irq)  ((void)0)
  54 #define i8259A_irq_pending(_irq) (0)
  55
  56 unsigned long io_apic_irqs;
  57
  58 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
  59 {
  60         struct physdev_apic apic_op;
  61         int ret;
  62
  63         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
  64         apic_op.reg = reg;
  65         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
  66         if (ret)
  67                 return ret;
  68         return apic_op.value;
  69 }
  70
  71 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
  72 {
  73         struct physdev_apic apic_op;
  74
  75         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
  76         apic_op.reg = reg;
  77         apic_op.value = value;
  78         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
  79 }
  80
  81 #define io_apic_read(a,r)    xen_io_apic_read(a,r)
  82 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
  83
  84 #endif /* CONFIG_XEN */
  85
  86 int (*ioapic_renumber_irq)(int ioapic, int irq);
  87 atomic_t irq_mis_count;
  88
  89 /* Where if anywhere is the i8259 connect in external int mode */
  90 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  91
  92 static DEFINE_SPINLOCK(ioapic_lock);
  93
  94 int timer_over_8254 __initdata = 1;
  95
  96 /*
  97  *      Is the SiS APIC rmw bug present ?
  98  *      -1 = don't know, 0 = no, 1 = yes
  99  */
 100 int sis_apic_bug = -1;
 101
 102 /*
 103  * # of IRQ routing registers
 104  */
 105 int nr_ioapic_registers[MAX_IO_APICS];
 106
 107 int disable_timer_pin_1 __initdata;
 108
 109 /*
 110  * Rough estimation of how many shared IRQs there are, can
 111  * be changed anytime.
 112  */
 113 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 114 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 115
 116 /*
 117  * This is performance-critical, we want to do it O(1)
 118  *
 119  * the indexing order of this array favors 1:1 mappings
 120  * between pins and IRQs.
 121  */
 122
 123 static struct irq_pin_list {
 124         int apic, pin, next;
 125 } irq_2_pin[PIN_MAP_SIZE];
 126
 127 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
 128 #ifdef CONFIG_PCI_MSI
 129 #define vector_to_irq(vector)   \
 130         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
 131 #else
 132 #define vector_to_irq(vector)   (vector)
 133 #endif
 134
 135 /*
 136  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 137  * shared ISA-space IRQs, so we have to support them. We are super
 138  * fast in the common case, and fast for shared ISA-space IRQs.
 139  */
 140 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 141 {
 142         static int first_free_entry = NR_IRQS;
 143         struct irq_pin_list *entry = irq_2_pin + irq;
 144
 145         while (entry->next)
 146                 entry = irq_2_pin + entry->next;
 147
 148         if (entry->pin != -1) {
 149                 entry->next = first_free_entry;
 150                 entry = irq_2_pin + entry->next;
 151                 if (++first_free_entry >= PIN_MAP_SIZE)
 152                         panic("io_apic.c: whoops");
 153         }
 154         entry->apic = apic;
 155         entry->pin = pin;
 156 }
 157
 158 #ifdef CONFIG_XEN
 159 #define clear_IO_APIC() ((void)0)
 160 #else
 161 /*
 162  * Reroute an IRQ to a different pin.
 163  */
 164 static void __init replace_pin_at_irq(unsigned int irq,
 165                                       int oldapic, int oldpin,
 166                                       int newapic, int newpin)
 167 {
 168         struct irq_pin_list *entry = irq_2_pin + irq;
 169
 170         while (1) {
 171                 if (entry->apic == oldapic && entry->pin == oldpin) {
 172                         entry->apic = newapic;
 173                         entry->pin = newpin;
 174                 }
 175                 if (!entry->next)
 176                         break;
 177                 entry = irq_2_pin + entry->next;
 178         }
 179 }
 180
 181 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 182 {
 183         struct irq_pin_list *entry = irq_2_pin + irq;
 184         unsigned int pin, reg;
 185
 186         for (;;) {
 187                 pin = entry->pin;
 188                 if (pin == -1)
 189                         break;
 190                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 191                 reg &= ~disable;
 192                 reg |= enable;
 193                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 194                 if (!entry->next)
 195                         break;
 196                 entry = irq_2_pin + entry->next;
 197         }
 198 }
 199
 200 /* mask = 1 */
 201 static void __mask_IO_APIC_irq (unsigned int irq)
 202 {
 203         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 204 }
 205
 206 /* mask = 0 */
 207 static void __unmask_IO_APIC_irq (unsigned int irq)
 208 {
 209         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 210 }
 211
 212 /* mask = 1, trigger = 0 */
 213 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 214 {
 215         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 216 }
 217
 218 /* mask = 0, trigger = 1 */
 219 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 220 {
 221         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 222 }
 223
 224 static void mask_IO_APIC_irq (unsigned int irq)
 225 {
 226         unsigned long flags;
 227
 228         spin_lock_irqsave(&ioapic_lock, flags);
 229         __mask_IO_APIC_irq(irq);
 230         spin_unlock_irqrestore(&ioapic_lock, flags);
 231 }
 232
 233 static void unmask_IO_APIC_irq (unsigned int irq)
 234 {
 235         unsigned long flags;
 236
 237         spin_lock_irqsave(&ioapic_lock, flags);
 238         __unmask_IO_APIC_irq(irq);
 239         spin_unlock_irqrestore(&ioapic_lock, flags);
 240 }
 241
 242 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 243 {
 244         struct IO_APIC_route_entry entry;
 245         unsigned long flags;
 246
 247         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 248         spin_lock_irqsave(&ioapic_lock, flags);
 249         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 250         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 251         spin_unlock_irqrestore(&ioapic_lock, flags);
 252         if (entry.delivery_mode == dest_SMI)
 253                 return;
 254
 255         /*
 256          * Disable it in the IO-APIC irq-routing table:
 257          */
 258         memset(&entry, 0, sizeof(entry));
 259         entry.mask = 1;
 260         spin_lock_irqsave(&ioapic_lock, flags);
 261         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 262         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 263         spin_unlock_irqrestore(&ioapic_lock, flags);
 264 }
 265
 266 static void clear_IO_APIC (void)
 267 {
 268         int apic, pin;
 269
 270         for (apic = 0; apic < nr_ioapics; apic++)
 271                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 272                         clear_IO_APIC_pin(apic, pin);
 273 }
 274
 275 #ifdef CONFIG_SMP
 276 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 277 {
 278         unsigned long flags;
 279         int pin;
 280         struct irq_pin_list *entry = irq_2_pin + irq;
 281         unsigned int apicid_value;
 282         cpumask_t tmp;
 283
 284         cpus_and(tmp, cpumask, cpu_online_map);
 285         if (cpus_empty(tmp))
 286                 tmp = TARGET_CPUS;
 287
 288         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 289
 290         apicid_value = cpu_mask_to_apicid(cpumask);
 291         /* Prepare to do the io_apic_write */
 292         apicid_value = apicid_value << 24;
 293         spin_lock_irqsave(&ioapic_lock, flags);
 294         for (;;) {
 295                 pin = entry->pin;
 296                 if (pin == -1)
 297                         break;
 298                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 299                 if (!entry->next)
 300                         break;
 301                 entry = irq_2_pin + entry->next;
 302         }
 303         set_irq_info(irq, cpumask);
 304         spin_unlock_irqrestore(&ioapic_lock, flags);
 305 }
 306
 307 #if defined(CONFIG_IRQBALANCE)
 308 # include <asm/processor.h>     /* kernel_thread() */
 309 # include <linux/kernel_stat.h> /* kstat */
 310 # include <linux/slab.h>                /* kmalloc() */
 311 # include <linux/timer.h>       /* time_after() */
 312
 313 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 314 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 315 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 316 # else
 317 #  define TDprintk(x...)
 318 #  define Dprintk(x...)
 319 # endif
 320
 321
 322 #define IRQBALANCE_CHECK_ARCH -999
 323 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 324 static int physical_balance = 0;
 325
 326 static struct irq_cpu_info {
 327         unsigned long * last_irq;
 328         unsigned long * irq_delta;
 329         unsigned long irq;
 330 } irq_cpu_data[NR_CPUS];
 331
 332 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 333 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 334 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 335
 336 #define IDLE_ENOUGH(cpu,now) \
 337         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 338
 339 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 340
 341 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 342
 343 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 344 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 345 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 346 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 347
 348 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 349
 350 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 351                         unsigned long now, int direction)
 352 {
 353         int search_idle = 1;
 354         int cpu = curr_cpu;
 355
 356         goto inside;
 357
 358         do {
 359                 if (unlikely(cpu == curr_cpu))
 360                         search_idle = 0;
 361 inside:
 362                 if (direction == 1) {
 363                         cpu++;
 364                         if (cpu >= NR_CPUS)
 365                                 cpu = 0;
 366                 } else {
 367                         cpu--;
 368                         if (cpu == -1)
 369                                 cpu = NR_CPUS-1;
 370                 }
 371         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 372                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 373
 374         return cpu;
 375 }
 376
 377 static inline void balance_irq(int cpu, int irq)
 378 {
 379         unsigned long now = jiffies;
 380         cpumask_t allowed_mask;
 381         unsigned int new_cpu;
 382
 383         if (irqbalance_disabled)
 384                 return;
 385
 386         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 387         new_cpu = move(cpu, allowed_mask, now, 1);
 388         if (cpu != new_cpu) {
 389                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 390         }
 391 }
 392
 393 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 394 {
 395         int i, j;
 396         Dprintk("Rotating IRQs among CPUs.\n");
 397         for_each_online_cpu(i) {
 398                 for (j = 0; j < NR_IRQS; j++) {
 399                         if (!irq_desc[j].action)
 400                                 continue;
 401                         /* Is it a significant load ?  */
 402                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 403                                                 useful_load_threshold)
 404                                 continue;
 405                         balance_irq(i, j);
 406                 }
 407         }
 408         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 409                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 410         return;
 411 }
 412
 413 static void do_irq_balance(void)
 414 {
 415         int i, j;
 416         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 417         unsigned long move_this_load = 0;
 418         int max_loaded = 0, min_loaded = 0;
 419         int load;
 420         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 421         int selected_irq;
 422         int tmp_loaded, first_attempt = 1;
 423         unsigned long tmp_cpu_irq;
 424         unsigned long imbalance = 0;
 425         cpumask_t allowed_mask, target_cpu_mask, tmp;
 426
 427         for_each_possible_cpu(i) {
 428                 int package_index;
 429                 CPU_IRQ(i) = 0;
 430                 if (!cpu_online(i))
 431                         continue;
 432                 package_index = CPU_TO_PACKAGEINDEX(i);
 433                 for (j = 0; j < NR_IRQS; j++) {
 434                         unsigned long value_now, delta;
 435                         /* Is this an active IRQ? */
 436                         if (!irq_desc[j].action)
 437                                 continue;
 438                         if ( package_index == i )
 439                                 IRQ_DELTA(package_index,j) = 0;
 440                         /* Determine the total count per processor per IRQ */
 441                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 442
 443                         /* Determine the activity per processor per IRQ */
 444                         delta = value_now - LAST_CPU_IRQ(i,j);
 445
 446                         /* Update last_cpu_irq[][] for the next time */
 447                         LAST_CPU_IRQ(i,j) = value_now;
 448
 449                         /* Ignore IRQs whose rate is less than the clock */
 450                         if (delta < useful_load_threshold)
 451                                 continue;
 452                         /* update the load for the processor or package total */
 453                         IRQ_DELTA(package_index,j) += delta;
 454
 455                         /* Keep track of the higher numbered sibling as well */
 456                         if (i != package_index)
 457                                 CPU_IRQ(i) += delta;
 458                         /*
 459                          * We have sibling A and sibling B in the package
 460                          *
 461                          * cpu_irq[A] = load for cpu A + load for cpu B
 462                          * cpu_irq[B] = load for cpu B
 463                          */
 464                         CPU_IRQ(package_index) += delta;
 465                 }
 466         }
 467         /* Find the least loaded processor package */
 468         for_each_online_cpu(i) {
 469                 if (i != CPU_TO_PACKAGEINDEX(i))
 470                         continue;
 471                 if (min_cpu_irq > CPU_IRQ(i)) {
 472                         min_cpu_irq = CPU_IRQ(i);
 473                         min_loaded = i;
 474                 }
 475         }
 476         max_cpu_irq = ULONG_MAX;
 477
 478 tryanothercpu:
 479         /* Look for heaviest loaded processor.
 480          * We may come back to get the next heaviest loaded processor.
 481          * Skip processors with trivial loads.
 482          */
 483         tmp_cpu_irq = 0;
 484         tmp_loaded = -1;
 485         for_each_online_cpu(i) {
 486                 if (i != CPU_TO_PACKAGEINDEX(i))
 487                         continue;
 488                 if (max_cpu_irq <= CPU_IRQ(i))
 489                         continue;
 490                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 491                         tmp_cpu_irq = CPU_IRQ(i);
 492                         tmp_loaded = i;
 493                 }
 494         }
 495
 496         if (tmp_loaded == -1) {
 497          /* In the case of small number of heavy interrupt sources,
 498           * loading some of the cpus too much. We use Ingo's original
 499           * approach to rotate them around.
 500           */
 501                 if (!first_attempt && imbalance >= useful_load_threshold) {
 502                         rotate_irqs_among_cpus(useful_load_threshold);
 503                         return;
 504                 }
 505                 goto not_worth_the_effort;
 506         }
 507
 508         first_attempt = 0;              /* heaviest search */
 509         max_cpu_irq = tmp_cpu_irq;      /* load */
 510         max_loaded = tmp_loaded;        /* processor */
 511         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 512
 513         Dprintk("max_loaded cpu = %d\n", max_loaded);
 514         Dprintk("min_loaded cpu = %d\n", min_loaded);
 515         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 516         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 517         Dprintk("load imbalance = %lu\n", imbalance);
 518
 519         /* if imbalance is less than approx 10% of max load, then
 520          * observe diminishing returns action. - quit
 521          */
 522         if (imbalance < (max_cpu_irq >> 3)) {
 523                 Dprintk("Imbalance too trivial\n");
 524                 goto not_worth_the_effort;
 525         }
 526
 527 tryanotherirq:
 528         /* if we select an IRQ to move that can't go where we want, then
 529          * see if there is another one to try.
 530          */
 531         move_this_load = 0;
 532         selected_irq = -1;
 533         for (j = 0; j < NR_IRQS; j++) {
 534                 /* Is this an active IRQ? */
 535                 if (!irq_desc[j].action)
 536                         continue;
 537                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 538                         continue;
 539                 /* Try to find the IRQ that is closest to the imbalance
 540                  * without going over.
 541                  */
 542                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 543                         move_this_load = IRQ_DELTA(max_loaded,j);
 544                         selected_irq = j;
 545                 }
 546         }
 547         if (selected_irq == -1) {
 548                 goto tryanothercpu;
 549         }
 550
 551         imbalance = move_this_load;
 552
 553         /* For physical_balance case, we accumlated both load
 554          * values in the one of the siblings cpu_irq[],
 555          * to use the same code for physical and logical processors
 556          * as much as possible.
 557          *
 558          * NOTE: the cpu_irq[] array holds the sum of the load for
 559          * sibling A and sibling B in the slot for the lowest numbered
 560          * sibling (A), _AND_ the load for sibling B in the slot for
 561          * the higher numbered sibling.
 562          *
 563          * We seek the least loaded sibling by making the comparison
 564          * (A+B)/2 vs B
 565          */
 566         load = CPU_IRQ(min_loaded) >> 1;
 567         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 568                 if (load > CPU_IRQ(j)) {
 569                         /* This won't change cpu_sibling_map[min_loaded] */
 570                         load = CPU_IRQ(j);
 571                         min_loaded = j;
 572                 }
 573         }
 574
 575         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 576         target_cpu_mask = cpumask_of_cpu(min_loaded);
 577         cpus_and(tmp, target_cpu_mask, allowed_mask);
 578
 579         if (!cpus_empty(tmp)) {
 580
 581                 Dprintk("irq = %d moved to cpu = %d\n",
 582                                 selected_irq, min_loaded);
 583                 /* mark for change destination */
 584                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 585
 586                 /* Since we made a change, come back sooner to
 587                  * check for more variation.
 588                  */
 589                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 590                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 591                 return;
 592         }
 593         goto tryanotherirq;
 594
 595 not_worth_the_effort:
 596         /*
 597          * if we did not find an IRQ to move, then adjust the time interval
 598          * upward
 599          */
 600         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 601                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 602         Dprintk("IRQ worth rotating not found\n");
 603         return;
 604 }
 605
 606 static int balanced_irq(void *unused)
 607 {
 608         int i;
 609         unsigned long prev_balance_time = jiffies;
 610         long time_remaining = balanced_irq_interval;
 611
 612         daemonize("kirqd");
 613
 614         /* push everything to CPU 0 to give us a starting point.  */
 615         for (i = 0 ; i < NR_IRQS ; i++) {
 616                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
 617                 set_pending_irq(i, cpumask_of_cpu(0));
 618         }
 619
 620         for ( ; ; ) {
 621                 time_remaining = schedule_timeout_interruptible(time_remaining);
 622                 try_to_freeze();
 623                 if (time_after(jiffies,
 624                                 prev_balance_time+balanced_irq_interval)) {
 625                         preempt_disable();
 626                         do_irq_balance();
 627                         prev_balance_time = jiffies;
 628                         time_remaining = balanced_irq_interval;
 629                         preempt_enable();
 630                 }
 631         }
 632         return 0;
 633 }
 634
 635 static int __init balanced_irq_init(void)
 636 {
 637         int i;
 638         struct cpuinfo_x86 *c;
 639         cpumask_t tmp;
 640
 641         cpus_shift_right(tmp, cpu_online_map, 2);
 642         c = &boot_cpu_data;
 643         /* When not overwritten by the command line ask subarchitecture. */
 644         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 645                 irqbalance_disabled = NO_BALANCE_IRQ;
 646         if (irqbalance_disabled)
 647                 return 0;
 648
 649          /* disable irqbalance completely if there is only one processor online */
 650         if (num_online_cpus() < 2) {
 651                 irqbalance_disabled = 1;
 652                 return 0;
 653         }
 654         /*
 655          * Enable physical balance only if more than 1 physical processor
 656          * is present
 657          */
 658         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 659                 physical_balance = 1;
 660
 661         for_each_online_cpu(i) {
 662                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 663                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 664                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 665                         printk(KERN_ERR "balanced_irq_init: out of memory");
 666                         goto failed;
 667                 }
 668                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 669                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 670         }
 671
 672         printk(KERN_INFO "Starting balanced_irq\n");
 673         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 674                 return 0;
 675         else
 676                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 677 failed:
 678         for_each_possible_cpu(i) {
 679                 kfree(irq_cpu_data[i].irq_delta);
 680                 irq_cpu_data[i].irq_delta = NULL;
 681                 kfree(irq_cpu_data[i].last_irq);
 682                 irq_cpu_data[i].last_irq = NULL;
 683         }
 684         return 0;
 685 }
 686
 687 int __init irqbalance_disable(char *str)
 688 {
 689         irqbalance_disabled = 1;
 690         return 1;
 691 }
 692
 693 __setup("noirqbalance", irqbalance_disable);
 694
 695 late_initcall(balanced_irq_init);
 696 #endif /* CONFIG_IRQBALANCE */
 697 #endif /* CONFIG_SMP */
 698 #endif
 699
 700 #ifndef CONFIG_SMP
 701 void fastcall send_IPI_self(int vector)
 702 {
 703 #ifndef CONFIG_XEN
 704         unsigned int cfg;
 705
 706         /*
 707          * Wait for idle.
 708          */
 709         apic_wait_icr_idle();
 710         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 711         /*
 712          * Send the IPI. The write to APIC_ICR fires this off.
 713          */
 714         apic_write_around(APIC_ICR, cfg);
 715 #endif
 716 }
 717 #endif /* !CONFIG_SMP */
 718
 719
 720 /*
 721  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 722  * specific CPU-side IRQs.
 723  */
 724
 725 #define MAX_PIRQS 8
 726 static int pirq_entries [MAX_PIRQS];
 727 static int pirqs_enabled;
 728 int skip_ioapic_setup;
 729
 730 static int __init ioapic_setup(char *str)
 731 {
 732         skip_ioapic_setup = 1;
 733         return 1;
 734 }
 735
 736 __setup("noapic", ioapic_setup);
 737
 738 static int __init ioapic_pirq_setup(char *str)
 739 {
 740         int i, max;
 741         int ints[MAX_PIRQS+1];
 742
 743         get_options(str, ARRAY_SIZE(ints), ints);
 744
 745         for (i = 0; i < MAX_PIRQS; i++)
 746                 pirq_entries[i] = -1;
 747
 748         pirqs_enabled = 1;
 749         apic_printk(APIC_VERBOSE, KERN_INFO
 750                         "PIRQ redirection, working around broken MP-BIOS.\n");
 751         max = MAX_PIRQS;
 752         if (ints[0] < MAX_PIRQS)
 753                 max = ints[0];
 754
 755         for (i = 0; i < max; i++) {
 756                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 757                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 758                 /*
 759                  * PIRQs are mapped upside down, usually.
 760                  */
 761                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 762         }
 763         return 1;
 764 }
 765
 766 __setup("pirq=", ioapic_pirq_setup);
 767
 768 /*
 769  * Find the IRQ entry number of a certain pin.
 770  */
 771 static int find_irq_entry(int apic, int pin, int type)
 772 {
 773         int i;
 774
 775         for (i = 0; i < mp_irq_entries; i++)
 776                 if (mp_irqs[i].mpc_irqtype == type &&
 777                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 778                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 779                     mp_irqs[i].mpc_dstirq == pin)
 780                         return i;
 781
 782         return -1;
 783 }
 784
 785 /*
 786  * Find the pin to which IRQ[irq] (ISA) is connected
 787  */
 788 static int __init find_isa_irq_pin(int irq, int type)
 789 {
 790         int i;
 791
 792         for (i = 0; i < mp_irq_entries; i++) {
 793                 int lbus = mp_irqs[i].mpc_srcbus;
 794
 795                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 796                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 797                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 798                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 799                     ) &&
 800                     (mp_irqs[i].mpc_irqtype == type) &&
 801                     (mp_irqs[i].mpc_srcbusirq == irq))
 802
 803                         return mp_irqs[i].mpc_dstirq;
 804         }
 805         return -1;
 806 }
 807
 808 static int __init find_isa_irq_apic(int irq, int type)
 809 {
 810         int i;
 811
 812         for (i = 0; i < mp_irq_entries; i++) {
 813                 int lbus = mp_irqs[i].mpc_srcbus;
 814
 815                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 816                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 817                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 818                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 819                     ) &&
 820                     (mp_irqs[i].mpc_irqtype == type) &&
 821                     (mp_irqs[i].mpc_srcbusirq == irq))
 822                         break;
 823         }
 824         if (i < mp_irq_entries) {
 825                 int apic;
 826                 for(apic = 0; apic < nr_ioapics; apic++) {
 827                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 828                                 return apic;
 829                 }
 830         }
 831
 832         return -1;
 833 }
 834
 835 /*
 836  * Find a specific PCI IRQ entry.
 837  * Not an __init, possibly needed by modules
 838  */
 839 static int pin_2_irq(int idx, int apic, int pin);
 840
 841 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 842 {
 843         int apic, i, best_guess = -1;
 844
 845         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 846                 "slot:%d, pin:%d.\n", bus, slot, pin);
 847         if (mp_bus_id_to_pci_bus[bus] == -1) {
 848                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 849                 return -1;
 850         }
 851         for (i = 0; i < mp_irq_entries; i++) {
 852                 int lbus = mp_irqs[i].mpc_srcbus;
 853
 854                 for (apic = 0; apic < nr_ioapics; apic++)
 855                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 856                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 857                                 break;
 858
 859                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 860                     !mp_irqs[i].mpc_irqtype &&
 861                     (bus == lbus) &&
 862                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 863                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 864
 865                         if (!(apic || IO_APIC_IRQ(irq)))
 866                                 continue;
 867
 868                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 869                                 return irq;
 870                         /*
 871                          * Use the first all-but-pin matching entry as a
 872                          * best-guess fuzzy result for broken mptables.
 873                          */
 874                         if (best_guess < 0)
 875                                 best_guess = irq;
 876                 }
 877         }
 878         return best_guess;
 879 }
 880 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 881
 882 /*
 883  * This function currently is only a helper for the i386 smp boot process where
 884  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 885  * so mask in all cases should simply be TARGET_CPUS
 886  */
 887 #ifdef CONFIG_SMP
 888 #ifndef CONFIG_XEN
 889 void __init setup_ioapic_dest(void)
 890 {
 891         int pin, ioapic, irq, irq_entry;
 892
 893         if (skip_ioapic_setup == 1)
 894                 return;
 895
 896         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 897                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 898                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 899                         if (irq_entry == -1)
 900                                 continue;
 901                         irq = pin_2_irq(irq_entry, ioapic, pin);
 902                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 903                 }
 904
 905         }
 906 }
 907 #endif /* !CONFIG_XEN */
 908 #endif
 909
 910 /*
 911  * EISA Edge/Level control register, ELCR
 912  */
 913 static int EISA_ELCR(unsigned int irq)
 914 {
 915         if (irq < 16) {
 916                 unsigned int port = 0x4d0 + (irq >> 3);
 917                 return (inb(port) >> (irq & 7)) & 1;
 918         }
 919         apic_printk(APIC_VERBOSE, KERN_INFO
 920                         "Broken MPtable reports ISA irq %d\n", irq);
 921         return 0;
 922 }
 923
 924 /* EISA interrupts are always polarity zero and can be edge or level
 925  * trigger depending on the ELCR value.  If an interrupt is listed as
 926  * EISA conforming in the MP table, that means its trigger type must
 927  * be read in from the ELCR */
 928
 929 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 930 #define default_EISA_polarity(idx)      (0)
 931
 932 /* ISA interrupts are always polarity zero edge triggered,
 933  * when listed as conforming in the MP table. */
 934
 935 #define default_ISA_trigger(idx)        (0)
 936 #define default_ISA_polarity(idx)       (0)
 937
 938 /* PCI interrupts are always polarity one level triggered,
 939  * when listed as conforming in the MP table. */
 940
 941 #define default_PCI_trigger(idx)        (1)
 942 #define default_PCI_polarity(idx)       (1)
 943
 944 /* MCA interrupts are always polarity zero level triggered,
 945  * when listed as conforming in the MP table. */
 946
 947 #define default_MCA_trigger(idx)        (1)
 948 #define default_MCA_polarity(idx)       (0)
 949
 950 /* NEC98 interrupts are always polarity zero edge triggered,
 951  * when listed as conforming in the MP table. */
 952
 953 #define default_NEC98_trigger(idx)     (0)
 954 #define default_NEC98_polarity(idx)    (0)
 955
 956 static int __init MPBIOS_polarity(int idx)
 957 {
 958         int bus = mp_irqs[idx].mpc_srcbus;
 959         int polarity;
 960
 961         /*
 962          * Determine IRQ line polarity (high active or low active):
 963          */
 964         switch (mp_irqs[idx].mpc_irqflag & 3)
 965         {
 966                 case 0: /* conforms, ie. bus-type dependent polarity */
 967                 {
 968                         switch (mp_bus_id_to_type[bus])
 969                         {
 970                                 case MP_BUS_ISA: /* ISA pin */
 971                                 {
 972                                         polarity = default_ISA_polarity(idx);
 973                                         break;
 974                                 }
 975                                 case MP_BUS_EISA: /* EISA pin */
 976                                 {
 977                                         polarity = default_EISA_polarity(idx);
 978                                         break;
 979                                 }
 980                                 case MP_BUS_PCI: /* PCI pin */
 981                                 {
 982                                         polarity = default_PCI_polarity(idx);
 983                                         break;
 984                                 }
 985                                 case MP_BUS_MCA: /* MCA pin */
 986                                 {
 987                                         polarity = default_MCA_polarity(idx);
 988                                         break;
 989                                 }
 990                                 case MP_BUS_NEC98: /* NEC 98 pin */
 991                                 {
 992                                         polarity = default_NEC98_polarity(idx);
 993                                         break;
 994                                 }
 995                                 default:
 996                                 {
 997                                         printk(KERN_WARNING "broken BIOS!!\n");
 998                                         polarity = 1;
 999                                         break;
1000                                 }
1001                         }
1002                         break;
1003                 }
1004                 case 1: /* high active */
1005                 {
1006                         polarity = 0;
1007                         break;
1008                 }
1009                 case 2: /* reserved */
1010                 {
1011                         printk(KERN_WARNING "broken BIOS!!\n");
1012                         polarity = 1;
1013                         break;
1014                 }
1015                 case 3: /* low active */
1016                 {
1017                         polarity = 1;
1018                         break;
1019                 }
1020                 default: /* invalid */
1021                 {
1022                         printk(KERN_WARNING "broken BIOS!!\n");
1023                         polarity = 1;
1024                         break;
1025                 }
1026         }
1027         return polarity;
1028 }
1029
1030 static int MPBIOS_trigger(int idx)
1031 {
1032         int bus = mp_irqs[idx].mpc_srcbus;
1033         int trigger;
1034
1035         /*
1036          * Determine IRQ trigger mode (edge or level sensitive):
1037          */
1038         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1039         {
1040                 case 0: /* conforms, ie. bus-type dependent */
1041                 {
1042                         switch (mp_bus_id_to_type[bus])
1043                         {
1044                                 case MP_BUS_ISA: /* ISA pin */
1045                                 {
1046                                         trigger = default_ISA_trigger(idx);
1047                                         break;
1048                                 }
1049                                 case MP_BUS_EISA: /* EISA pin */
1050                                 {
1051                                         trigger = default_EISA_trigger(idx);
1052                                         break;
1053                                 }
1054                                 case MP_BUS_PCI: /* PCI pin */
1055                                 {
1056                                         trigger = default_PCI_trigger(idx);
1057                                         break;
1058                                 }
1059                                 case MP_BUS_MCA: /* MCA pin */
1060                                 {
1061                                         trigger = default_MCA_trigger(idx);
1062                                         break;
1063                                 }
1064                                 case MP_BUS_NEC98: /* NEC 98 pin */
1065                                 {
1066                                         trigger = default_NEC98_trigger(idx);
1067                                         break;
1068                                 }
1069                                 default:
1070                                 {
1071                                         printk(KERN_WARNING "broken BIOS!!\n");
1072                                         trigger = 1;
1073                                         break;
1074                                 }
1075                         }
1076                         break;
1077                 }
1078                 case 1: /* edge */
1079                 {
1080                         trigger = 0;
1081                         break;
1082                 }
1083                 case 2: /* reserved */
1084                 {
1085                         printk(KERN_WARNING "broken BIOS!!\n");
1086                         trigger = 1;
1087                         break;
1088                 }
1089                 case 3: /* level */
1090                 {
1091                         trigger = 1;
1092                         break;
1093                 }
1094                 default: /* invalid */
1095                 {
1096                         printk(KERN_WARNING "broken BIOS!!\n");
1097                         trigger = 0;
1098                         break;
1099                 }
1100         }
1101         return trigger;
1102 }
1103
1104 static inline int irq_polarity(int idx)
1105 {
1106         return MPBIOS_polarity(idx);
1107 }
1108
1109 static inline int irq_trigger(int idx)
1110 {
1111         return MPBIOS_trigger(idx);
1112 }
1113
1114 static int pin_2_irq(int idx, int apic, int pin)
1115 {
1116         int irq, i;
1117         int bus = mp_irqs[idx].mpc_srcbus;
1118
1119         /*
1120          * Debugging check, we are in big trouble if this message pops up!
1121          */
1122         if (mp_irqs[idx].mpc_dstirq != pin)
1123                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1124
1125         switch (mp_bus_id_to_type[bus])
1126         {
1127                 case MP_BUS_ISA: /* ISA pin */
1128                 case MP_BUS_EISA:
1129                 case MP_BUS_MCA:
1130                 case MP_BUS_NEC98:
1131                 {
1132                         irq = mp_irqs[idx].mpc_srcbusirq;
1133                         break;
1134                 }
1135                 case MP_BUS_PCI: /* PCI pin */
1136                 {
1137                         /*
1138                          * PCI IRQs are mapped in order
1139                          */
1140                         i = irq = 0;
1141                         while (i < apic)
1142                                 irq += nr_ioapic_registers[i++];
1143                         irq += pin;
1144
1145                         /*
1146                          * For MPS mode, so far only needed by ES7000 platform
1147                          */
1148                         if (ioapic_renumber_irq)
1149                                 irq = ioapic_renumber_irq(apic, irq);
1150
1151                         break;
1152                 }
1153                 default:
1154                 {
1155                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1156                         irq = 0;
1157                         break;
1158                 }
1159         }
1160
1161         /*
1162          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1163          */
1164         if ((pin >= 16) && (pin <= 23)) {
1165                 if (pirq_entries[pin-16] != -1) {
1166                         if (!pirq_entries[pin-16]) {
1167                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1168                                                 "disabling PIRQ%d\n", pin-16);
1169                         } else {
1170                                 irq = pirq_entries[pin-16];
1171                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1172                                                 "using PIRQ%d -> IRQ %d\n",
1173                                                 pin-16, irq);
1174                         }
1175                 }
1176         }
1177         return irq;
1178 }
1179
1180 static inline int IO_APIC_irq_trigger(int irq)
1181 {
1182         int apic, idx, pin;
1183
1184         for (apic = 0; apic < nr_ioapics; apic++) {
1185                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1186                         idx = find_irq_entry(apic,pin,mp_INT);
1187                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1188                                 return irq_trigger(idx);
1189                 }
1190         }
1191         /*
1192          * nonexistent IRQs are edge default
1193          */
1194         return 0;
1195 }
1196
1197 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1198 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1199
1200 int assign_irq_vector(int irq)
1201 {
1202         struct physdev_irq irq_op;
1203
1204         BUG_ON(irq >= NR_IRQ_VECTORS);
1205         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1206                 return IO_APIC_VECTOR(irq);
1207
1208         irq_op.irq = irq;
1209         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
1210                 return -ENOSPC;
1211
1212         vector_irq[irq_op.vector] = irq;
1213         if (irq != AUTO_ASSIGN)
1214                 IO_APIC_VECTOR(irq) = irq_op.vector;
1215
1216         return irq_op.vector;
1217 }
1218
1219 #ifndef CONFIG_XEN
1220 static struct hw_interrupt_type ioapic_level_type;
1221 static struct hw_interrupt_type ioapic_edge_type;
1222
1223 #define IOAPIC_AUTO     -1
1224 #define IOAPIC_EDGE     0
1225 #define IOAPIC_LEVEL    1
1226
1227 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1228 {
1229         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1230                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1231                                 trigger == IOAPIC_LEVEL)
1232                         irq_desc[vector].handler = &ioapic_level_type;
1233                 else
1234                         irq_desc[vector].handler = &ioapic_edge_type;
1235                 set_intr_gate(vector, interrupt[vector]);
1236         } else  {
1237                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1238                                 trigger == IOAPIC_LEVEL)
1239                         irq_desc[irq].handler = &ioapic_level_type;
1240                 else
1241                         irq_desc[irq].handler = &ioapic_edge_type;
1242                 set_intr_gate(vector, interrupt[irq]);
1243         }
1244 }
1245 #else
1246 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
1247 #endif
1248
1249 static void __init setup_IO_APIC_irqs(void)
1250 {
1251         struct IO_APIC_route_entry entry;
1252         int apic, pin, idx, irq, first_notcon = 1, vector;
1253         unsigned long flags;
1254
1255         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1256
1257         for (apic = 0; apic < nr_ioapics; apic++) {
1258         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1259
1260                 /*
1261                  * add it to the IO-APIC irq-routing table:
1262                  */
1263                 memset(&entry,0,sizeof(entry));
1264
1265                 entry.delivery_mode = INT_DELIVERY_MODE;
1266                 entry.dest_mode = INT_DEST_MODE;
1267                 entry.mask = 0;                         /* enable IRQ */
1268                 entry.dest.logical.logical_dest =
1269                                         cpu_mask_to_apicid(TARGET_CPUS);
1270
1271                 idx = find_irq_entry(apic,pin,mp_INT);
1272                 if (idx == -1) {
1273                         if (first_notcon) {
1274                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1275                                                 " IO-APIC (apicid-pin) %d-%d",
1276                                                 mp_ioapics[apic].mpc_apicid,
1277                                                 pin);
1278                                 first_notcon = 0;
1279                         } else
1280                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1281                                         mp_ioapics[apic].mpc_apicid, pin);
1282                         continue;
1283                 }
1284
1285                 entry.trigger = irq_trigger(idx);
1286                 entry.polarity = irq_polarity(idx);
1287
1288                 if (irq_trigger(idx)) {
1289                         entry.trigger = 1;
1290                         entry.mask = 1;
1291                 }
1292
1293                 irq = pin_2_irq(idx, apic, pin);
1294                 /*
1295                  * skip adding the timer int on secondary nodes, which causes
1296                  * a small but painful rift in the time-space continuum
1297                  */
1298                 if (multi_timer_check(apic, irq))
1299                         continue;
1300                 else
1301                         add_pin_to_irq(irq, apic, pin);
1302
1303                 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1304                         continue;
1305
1306                 if (IO_APIC_IRQ(irq)) {
1307                         vector = assign_irq_vector(irq);
1308                         entry.vector = vector;
1309                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1310
1311                         if (!apic && (irq < 16))
1312                                 disable_8259A_irq(irq);
1313                 }
1314                 spin_lock_irqsave(&ioapic_lock, flags);
1315                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1316                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1317                 set_native_irq_info(irq, TARGET_CPUS);
1318                 spin_unlock_irqrestore(&ioapic_lock, flags);
1319         }
1320         }
1321
1322         if (!first_notcon)
1323                 apic_printk(APIC_VERBOSE, " not connected.\n");
1324 }
1325
1326 /*
1327  * Set up the 8259A-master output pin:
1328  */
1329 #ifndef CONFIG_XEN
1330 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1331 {
1332         struct IO_APIC_route_entry entry;
1333         unsigned long flags;
1334
1335         memset(&entry,0,sizeof(entry));
1336
1337         disable_8259A_irq(0);
1338
1339         /* mask LVT0 */
1340         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1341
1342         /*
1343          * We use logical delivery to get the timer IRQ
1344          * to the first CPU.
1345          */
1346         entry.dest_mode = INT_DEST_MODE;
1347         entry.mask = 0;                                 /* unmask IRQ now */
1348         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1349         entry.delivery_mode = INT_DELIVERY_MODE;
1350         entry.polarity = 0;
1351         entry.trigger = 0;
1352         entry.vector = vector;
1353
1354         /*
1355          * The timer IRQ doesn't have to know that behind the
1356          * scene we have a 8259A-master in AEOI mode ...
1357          */
1358         irq_desc[0].handler = &ioapic_edge_type;
1359
1360         /*
1361          * Add it to the IO-APIC irq-routing table:
1362          */
1363         spin_lock_irqsave(&ioapic_lock, flags);
1364         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1365         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1366         spin_unlock_irqrestore(&ioapic_lock, flags);
1367
1368         enable_8259A_irq(0);
1369 }
1370
1371 static inline void UNEXPECTED_IO_APIC(void)
1372 {
1373 }
1374
1375 void __init print_IO_APIC(void)
1376 {
1377         int apic, i;
1378         union IO_APIC_reg_00 reg_00;
1379         union IO_APIC_reg_01 reg_01;
1380         union IO_APIC_reg_02 reg_02;
1381         union IO_APIC_reg_03 reg_03;
1382         unsigned long flags;
1383
1384         if (apic_verbosity == APIC_QUIET)
1385                 return;
1386
1387         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1388         for (i = 0; i < nr_ioapics; i++)
1389                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1390                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1391
1392         /*
1393          * We are a bit conservative about what we expect.  We have to
1394          * know about every hardware change ASAP.
1395          */
1396         printk(KERN_INFO "testing the IO APIC.......................\n");
1397
1398         for (apic = 0; apic < nr_ioapics; apic++) {
1399
1400         spin_lock_irqsave(&ioapic_lock, flags);
1401         reg_00.raw = io_apic_read(apic, 0);
1402         reg_01.raw = io_apic_read(apic, 1);
1403         if (reg_01.bits.version >= 0x10)
1404                 reg_02.raw = io_apic_read(apic, 2);
1405         if (reg_01.bits.version >= 0x20)
1406                 reg_03.raw = io_apic_read(apic, 3);
1407         spin_unlock_irqrestore(&ioapic_lock, flags);
1408
1409         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1410         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1411         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1412         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1413         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1414         if (reg_00.bits.ID >= get_physical_broadcast())
1415                 UNEXPECTED_IO_APIC();
1416         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1417                 UNEXPECTED_IO_APIC();
1418
1419         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1420         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1421         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1422                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1423                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1424                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1425                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1426                 (reg_01.bits.entries != 0x2E) &&
1427                 (reg_01.bits.entries != 0x3F)
1428         )
1429                 UNEXPECTED_IO_APIC();
1430
1431         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1432         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1433         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1434                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1435                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1436                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1437                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1438         )
1439                 UNEXPECTED_IO_APIC();
1440         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1441                 UNEXPECTED_IO_APIC();
1442
1443         /*
1444          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1445          * but the value of reg_02 is read as the previous read register
1446          * value, so ignore it if reg_02 == reg_01.
1447          */
1448         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1449                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1450                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1451                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1452                         UNEXPECTED_IO_APIC();
1453         }
1454
1455         /*
1456          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1457          * or reg_03, but the value of reg_0[23] is read as the previous read
1458          * register value, so ignore it if reg_03 == reg_0[12].
1459          */
1460         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1461             reg_03.raw != reg_01.raw) {
1462                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1463                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1464                 if (reg_03.bits.__reserved_1)
1465                         UNEXPECTED_IO_APIC();
1466         }
1467
1468         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1469
1470         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1471                           " Stat Dest Deli Vect:   \n");
1472
1473         for (i = 0; i <= reg_01.bits.entries; i++) {
1474                 struct IO_APIC_route_entry entry;
1475
1476                 spin_lock_irqsave(&ioapic_lock, flags);
1477                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1478                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1479                 spin_unlock_irqrestore(&ioapic_lock, flags);
1480
1481                 printk(KERN_DEBUG " %02x %03X %02X  ",
1482                         i,
1483                         entry.dest.logical.logical_dest,
1484                         entry.dest.physical.physical_dest
1485                 );
1486
1487                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1488                         entry.mask,
1489                         entry.trigger,
1490                         entry.irr,
1491                         entry.polarity,
1492                         entry.delivery_status,
1493                         entry.dest_mode,
1494                         entry.delivery_mode,
1495                         entry.vector
1496                 );
1497         }
1498         }
1499         if (use_pci_vector())
1500                 printk(KERN_INFO "Using vector-based indexing\n");
1501         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1502         for (i = 0; i < NR_IRQS; i++) {
1503                 struct irq_pin_list *entry = irq_2_pin + i;
1504                 if (entry->pin < 0)
1505                         continue;
1506                 if (use_pci_vector() && !platform_legacy_irq(i))
1507                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1508                 else
1509                         printk(KERN_DEBUG "IRQ%d ", i);
1510                 for (;;) {
1511                         printk("-> %d:%d", entry->apic, entry->pin);
1512                         if (!entry->next)
1513                                 break;
1514                         entry = irq_2_pin + entry->next;
1515                 }
1516                 printk("\n");
1517         }
1518
1519         printk(KERN_INFO ".................................... done.\n");
1520
1521         return;
1522 }
1523
1524 #if 0
1525
1526 static void print_APIC_bitfield (int base)
1527 {
1528         unsigned int v;
1529         int i, j;
1530
1531         if (apic_verbosity == APIC_QUIET)
1532                 return;
1533
1534         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1535         for (i = 0; i < 8; i++) {
1536                 v = apic_read(base + i*0x10);
1537                 for (j = 0; j < 32; j++) {
1538                         if (v & (1<<j))
1539                                 printk("1");
1540                         else
1541                                 printk("0");
1542                 }
1543                 printk("\n");
1544         }
1545 }
1546
1547 void /*__init*/ print_local_APIC(void * dummy)
1548 {
1549         unsigned int v, ver, maxlvt;
1550
1551         if (apic_verbosity == APIC_QUIET)
1552                 return;
1553
1554         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1555                 smp_processor_id(), hard_smp_processor_id());
1556         v = apic_read(APIC_ID);
1557         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1558         v = apic_read(APIC_LVR);
1559         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1560         ver = GET_APIC_VERSION(v);
1561         maxlvt = get_maxlvt();
1562
1563         v = apic_read(APIC_TASKPRI);
1564         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1565
1566         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1567                 v = apic_read(APIC_ARBPRI);
1568                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1569                         v & APIC_ARBPRI_MASK);
1570                 v = apic_read(APIC_PROCPRI);
1571                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1572         }
1573
1574         v = apic_read(APIC_EOI);
1575         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1576         v = apic_read(APIC_RRR);
1577         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1578         v = apic_read(APIC_LDR);
1579         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1580         v = apic_read(APIC_DFR);
1581         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1582         v = apic_read(APIC_SPIV);
1583         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1584
1585         printk(KERN_DEBUG "... APIC ISR field:\n");
1586         print_APIC_bitfield(APIC_ISR);
1587         printk(KERN_DEBUG "... APIC TMR field:\n");
1588         print_APIC_bitfield(APIC_TMR);
1589         printk(KERN_DEBUG "... APIC IRR field:\n");
1590         print_APIC_bitfield(APIC_IRR);
1591
1592         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1593                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1594                         apic_write(APIC_ESR, 0);
1595                 v = apic_read(APIC_ESR);
1596                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1597         }
1598
1599         v = apic_read(APIC_ICR);
1600         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1601         v = apic_read(APIC_ICR2);
1602         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1603
1604         v = apic_read(APIC_LVTT);
1605         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1606
1607         if (maxlvt > 3) {                       /* PC is LVT#4. */
1608                 v = apic_read(APIC_LVTPC);
1609                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1610         }
1611         v = apic_read(APIC_LVT0);
1612         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1613         v = apic_read(APIC_LVT1);
1614         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1615
1616         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1617                 v = apic_read(APIC_LVTERR);
1618                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1619         }
1620
1621         v = apic_read(APIC_TMICT);
1622         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1623         v = apic_read(APIC_TMCCT);
1624         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1625         v = apic_read(APIC_TDCR);
1626         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1627         printk("\n");
1628 }
1629
1630 void print_all_local_APICs (void)
1631 {
1632         on_each_cpu(print_local_APIC, NULL, 1, 1);
1633 }
1634
1635 void /*__init*/ print_PIC(void)
1636 {
1637         unsigned int v;
1638         unsigned long flags;
1639
1640         if (apic_verbosity == APIC_QUIET)
1641                 return;
1642
1643         printk(KERN_DEBUG "\nprinting PIC contents\n");
1644
1645         spin_lock_irqsave(&i8259A_lock, flags);
1646
1647         v = inb(0xa1) << 8 | inb(0x21);
1648         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1649
1650         v = inb(0xa0) << 8 | inb(0x20);
1651         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1652
1653         outb(0x0b,0xa0);
1654         outb(0x0b,0x20);
1655         v = inb(0xa0) << 8 | inb(0x20);
1656         outb(0x0a,0xa0);
1657         outb(0x0a,0x20);
1658
1659         spin_unlock_irqrestore(&i8259A_lock, flags);
1660
1661         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1662
1663         v = inb(0x4d1) << 8 | inb(0x4d0);
1664         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1665 }
1666
1667 #endif  /*  0  */
1668
1669 #else
1670 void __init print_IO_APIC(void) { }
1671 #endif /* !CONFIG_XEN */
1672
1673 static void __init enable_IO_APIC(void)
1674 {
1675         union IO_APIC_reg_01 reg_01;
1676         int i8259_apic, i8259_pin;
1677         int i, apic;
1678         unsigned long flags;
1679
1680         for (i = 0; i < PIN_MAP_SIZE; i++) {
1681                 irq_2_pin[i].pin = -1;
1682                 irq_2_pin[i].next = 0;
1683         }
1684         if (!pirqs_enabled)
1685                 for (i = 0; i < MAX_PIRQS; i++)
1686                         pirq_entries[i] = -1;
1687
1688         /*
1689          * The number of IO-APIC IRQ registers (== #pins):
1690          */
1691         for (apic = 0; apic < nr_ioapics; apic++) {
1692                 spin_lock_irqsave(&ioapic_lock, flags);
1693                 reg_01.raw = io_apic_read(apic, 1);
1694                 spin_unlock_irqrestore(&ioapic_lock, flags);
1695                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1696         }
1697         for(apic = 0; apic < nr_ioapics; apic++) {
1698                 int pin;
1699                 /* See if any of the pins is in ExtINT mode */
1700                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1701                         struct IO_APIC_route_entry entry;
1702                         spin_lock_irqsave(&ioapic_lock, flags);
1703                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1704                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1705                         spin_unlock_irqrestore(&ioapic_lock, flags);
1706
1707
1708                         /* If the interrupt line is enabled and in ExtInt mode
1709                          * I have found the pin where the i8259 is connected.
1710                          */
1711                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1712                                 ioapic_i8259.apic = apic;
1713                                 ioapic_i8259.pin  = pin;
1714                                 goto found_i8259;
1715                         }
1716                 }
1717         }
1718  found_i8259:
1719         /* Look to see what if the MP table has reported the ExtINT */
1720         /* If we could not find the appropriate pin by looking at the ioapic
1721          * the i8259 probably is not connected the ioapic but give the
1722          * mptable a chance anyway.
1723          */
1724         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1725         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1726         /* Trust the MP table if nothing is setup in the hardware */
1727         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1728                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1729                 ioapic_i8259.pin  = i8259_pin;
1730                 ioapic_i8259.apic = i8259_apic;
1731         }
1732         /* Complain if the MP table and the hardware disagree */
1733         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1734                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1735         {
1736                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1737         }
1738
1739         /*
1740          * Do not trust the IO-APIC being empty at bootup
1741          */
1742         clear_IO_APIC();
1743 }
1744
1745 /*
1746  * Not an __init, needed by the reboot code
1747  */
1748 void disable_IO_APIC(void)
1749 {
1750         /*
1751          * Clear the IO-APIC before rebooting:
1752          */
1753         clear_IO_APIC();
1754
1755 #ifndef CONFIG_XEN
1756         /*
1757          * If the i8259 is routed through an IOAPIC
1758          * Put that IOAPIC in virtual wire mode
1759          * so legacy interrupts can be delivered.
1760          */
1761         if (ioapic_i8259.pin != -1) {
1762                 struct IO_APIC_route_entry entry;
1763                 unsigned long flags;
1764
1765                 memset(&entry, 0, sizeof(entry));
1766                 entry.mask            = 0; /* Enabled */
1767                 entry.trigger         = 0; /* Edge */
1768                 entry.irr             = 0;
1769                 entry.polarity        = 0; /* High */
1770                 entry.delivery_status = 0;
1771                 entry.dest_mode       = 0; /* Physical */
1772                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1773                 entry.vector          = 0;
1774                 entry.dest.physical.physical_dest =
1775                                         GET_APIC_ID(apic_read(APIC_ID));
1776
1777                 /*
1778                  * Add it to the IO-APIC irq-routing table:
1779                  */
1780                 spin_lock_irqsave(&ioapic_lock, flags);
1781                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1782                         *(((int *)&entry)+1));
1783                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1784                         *(((int *)&entry)+0));
1785                 spin_unlock_irqrestore(&ioapic_lock, flags);
1786         }
1787         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1788 #endif
1789 }
1790
1791 /*
1792  * function to set the IO-APIC physical IDs based on the
1793  * values stored in the MPC table.
1794  *
1795  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1796  */
1797
1798 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1799 static void __init setup_ioapic_ids_from_mpc(void)
1800 {
1801         union IO_APIC_reg_00 reg_00;
1802         physid_mask_t phys_id_present_map;
1803         int apic;
1804         int i;
1805         unsigned char old_id;
1806         unsigned long flags;
1807
1808         /*
1809          * Don't check I/O APIC IDs for xAPIC systems.  They have
1810          * no meaning without the serial APIC bus.
1811          */
1812         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1813                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1814                 return;
1815         /*
1816          * This is broken; anything with a real cpu count has to
1817          * circumvent this idiocy regardless.
1818          */
1819         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1820
1821         /*
1822          * Set the IOAPIC ID to the value stored in the MPC table.
1823          */
1824         for (apic = 0; apic < nr_ioapics; apic++) {
1825
1826                 /* Read the register 0 value */
1827                 spin_lock_irqsave(&ioapic_lock, flags);
1828                 reg_00.raw = io_apic_read(apic, 0);
1829                 spin_unlock_irqrestore(&ioapic_lock, flags);
1830
1831                 old_id = mp_ioapics[apic].mpc_apicid;
1832
1833                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1834                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1835                                 apic, mp_ioapics[apic].mpc_apicid);
1836                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1837                                 reg_00.bits.ID);
1838                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1839                 }
1840
1841                 /*
1842                  * Sanity check, is the ID really free? Every APIC in a
1843                  * system must have a unique ID or we get lots of nice
1844                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1845                  */
1846                 if (check_apicid_used(phys_id_present_map,
1847                                         mp_ioapics[apic].mpc_apicid)) {
1848                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1849                                 apic, mp_ioapics[apic].mpc_apicid);
1850                         for (i = 0; i < get_physical_broadcast(); i++)
1851                                 if (!physid_isset(i, phys_id_present_map))
1852                                         break;
1853                         if (i >= get_physical_broadcast())
1854                                 panic("Max APIC ID exceeded!\n");
1855                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1856                                 i);
1857                         physid_set(i, phys_id_present_map);
1858                         mp_ioapics[apic].mpc_apicid = i;
1859                 } else {
1860                         physid_mask_t tmp;
1861                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1862                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1863                                         "phys_id_present_map\n",
1864                                         mp_ioapics[apic].mpc_apicid);
1865                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1866                 }
1867
1868
1869                 /*
1870                  * We need to adjust the IRQ routing table
1871                  * if the ID changed.
1872                  */
1873                 if (old_id != mp_ioapics[apic].mpc_apicid)
1874                         for (i = 0; i < mp_irq_entries; i++)
1875                                 if (mp_irqs[i].mpc_dstapic == old_id)
1876                                         mp_irqs[i].mpc_dstapic
1877                                                 = mp_ioapics[apic].mpc_apicid;
1878
1879                 /*
1880                  * Read the right value from the MPC table and
1881                  * write it into the ID register.
1882                  */
1883                 apic_printk(APIC_VERBOSE, KERN_INFO
1884                         "...changing IO-APIC physical APIC ID to %d ...",
1885                         mp_ioapics[apic].mpc_apicid);
1886
1887                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1888                 spin_lock_irqsave(&ioapic_lock, flags);
1889                 io_apic_write(apic, 0, reg_00.raw);
1890                 spin_unlock_irqrestore(&ioapic_lock, flags);
1891
1892                 /*
1893                  * Sanity check
1894                  */
1895                 spin_lock_irqsave(&ioapic_lock, flags);
1896                 reg_00.raw = io_apic_read(apic, 0);
1897                 spin_unlock_irqrestore(&ioapic_lock, flags);
1898                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1899                         printk("could not set ID!\n");
1900                 else
1901                         apic_printk(APIC_VERBOSE, " ok.\n");
1902         }
1903 }
1904 #else
1905 static void __init setup_ioapic_ids_from_mpc(void) { }
1906 #endif
1907
1908 #ifndef CONFIG_XEN
1909 /*
1910  * There is a nasty bug in some older SMP boards, their mptable lies
1911  * about the timer IRQ. We do the following to work around the situation:
1912  *
1913  *      - timer IRQ defaults to IO-APIC IRQ
1914  *      - if this function detects that timer IRQs are defunct, then we fall
1915  *        back to ISA timer IRQs
1916  */
1917 static int __init timer_irq_works(void)
1918 {
1919         unsigned long t1 = jiffies;
1920
1921         local_irq_enable();
1922         /* Let ten ticks pass... */
1923         mdelay((10 * 1000) / HZ);
1924
1925         /*
1926          * Expect a few ticks at least, to be sure some possible
1927          * glue logic does not lock up after one or two first
1928          * ticks in a non-ExtINT mode.  Also the local APIC
1929          * might have cached one ExtINT interrupt.  Finally, at
1930          * least one tick may be lost due to delays.
1931          */
1932         if (jiffies - t1 > 4)
1933                 return 1;
1934
1935         return 0;
1936 }
1937
1938 /*
1939  * In the SMP+IOAPIC case it might happen that there are an unspecified
1940  * number of pending IRQ events unhandled. These cases are very rare,
1941  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1942  * better to do it this way as thus we do not have to be aware of
1943  * 'pending' interrupts in the IRQ path, except at this point.
1944  */
1945 /*
1946  * Edge triggered needs to resend any interrupt
1947  * that was delayed but this is now handled in the device
1948  * independent code.
1949  */
1950
1951 /*
1952  * Starting up a edge-triggered IO-APIC interrupt is
1953  * nasty - we need to make sure that we get the edge.
1954  * If it is already asserted for some reason, we need
1955  * return 1 to indicate that is was pending.
1956  *
1957  * This is not complete - we should be able to fake
1958  * an edge even if it isn't on the 8259A...
1959  */
1960 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1961 {
1962         int was_pending = 0;
1963         unsigned long flags;
1964
1965         spin_lock_irqsave(&ioapic_lock, flags);
1966         if (irq < 16) {
1967                 disable_8259A_irq(irq);
1968                 if (i8259A_irq_pending(irq))
1969                         was_pending = 1;
1970         }
1971         __unmask_IO_APIC_irq(irq);
1972         spin_unlock_irqrestore(&ioapic_lock, flags);
1973
1974         return was_pending;
1975 }
1976
1977 /*
1978  * Once we have recorded IRQ_PENDING already, we can mask the
1979  * interrupt for real. This prevents IRQ storms from unhandled
1980  * devices.
1981  */
1982 static void ack_edge_ioapic_irq(unsigned int irq)
1983 {
1984         move_irq(irq);
1985         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1986                                         == (IRQ_PENDING | IRQ_DISABLED))
1987                 mask_IO_APIC_irq(irq);
1988         ack_APIC_irq();
1989 }
1990
1991 /*
1992  * Level triggered interrupts can just be masked,
1993  * and shutting down and starting up the interrupt
1994  * is the same as enabling and disabling them -- except
1995  * with a startup need to return a "was pending" value.
1996  *
1997  * Level triggered interrupts are special because we
1998  * do not touch any IO-APIC register while handling
1999  * them. We ack the APIC in the end-IRQ handler, not
2000  * in the start-IRQ-handler. Protection against reentrance
2001  * from the same interrupt is still provided, both by the
2002  * generic IRQ layer and by the fact that an unacked local
2003  * APIC does not accept IRQs.
2004  */
2005 static unsigned int startup_level_ioapic_irq (unsigned int irq)
2006 {
2007         unmask_IO_APIC_irq(irq);
2008
2009         return 0; /* don't check for pending */
2010 }
2011
2012 static void end_level_ioapic_irq (unsigned int irq)
2013 {
2014         unsigned long v;
2015         int i;
2016
2017         move_irq(irq);
2018 /*
2019  * It appears there is an erratum which affects at least version 0x11
2020  * of I/O APIC (that's the 82093AA and cores integrated into various
2021  * chipsets).  Under certain conditions a level-triggered interrupt is
2022  * erroneously delivered as edge-triggered one but the respective IRR
2023  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2024  * message but it will never arrive and further interrupts are blocked
2025  * from the source.  The exact reason is so far unknown, but the
2026  * phenomenon was observed when two consecutive interrupt requests
2027  * from a given source get delivered to the same CPU and the source is
2028  * temporarily disabled in between.
2029  *
2030  * A workaround is to simulate an EOI message manually.  We achieve it
2031  * by setting the trigger mode to edge and then to level when the edge
2032  * trigger mode gets detected in the TMR of a local APIC for a
2033  * level-triggered interrupt.  We mask the source for the time of the
2034  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2035  * The idea is from Manfred Spraul.  --macro
2036  */
2037         i = IO_APIC_VECTOR(irq);
2038
2039         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2040
2041         ack_APIC_irq();
2042
2043         if (!(v & (1 << (i & 0x1f)))) {
2044                 atomic_inc(&irq_mis_count);
2045                 spin_lock(&ioapic_lock);
2046                 __mask_and_edge_IO_APIC_irq(irq);
2047                 __unmask_and_level_IO_APIC_irq(irq);
2048                 spin_unlock(&ioapic_lock);
2049         }
2050 }
2051
2052 #ifdef CONFIG_PCI_MSI
2053 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2054 {
2055         int irq = vector_to_irq(vector);
2056
2057         return startup_edge_ioapic_irq(irq);
2058 }
2059
2060 static void ack_edge_ioapic_vector(unsigned int vector)
2061 {
2062         int irq = vector_to_irq(vector);
2063
2064         move_native_irq(vector);
2065         ack_edge_ioapic_irq(irq);
2066 }
2067
2068 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2069 {
2070         int irq = vector_to_irq(vector);
2071
2072         return startup_level_ioapic_irq (irq);
2073 }
2074
2075 static void end_level_ioapic_vector (unsigned int vector)
2076 {
2077         int irq = vector_to_irq(vector);
2078
2079         move_native_irq(vector);
2080         end_level_ioapic_irq(irq);
2081 }
2082
2083 static void mask_IO_APIC_vector (unsigned int vector)
2084 {
2085         int irq = vector_to_irq(vector);
2086
2087         mask_IO_APIC_irq(irq);
2088 }
2089
2090 static void unmask_IO_APIC_vector (unsigned int vector)
2091 {
2092         int irq = vector_to_irq(vector);
2093
2094         unmask_IO_APIC_irq(irq);
2095 }
2096
2097 #ifdef CONFIG_SMP
2098 static void set_ioapic_affinity_vector (unsigned int vector,
2099                                         cpumask_t cpu_mask)
2100 {
2101         int irq = vector_to_irq(vector);
2102
2103         set_native_irq_info(vector, cpu_mask);
2104         set_ioapic_affinity_irq(irq, cpu_mask);
2105 }
2106 #endif
2107 #endif
2108
2109 /*
2110  * Level and edge triggered IO-APIC interrupts need different handling,
2111  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2112  * handled with the level-triggered descriptor, but that one has slightly
2113  * more overhead. Level-triggered interrupts cannot be handled with the
2114  * edge-triggered handler, without risking IRQ storms and other ugly
2115  * races.
2116  */
2117 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2118         .typename       = "IO-APIC-edge",
2119         .startup        = startup_edge_ioapic,
2120         .shutdown       = shutdown_edge_ioapic,
2121         .enable         = enable_edge_ioapic,
2122         .disable        = disable_edge_ioapic,
2123         .ack            = ack_edge_ioapic,
2124         .end            = end_edge_ioapic,
2125 #ifdef CONFIG_SMP
2126         .set_affinity   = set_ioapic_affinity,
2127 #endif
2128 };
2129
2130 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2131         .typename       = "IO-APIC-level",
2132         .startup        = startup_level_ioapic,
2133         .shutdown       = shutdown_level_ioapic,
2134         .enable         = enable_level_ioapic,
2135         .disable        = disable_level_ioapic,
2136         .ack            = mask_and_ack_level_ioapic,
2137         .end            = end_level_ioapic,
2138 #ifdef CONFIG_SMP
2139         .set_affinity   = set_ioapic_affinity,
2140 #endif
2141 };
2142 #endif /* !CONFIG_XEN */
2143
2144 static inline void init_IO_APIC_traps(void)
2145 {
2146         int irq;
2147
2148         /*
2149          * NOTE! The local APIC isn't very good at handling
2150          * multiple interrupts at the same interrupt level.
2151          * As the interrupt level is determined by taking the
2152          * vector number and shifting that right by 4, we
2153          * want to spread these out a bit so that they don't
2154          * all fall in the same interrupt level.
2155          *
2156          * Also, we've got to be careful not to trash gate
2157          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2158          */
2159         for (irq = 0; irq < NR_IRQS ; irq++) {
2160                 int tmp = irq;
2161                 if (use_pci_vector()) {
2162                         if (!platform_legacy_irq(tmp))
2163                                 if ((tmp = vector_to_irq(tmp)) == -1)
2164                                         continue;
2165                 }
2166                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2167                         /*
2168                          * Hmm.. We don't have an entry for this,
2169                          * so default to an old-fashioned 8259
2170                          * interrupt if we can..
2171                          */
2172                         if (irq < 16)
2173                                 make_8259A_irq(irq);
2174 #ifndef CONFIG_XEN
2175                         else
2176                                 /* Strange. Oh, well.. */
2177                                 irq_desc[irq].handler = &no_irq_type;
2178 #endif
2179                 }
2180         }
2181 }
2182
2183 #ifndef CONFIG_XEN
2184 static void enable_lapic_irq (unsigned int irq)
2185 {
2186         unsigned long v;
2187
2188         v = apic_read(APIC_LVT0);
2189         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2190 }
2191
2192 static void disable_lapic_irq (unsigned int irq)
2193 {
2194         unsigned long v;
2195
2196         v = apic_read(APIC_LVT0);
2197         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2198 }
2199
2200 static void ack_lapic_irq (unsigned int irq)
2201 {
2202         ack_APIC_irq();
2203 }
2204
2205 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2206
2207 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2208         .typename       = "local-APIC-edge",
2209         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2210         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2211         .enable         = enable_lapic_irq,
2212         .disable        = disable_lapic_irq,
2213         .ack            = ack_lapic_irq,
2214         .end            = end_lapic_irq
2215 };
2216
2217 static void setup_nmi (void)
2218 {
2219         /*
2220          * Dirty trick to enable the NMI watchdog ...
2221          * We put the 8259A master into AEOI mode and
2222          * unmask on all local APICs LVT0 as NMI.
2223          *
2224          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2225          * is from Maciej W. Rozycki - so we do not have to EOI from
2226          * the NMI handler or the timer interrupt.
2227          */
2228         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2229
2230         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2231
2232         apic_printk(APIC_VERBOSE, " done.\n");
2233 }
2234
2235 /*
2236  * This looks a bit hackish but it's about the only one way of sending
2237  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2238  * not support the ExtINT mode, unfortunately.  We need to send these
2239  * cycles as some i82489DX-based boards have glue logic that keeps the
2240  * 8259A interrupt line asserted until INTA.  --macro
2241  */
2242 static inline void unlock_ExtINT_logic(void)
2243 {
2244         int apic, pin, i;
2245         struct IO_APIC_route_entry entry0, entry1;
2246         unsigned char save_control, save_freq_select;
2247         unsigned long flags;
2248
2249         pin  = find_isa_irq_pin(8, mp_INT);
2250         apic = find_isa_irq_apic(8, mp_INT);
2251         if (pin == -1)
2252                 return;
2253
2254         spin_lock_irqsave(&ioapic_lock, flags);
2255         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2256         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2257         spin_unlock_irqrestore(&ioapic_lock, flags);
2258         clear_IO_APIC_pin(apic, pin);
2259
2260         memset(&entry1, 0, sizeof(entry1));
2261
2262         entry1.dest_mode = 0;                   /* physical delivery */
2263         entry1.mask = 0;                        /* unmask IRQ now */
2264         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2265         entry1.delivery_mode = dest_ExtINT;
2266         entry1.polarity = entry0.polarity;
2267         entry1.trigger = 0;
2268         entry1.vector = 0;
2269
2270         spin_lock_irqsave(&ioapic_lock, flags);
2271         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2272         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2273         spin_unlock_irqrestore(&ioapic_lock, flags);
2274
2275         save_control = CMOS_READ(RTC_CONTROL);
2276         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2277         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2278                    RTC_FREQ_SELECT);
2279         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2280
2281         i = 100;
2282         while (i-- > 0) {
2283                 mdelay(10);
2284                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2285                         i -= 10;
2286         }
2287
2288         CMOS_WRITE(save_control, RTC_CONTROL);
2289         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2290         clear_IO_APIC_pin(apic, pin);
2291
2292         spin_lock_irqsave(&ioapic_lock, flags);
2293         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2294         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2295         spin_unlock_irqrestore(&ioapic_lock, flags);
2296 }
2297
2298 int timer_uses_ioapic_pin_0;
2299
2300 /*
2301  * This code may look a bit paranoid, but it's supposed to cooperate with
2302  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2303  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2304  * fanatically on his truly buggy board.
2305  */
2306 static inline void check_timer(void)
2307 {
2308         int apic1, pin1, apic2, pin2;
2309         int vector;
2310
2311         /*
2312          * get/set the timer IRQ vector:
2313          */
2314         disable_8259A_irq(0);
2315         vector = assign_irq_vector(0);
2316         set_intr_gate(vector, interrupt[0]);
2317
2318         /*
2319          * Subtle, code in do_timer_interrupt() expects an AEOI
2320          * mode for the 8259A whenever interrupts are routed
2321          * through I/O APICs.  Also IRQ0 has to be enabled in
2322          * the 8259A which implies the virtual wire has to be
2323          * disabled in the local APIC.
2324          */
2325         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2326         init_8259A(1);
2327         timer_ack = 1;
2328         if (timer_over_8254 > 0)
2329                 enable_8259A_irq(0);
2330
2331         pin1  = find_isa_irq_pin(0, mp_INT);
2332         apic1 = find_isa_irq_apic(0, mp_INT);
2333         pin2  = ioapic_i8259.pin;
2334         apic2 = ioapic_i8259.apic;
2335
2336         if (pin1 == 0)
2337                 timer_uses_ioapic_pin_0 = 1;
2338
2339         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2340                 vector, apic1, pin1, apic2, pin2);
2341
2342         if (pin1 != -1) {
2343                 /*
2344                  * Ok, does IRQ0 through the IOAPIC work?
2345                  */
2346                 unmask_IO_APIC_irq(0);
2347                 if (timer_irq_works()) {
2348                         if (nmi_watchdog == NMI_IO_APIC) {
2349                                 disable_8259A_irq(0);
2350                                 setup_nmi();
2351                                 enable_8259A_irq(0);
2352                         }
2353                         if (disable_timer_pin_1 > 0)
2354                                 clear_IO_APIC_pin(0, pin1);
2355                         return;
2356                 }
2357                 clear_IO_APIC_pin(apic1, pin1);
2358                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2359                                 "IO-APIC\n");
2360         }
2361
2362         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2363         if (pin2 != -1) {
2364                 printk("\n..... (found pin %d) ...", pin2);
2365                 /*
2366                  * legacy devices should be connected to IO APIC #0
2367                  */
2368                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2369                 if (timer_irq_works()) {
2370                         printk("works.\n");
2371                         if (pin1 != -1)
2372                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2373                         else
2374                                 add_pin_to_irq(0, apic2, pin2);
2375                         if (nmi_watchdog == NMI_IO_APIC) {
2376                                 setup_nmi();
2377                         }
2378                         return;
2379                 }
2380                 /*
2381                  * Cleanup, just in case ...
2382                  */
2383                 clear_IO_APIC_pin(apic2, pin2);
2384         }
2385         printk(" failed.\n");
2386
2387         if (nmi_watchdog == NMI_IO_APIC) {
2388                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2389                 nmi_watchdog = 0;
2390         }
2391
2392         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2393
2394         disable_8259A_irq(0);
2395         irq_desc[0].handler = &lapic_irq_type;
2396         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2397         enable_8259A_irq(0);
2398
2399         if (timer_irq_works()) {
2400                 printk(" works.\n");
2401                 return;
2402         }
2403         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2404         printk(" failed.\n");
2405
2406         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2407
2408         timer_ack = 0;
2409         init_8259A(0);
2410         make_8259A_irq(0);
2411         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2412
2413         unlock_ExtINT_logic();
2414
2415         if (timer_irq_works()) {
2416                 printk(" works.\n");
2417                 return;
2418         }
2419         printk(" failed :(.\n");
2420         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2421                 "report.  Then try booting with the 'noapic' option");
2422 }
2423 #else
2424 int timer_uses_ioapic_pin_0;
2425 #define check_timer() ((void)0)
2426 #endif
2427
2428 /*
2429  *
2430  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2431  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2432  *   Linux doesn't really care, as it's not actually used
2433  *   for any interrupt handling anyway.
2434  */
2435 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2436
2437 void __init setup_IO_APIC(void)
2438 {
2439         enable_IO_APIC();
2440
2441         if (acpi_ioapic)
2442                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2443         else
2444                 io_apic_irqs = ~PIC_IRQS;
2445
2446         printk("ENABLING IO-APIC IRQs\n");
2447
2448         /*
2449          * Set up IO-APIC IRQ routing.
2450          */
2451         if (!acpi_ioapic)
2452                 setup_ioapic_ids_from_mpc();
2453 #ifndef CONFIG_XEN
2454         sync_Arb_IDs();
2455 #endif
2456         setup_IO_APIC_irqs();
2457         init_IO_APIC_traps();
2458         check_timer();
2459         if (!acpi_ioapic)
2460                 print_IO_APIC();
2461 }
2462
2463 static int __init setup_disable_8254_timer(char *s)
2464 {
2465         timer_over_8254 = -1;
2466         return 1;
2467 }
2468 static int __init setup_enable_8254_timer(char *s)
2469 {
2470         timer_over_8254 = 2;
2471         return 1;
2472 }
2473
2474 __setup("disable_8254_timer", setup_disable_8254_timer);
2475 __setup("enable_8254_timer", setup_enable_8254_timer);
2476
2477 /*
2478  *      Called after all the initialization is done. If we didnt find any
2479  *      APIC bugs then we can allow the modify fast path
2480  */
2481
2482 static int __init io_apic_bug_finalize(void)
2483 {
2484         if(sis_apic_bug == -1)
2485                 sis_apic_bug = 0;
2486         if (xen_start_info->flags & SIF_INITDOMAIN) {
2487                 dom0_op_t op = { .cmd = DOM0_PLATFORM_QUIRK };
2488                 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2489                         QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2490                 HYPERVISOR_dom0_op(&op);
2491         }
2492         return 0;
2493 }
2494
2495 late_initcall(io_apic_bug_finalize);
2496
2497 struct sysfs_ioapic_data {
2498         struct sys_device dev;
2499         struct IO_APIC_route_entry entry[0];
2500 };
2501 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2502
2503 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2504 {
2505         struct IO_APIC_route_entry *entry;
2506         struct sysfs_ioapic_data *data;
2507         unsigned long flags;
2508         int i;
2509
2510         data = container_of(dev, struct sysfs_ioapic_data, dev);
2511         entry = data->entry;
2512         spin_lock_irqsave(&ioapic_lock, flags);
2513         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2514                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2515                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2516         }
2517         spin_unlock_irqrestore(&ioapic_lock, flags);
2518
2519         return 0;
2520 }
2521
2522 static int ioapic_resume(struct sys_device *dev)
2523 {
2524         struct IO_APIC_route_entry *entry;
2525         struct sysfs_ioapic_data *data;
2526         unsigned long flags;
2527         union IO_APIC_reg_00 reg_00;
2528         int i;
2529
2530         data = container_of(dev, struct sysfs_ioapic_data, dev);
2531         entry = data->entry;
2532
2533         spin_lock_irqsave(&ioapic_lock, flags);
2534         reg_00.raw = io_apic_read(dev->id, 0);
2535         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2536                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2537                 io_apic_write(dev->id, 0, reg_00.raw);
2538         }
2539         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2540                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2541                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2542         }
2543         spin_unlock_irqrestore(&ioapic_lock, flags);
2544
2545         return 0;
2546 }
2547
2548 static struct sysdev_class ioapic_sysdev_class = {
2549         set_kset_name("ioapic"),
2550         .suspend = ioapic_suspend,
2551         .resume = ioapic_resume,
2552 };
2553
2554 static int __init ioapic_init_sysfs(void)
2555 {
2556         struct sys_device * dev;
2557         int i, size, error = 0;
2558
2559         error = sysdev_class_register(&ioapic_sysdev_class);
2560         if (error)
2561                 return error;
2562
2563         for (i = 0; i < nr_ioapics; i++ ) {
2564                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2565                         * sizeof(struct IO_APIC_route_entry);
2566                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2567                 if (!mp_ioapic_data[i]) {
2568                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2569                         continue;
2570                 }
2571                 memset(mp_ioapic_data[i], 0, size);
2572                 dev = &mp_ioapic_data[i]->dev;
2573                 dev->id = i;
2574                 dev->cls = &ioapic_sysdev_class;
2575                 error = sysdev_register(dev);
2576                 if (error) {
2577                         kfree(mp_ioapic_data[i]);
2578                         mp_ioapic_data[i] = NULL;
2579                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2580                         continue;
2581                 }
2582         }
2583
2584         return 0;
2585 }
2586
2587 device_initcall(ioapic_init_sysfs);
2588
2589 /* --------------------------------------------------------------------------
2590                           ACPI-based IOAPIC Configuration
2591    -------------------------------------------------------------------------- */
2592
2593 #ifdef CONFIG_ACPI
2594
2595 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2596 {
2597 #ifndef CONFIG_XEN
2598         union IO_APIC_reg_00 reg_00;
2599         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2600         physid_mask_t tmp;
2601         unsigned long flags;
2602         int i = 0;
2603
2604         /*
2605          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2606          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2607          * supports up to 16 on one shared APIC bus.
2608          *
2609          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2610          *      advantage of new APIC bus architecture.
2611          */
2612
2613         if (physids_empty(apic_id_map))
2614                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2615
2616         spin_lock_irqsave(&ioapic_lock, flags);
2617         reg_00.raw = io_apic_read(ioapic, 0);
2618         spin_unlock_irqrestore(&ioapic_lock, flags);
2619
2620         if (apic_id >= get_physical_broadcast()) {
2621                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2622                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2623                 apic_id = reg_00.bits.ID;
2624         }
2625
2626         /*
2627          * Every APIC in a system must have a unique ID or we get lots of nice
2628          * 'stuck on smp_invalidate_needed IPI wait' messages.
2629          */
2630         if (check_apicid_used(apic_id_map, apic_id)) {
2631
2632                 for (i = 0; i < get_physical_broadcast(); i++) {
2633                         if (!check_apicid_used(apic_id_map, i))
2634                                 break;
2635                 }
2636
2637                 if (i == get_physical_broadcast())
2638                         panic("Max apic_id exceeded!\n");
2639
2640                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2641                         "trying %d\n", ioapic, apic_id, i);
2642
2643                 apic_id = i;
2644         }
2645
2646         tmp = apicid_to_cpu_present(apic_id);
2647         physids_or(apic_id_map, apic_id_map, tmp);
2648
2649         if (reg_00.bits.ID != apic_id) {
2650                 reg_00.bits.ID = apic_id;
2651
2652                 spin_lock_irqsave(&ioapic_lock, flags);
2653                 io_apic_write(ioapic, 0, reg_00.raw);
2654                 reg_00.raw = io_apic_read(ioapic, 0);
2655                 spin_unlock_irqrestore(&ioapic_lock, flags);
2656
2657                 /* Sanity check */
2658                 if (reg_00.bits.ID != apic_id) {
2659                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2660                         return -1;
2661                 }
2662         }
2663
2664         apic_printk(APIC_VERBOSE, KERN_INFO
2665                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2666 #endif /* !CONFIG_XEN */
2667
2668         return apic_id;
2669 }
2670
2671
2672 int __init io_apic_get_version (int ioapic)
2673 {
2674         union IO_APIC_reg_01    reg_01;
2675         unsigned long flags;
2676
2677         spin_lock_irqsave(&ioapic_lock, flags);
2678         reg_01.raw = io_apic_read(ioapic, 1);
2679         spin_unlock_irqrestore(&ioapic_lock, flags);
2680
2681         return reg_01.bits.version;
2682 }
2683
2684
2685 int __init io_apic_get_redir_entries (int ioapic)
2686 {
2687         union IO_APIC_reg_01    reg_01;
2688         unsigned long flags;
2689
2690         spin_lock_irqsave(&ioapic_lock, flags);
2691         reg_01.raw = io_apic_read(ioapic, 1);
2692         spin_unlock_irqrestore(&ioapic_lock, flags);
2693
2694         return reg_01.bits.entries;
2695 }
2696
2697
2698 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2699 {
2700         struct IO_APIC_route_entry entry;
2701         unsigned long flags;
2702
2703         if (!IO_APIC_IRQ(irq)) {
2704                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2705                         ioapic);
2706                 return -EINVAL;
2707         }
2708
2709         /*
2710          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2711          * Note that we mask (disable) IRQs now -- these get enabled when the
2712          * corresponding device driver registers for this IRQ.
2713          */
2714
2715         memset(&entry,0,sizeof(entry));
2716
2717         entry.delivery_mode = INT_DELIVERY_MODE;
2718         entry.dest_mode = INT_DEST_MODE;
2719         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2720         entry.trigger = edge_level;
2721         entry.polarity = active_high_low;
2722         entry.mask  = 1;
2723
2724         /*
2725          * IRQs < 16 are already in the irq_2_pin[] map
2726          */
2727         if (irq >= 16)
2728                 add_pin_to_irq(irq, ioapic, pin);
2729
2730         entry.vector = assign_irq_vector(irq);
2731
2732         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2733                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2734                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2735                 edge_level, active_high_low);
2736
2737         ioapic_register_intr(irq, entry.vector, edge_level);
2738
2739         if (!ioapic && (irq < 16))
2740                 disable_8259A_irq(irq);
2741
2742         spin_lock_irqsave(&ioapic_lock, flags);
2743         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2744         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2745         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2746         spin_unlock_irqrestore(&ioapic_lock, flags);
2747
2748         return 0;
2749 }
2750
2751 #endif /* CONFIG_ACPI */