arch/i386/kernel/io_apic-xen.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/pci.h>
  35 #include <linux/msi.h>
  36 #include <linux/htirq.h>
  37 #include <linux/freezer.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/timer.h>
  43 #include <asm/i8259.h>
  44 #include <asm/nmi.h>
  45 #include <asm/msidef.h>
  46 #include <asm/hypertransport.h>
  47
  48 #include <mach_apic.h>
  49 #include <mach_apicdef.h>
  50
  51 #include "io_ports.h"
  52
  53 #ifdef CONFIG_XEN
  54
  55 #include <xen/interface/xen.h>
  56 #include <xen/interface/physdev.h>
  57
  58 /* Fake i8259 */
  59 #define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
  60 #define disable_8259A_irq(_irq)  ((void)0)
  61 #define i8259A_irq_pending(_irq) (0)
  62
  63 unsigned long io_apic_irqs;
  64
  65 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
  66 {
  67         struct physdev_apic apic_op;
  68         int ret;
  69
  70         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
  71         apic_op.reg = reg;
  72         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
  73         if (ret)
  74                 return ret;
  75         return apic_op.value;
  76 }
  77
  78 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
  79 {
  80         struct physdev_apic apic_op;
  81
  82         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
  83         apic_op.reg = reg;
  84         apic_op.value = value;
  85         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
  86 }
  87
  88 #define io_apic_read(a,r)    xen_io_apic_read(a,r)
  89 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
  90
  91 #endif /* CONFIG_XEN */
  92
  93 int (*ioapic_renumber_irq)(int ioapic, int irq);
  94 atomic_t irq_mis_count;
  95
  96 /* Where if anywhere is the i8259 connect in external int mode */
  97 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  98
  99 static DEFINE_SPINLOCK(ioapic_lock);
 100 static DEFINE_SPINLOCK(vector_lock);
 101
 102 int timer_over_8254 __initdata = 1;
 103
 104 /*
 105  *      Is the SiS APIC rmw bug present ?
 106  *      -1 = don't know, 0 = no, 1 = yes
 107  */
 108 int sis_apic_bug = -1;
 109
 110 /*
 111  * # of IRQ routing registers
 112  */
 113 int nr_ioapic_registers[MAX_IO_APICS];
 114
 115 static int disable_timer_pin_1 __initdata;
 116
 117 /*
 118  * Rough estimation of how many shared IRQs there are, can
 119  * be changed anytime.
 120  */
 121 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 122 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 123
 124 /*
 125  * This is performance-critical, we want to do it O(1)
 126  *
 127  * the indexing order of this array favors 1:1 mappings
 128  * between pins and IRQs.
 129  */
 130
 131 static struct irq_pin_list {
 132         int apic, pin, next;
 133 } irq_2_pin[PIN_MAP_SIZE];
 134
 135 #ifndef CONFIG_XEN
 136 struct io_apic {
 137         unsigned int index;
 138         unsigned int unused[3];
 139         unsigned int data;
 140 };
 141
 142 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 143 {
 144         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 145                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 146 }
 147
 148 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 149 {
 150         struct io_apic __iomem *io_apic = io_apic_base(apic);
 151         writel(reg, &io_apic->index);
 152         return readl(&io_apic->data);
 153 }
 154
 155 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 156 {
 157         struct io_apic __iomem *io_apic = io_apic_base(apic);
 158         writel(reg, &io_apic->index);
 159         writel(value, &io_apic->data);
 160 }
 161
 162 /*
 163  * Re-write a value: to be used for read-modify-write
 164  * cycles where the read already set up the index register.
 165  *
 166  * Older SiS APIC requires we rewrite the index register
 167  */
 168 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 169 {
 170         volatile struct io_apic *io_apic = io_apic_base(apic);
 171         if (sis_apic_bug)
 172                 writel(reg, &io_apic->index);
 173         writel(value, &io_apic->data);
 174 }
 175 #endif /* !CONFIG_XEN */
 176
 177 union entry_union {
 178         struct { u32 w1, w2; };
 179         struct IO_APIC_route_entry entry;
 180 };
 181
 182 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 183 {
 184         union entry_union eu;
 185         unsigned long flags;
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 188         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 189         spin_unlock_irqrestore(&ioapic_lock, flags);
 190         return eu.entry;
 191 }
 192
 193 /*
 194  * When we write a new IO APIC routing entry, we need to write the high
 195  * word first! If the mask bit in the low word is clear, we will enable
 196  * the interrupt, and we need to make sure the entry is fully populated
 197  * before that happens.
 198  */
 199 static void
 200 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 201 {
 202         union entry_union eu;
 203         eu.entry = e;
 204         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 205         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 206 }
 207
 208 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 209 {
 210         unsigned long flags;
 211         spin_lock_irqsave(&ioapic_lock, flags);
 212         __ioapic_write_entry(apic, pin, e);
 213         spin_unlock_irqrestore(&ioapic_lock, flags);
 214 }
 215
 216 /*
 217  * When we mask an IO APIC routing entry, we need to write the low
 218  * word first, in order to set the mask bit before we change the
 219  * high bits!
 220  */
 221
 222 #ifndef CONFIG_XEN
 223 static void ioapic_mask_entry(int apic, int pin)
 224 {
 225         unsigned long flags;
 226         union entry_union eu = { .entry.mask = 1 };
 227
 228         spin_lock_irqsave(&ioapic_lock, flags);
 229         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 230         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 231         spin_unlock_irqrestore(&ioapic_lock, flags);
 232 }
 233 #endif
 234
 235 /*
 236  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 237  * shared ISA-space IRQs, so we have to support them. We are super
 238  * fast in the common case, and fast for shared ISA-space IRQs.
 239  */
 240 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 241 {
 242         static int first_free_entry = NR_IRQS;
 243         struct irq_pin_list *entry = irq_2_pin + irq;
 244
 245         while (entry->next)
 246                 entry = irq_2_pin + entry->next;
 247
 248         if (entry->pin != -1) {
 249                 entry->next = first_free_entry;
 250                 entry = irq_2_pin + entry->next;
 251                 if (++first_free_entry >= PIN_MAP_SIZE)
 252                         panic("io_apic.c: whoops");
 253         }
 254         entry->apic = apic;
 255         entry->pin = pin;
 256 }
 257
 258 #ifdef CONFIG_XEN
 259 #define clear_IO_APIC() ((void)0)
 260 #else
 261 /*
 262  * Reroute an IRQ to a different pin.
 263  */
 264 static void __init replace_pin_at_irq(unsigned int irq,
 265                                       int oldapic, int oldpin,
 266                                       int newapic, int newpin)
 267 {
 268         struct irq_pin_list *entry = irq_2_pin + irq;
 269
 270         while (1) {
 271                 if (entry->apic == oldapic && entry->pin == oldpin) {
 272                         entry->apic = newapic;
 273                         entry->pin = newpin;
 274                 }
 275                 if (!entry->next)
 276                         break;
 277                 entry = irq_2_pin + entry->next;
 278         }
 279 }
 280
 281 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 282 {
 283         struct irq_pin_list *entry = irq_2_pin + irq;
 284         unsigned int pin, reg;
 285
 286         for (;;) {
 287                 pin = entry->pin;
 288                 if (pin == -1)
 289                         break;
 290                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 291                 reg &= ~disable;
 292                 reg |= enable;
 293                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 294                 if (!entry->next)
 295                         break;
 296                 entry = irq_2_pin + entry->next;
 297         }
 298 }
 299
 300 /* mask = 1 */
 301 static void __mask_IO_APIC_irq (unsigned int irq)
 302 {
 303         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 304 }
 305
 306 /* mask = 0 */
 307 static void __unmask_IO_APIC_irq (unsigned int irq)
 308 {
 309         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 310 }
 311
 312 /* mask = 1, trigger = 0 */
 313 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 314 {
 315         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 316 }
 317
 318 /* mask = 0, trigger = 1 */
 319 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 320 {
 321         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 322 }
 323
 324 static void mask_IO_APIC_irq (unsigned int irq)
 325 {
 326         unsigned long flags;
 327
 328         spin_lock_irqsave(&ioapic_lock, flags);
 329         __mask_IO_APIC_irq(irq);
 330         spin_unlock_irqrestore(&ioapic_lock, flags);
 331 }
 332
 333 static void unmask_IO_APIC_irq (unsigned int irq)
 334 {
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&ioapic_lock, flags);
 338         __unmask_IO_APIC_irq(irq);
 339         spin_unlock_irqrestore(&ioapic_lock, flags);
 340 }
 341
 342 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 343 {
 344         struct IO_APIC_route_entry entry;
 345
 346         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 347         entry = ioapic_read_entry(apic, pin);
 348         if (entry.delivery_mode == dest_SMI)
 349                 return;
 350
 351         /*
 352          * Disable it in the IO-APIC irq-routing table:
 353          */
 354         ioapic_mask_entry(apic, pin);
 355 }
 356
 357 static void clear_IO_APIC (void)
 358 {
 359         int apic, pin;
 360
 361         for (apic = 0; apic < nr_ioapics; apic++)
 362                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 363                         clear_IO_APIC_pin(apic, pin);
 364 }
 365
 366 #ifdef CONFIG_SMP
 367 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 368 {
 369         unsigned long flags;
 370         int pin;
 371         struct irq_pin_list *entry = irq_2_pin + irq;
 372         unsigned int apicid_value;
 373         cpumask_t tmp;
 374
 375         cpus_and(tmp, cpumask, cpu_online_map);
 376         if (cpus_empty(tmp))
 377                 tmp = TARGET_CPUS;
 378
 379         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 380
 381         apicid_value = cpu_mask_to_apicid(cpumask);
 382         /* Prepare to do the io_apic_write */
 383         apicid_value = apicid_value << 24;
 384         spin_lock_irqsave(&ioapic_lock, flags);
 385         for (;;) {
 386                 pin = entry->pin;
 387                 if (pin == -1)
 388                         break;
 389                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 390                 if (!entry->next)
 391                         break;
 392                 entry = irq_2_pin + entry->next;
 393         }
 394         set_native_irq_info(irq, cpumask);
 395         spin_unlock_irqrestore(&ioapic_lock, flags);
 396 }
 397
 398 #if defined(CONFIG_IRQBALANCE)
 399 # include <asm/processor.h>     /* kernel_thread() */
 400 # include <linux/kernel_stat.h> /* kstat */
 401 # include <linux/slab.h>                /* kmalloc() */
 402 # include <linux/timer.h>       /* time_after() */
 403
 404 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 405 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 406 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 407 # else
 408 #  define TDprintk(x...)
 409 #  define Dprintk(x...)
 410 # endif
 411
 412 #define IRQBALANCE_CHECK_ARCH -999
 413 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 414 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 415 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 416 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 417
 418 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 419 static int physical_balance __read_mostly;
 420 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 421
 422 static struct irq_cpu_info {
 423         unsigned long * last_irq;
 424         unsigned long * irq_delta;
 425         unsigned long irq;
 426 } irq_cpu_data[NR_CPUS];
 427
 428 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 429 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 430 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 431
 432 #define IDLE_ENOUGH(cpu,now) \
 433         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 434
 435 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 436
 437 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 438
 439 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 440         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 441 };
 442
 443 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 444 {
 445         balance_irq_affinity[irq] = mask;
 446 }
 447
 448 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 449                         unsigned long now, int direction)
 450 {
 451         int search_idle = 1;
 452         int cpu = curr_cpu;
 453
 454         goto inside;
 455
 456         do {
 457                 if (unlikely(cpu == curr_cpu))
 458                         search_idle = 0;
 459 inside:
 460                 if (direction == 1) {
 461                         cpu++;
 462                         if (cpu >= NR_CPUS)
 463                                 cpu = 0;
 464                 } else {
 465                         cpu--;
 466                         if (cpu == -1)
 467                                 cpu = NR_CPUS-1;
 468                 }
 469         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 470                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 471
 472         return cpu;
 473 }
 474
 475 static inline void balance_irq(int cpu, int irq)
 476 {
 477         unsigned long now = jiffies;
 478         cpumask_t allowed_mask;
 479         unsigned int new_cpu;
 480
 481         if (irqbalance_disabled)
 482                 return;
 483
 484         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 485         new_cpu = move(cpu, allowed_mask, now, 1);
 486         if (cpu != new_cpu) {
 487                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 488         }
 489 }
 490
 491 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 492 {
 493         int i, j;
 494         Dprintk("Rotating IRQs among CPUs.\n");
 495         for_each_online_cpu(i) {
 496                 for (j = 0; j < NR_IRQS; j++) {
 497                         if (!irq_desc[j].action)
 498                                 continue;
 499                         /* Is it a significant load ?  */
 500                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 501                                                 useful_load_threshold)
 502                                 continue;
 503                         balance_irq(i, j);
 504                 }
 505         }
 506         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 507                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 508         return;
 509 }
 510
 511 static void do_irq_balance(void)
 512 {
 513         int i, j;
 514         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 515         unsigned long move_this_load = 0;
 516         int max_loaded = 0, min_loaded = 0;
 517         int load;
 518         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 519         int selected_irq;
 520         int tmp_loaded, first_attempt = 1;
 521         unsigned long tmp_cpu_irq;
 522         unsigned long imbalance = 0;
 523         cpumask_t allowed_mask, target_cpu_mask, tmp;
 524
 525         for_each_possible_cpu(i) {
 526                 int package_index;
 527                 CPU_IRQ(i) = 0;
 528                 if (!cpu_online(i))
 529                         continue;
 530                 package_index = CPU_TO_PACKAGEINDEX(i);
 531                 for (j = 0; j < NR_IRQS; j++) {
 532                         unsigned long value_now, delta;
 533                         /* Is this an active IRQ? */
 534                         if (!irq_desc[j].action)
 535                                 continue;
 536                         if ( package_index == i )
 537                                 IRQ_DELTA(package_index,j) = 0;
 538                         /* Determine the total count per processor per IRQ */
 539                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 540
 541                         /* Determine the activity per processor per IRQ */
 542                         delta = value_now - LAST_CPU_IRQ(i,j);
 543
 544                         /* Update last_cpu_irq[][] for the next time */
 545                         LAST_CPU_IRQ(i,j) = value_now;
 546
 547                         /* Ignore IRQs whose rate is less than the clock */
 548                         if (delta < useful_load_threshold)
 549                                 continue;
 550                         /* update the load for the processor or package total */
 551                         IRQ_DELTA(package_index,j) += delta;
 552
 553                         /* Keep track of the higher numbered sibling as well */
 554                         if (i != package_index)
 555                                 CPU_IRQ(i) += delta;
 556                         /*
 557                          * We have sibling A and sibling B in the package
 558                          *
 559                          * cpu_irq[A] = load for cpu A + load for cpu B
 560                          * cpu_irq[B] = load for cpu B
 561                          */
 562                         CPU_IRQ(package_index) += delta;
 563                 }
 564         }
 565         /* Find the least loaded processor package */
 566         for_each_online_cpu(i) {
 567                 if (i != CPU_TO_PACKAGEINDEX(i))
 568                         continue;
 569                 if (min_cpu_irq > CPU_IRQ(i)) {
 570                         min_cpu_irq = CPU_IRQ(i);
 571                         min_loaded = i;
 572                 }
 573         }
 574         max_cpu_irq = ULONG_MAX;
 575
 576 tryanothercpu:
 577         /* Look for heaviest loaded processor.
 578          * We may come back to get the next heaviest loaded processor.
 579          * Skip processors with trivial loads.
 580          */
 581         tmp_cpu_irq = 0;
 582         tmp_loaded = -1;
 583         for_each_online_cpu(i) {
 584                 if (i != CPU_TO_PACKAGEINDEX(i))
 585                         continue;
 586                 if (max_cpu_irq <= CPU_IRQ(i))
 587                         continue;
 588                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 589                         tmp_cpu_irq = CPU_IRQ(i);
 590                         tmp_loaded = i;
 591                 }
 592         }
 593
 594         if (tmp_loaded == -1) {
 595          /* In the case of small number of heavy interrupt sources,
 596           * loading some of the cpus too much. We use Ingo's original
 597           * approach to rotate them around.
 598           */
 599                 if (!first_attempt && imbalance >= useful_load_threshold) {
 600                         rotate_irqs_among_cpus(useful_load_threshold);
 601                         return;
 602                 }
 603                 goto not_worth_the_effort;
 604         }
 605
 606         first_attempt = 0;              /* heaviest search */
 607         max_cpu_irq = tmp_cpu_irq;      /* load */
 608         max_loaded = tmp_loaded;        /* processor */
 609         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 610
 611         Dprintk("max_loaded cpu = %d\n", max_loaded);
 612         Dprintk("min_loaded cpu = %d\n", min_loaded);
 613         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 614         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 615         Dprintk("load imbalance = %lu\n", imbalance);
 616
 617         /* if imbalance is less than approx 10% of max load, then
 618          * observe diminishing returns action. - quit
 619          */
 620         if (imbalance < (max_cpu_irq >> 3)) {
 621                 Dprintk("Imbalance too trivial\n");
 622                 goto not_worth_the_effort;
 623         }
 624
 625 tryanotherirq:
 626         /* if we select an IRQ to move that can't go where we want, then
 627          * see if there is another one to try.
 628          */
 629         move_this_load = 0;
 630         selected_irq = -1;
 631         for (j = 0; j < NR_IRQS; j++) {
 632                 /* Is this an active IRQ? */
 633                 if (!irq_desc[j].action)
 634                         continue;
 635                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 636                         continue;
 637                 /* Try to find the IRQ that is closest to the imbalance
 638                  * without going over.
 639                  */
 640                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 641                         move_this_load = IRQ_DELTA(max_loaded,j);
 642                         selected_irq = j;
 643                 }
 644         }
 645         if (selected_irq == -1) {
 646                 goto tryanothercpu;
 647         }
 648
 649         imbalance = move_this_load;
 650
 651         /* For physical_balance case, we accumlated both load
 652          * values in the one of the siblings cpu_irq[],
 653          * to use the same code for physical and logical processors
 654          * as much as possible.
 655          *
 656          * NOTE: the cpu_irq[] array holds the sum of the load for
 657          * sibling A and sibling B in the slot for the lowest numbered
 658          * sibling (A), _AND_ the load for sibling B in the slot for
 659          * the higher numbered sibling.
 660          *
 661          * We seek the least loaded sibling by making the comparison
 662          * (A+B)/2 vs B
 663          */
 664         load = CPU_IRQ(min_loaded) >> 1;
 665         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 666                 if (load > CPU_IRQ(j)) {
 667                         /* This won't change cpu_sibling_map[min_loaded] */
 668                         load = CPU_IRQ(j);
 669                         min_loaded = j;
 670                 }
 671         }
 672
 673         cpus_and(allowed_mask,
 674                 cpu_online_map,
 675                 balance_irq_affinity[selected_irq]);
 676         target_cpu_mask = cpumask_of_cpu(min_loaded);
 677         cpus_and(tmp, target_cpu_mask, allowed_mask);
 678
 679         if (!cpus_empty(tmp)) {
 680
 681                 Dprintk("irq = %d moved to cpu = %d\n",
 682                                 selected_irq, min_loaded);
 683                 /* mark for change destination */
 684                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 685
 686                 /* Since we made a change, come back sooner to
 687                  * check for more variation.
 688                  */
 689                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 690                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 691                 return;
 692         }
 693         goto tryanotherirq;
 694
 695 not_worth_the_effort:
 696         /*
 697          * if we did not find an IRQ to move, then adjust the time interval
 698          * upward
 699          */
 700         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 701                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 702         Dprintk("IRQ worth rotating not found\n");
 703         return;
 704 }
 705
 706 static int balanced_irq(void *unused)
 707 {
 708         int i;
 709         unsigned long prev_balance_time = jiffies;
 710         long time_remaining = balanced_irq_interval;
 711
 712         daemonize("kirqd");
 713
 714         /* push everything to CPU 0 to give us a starting point.  */
 715         for (i = 0 ; i < NR_IRQS ; i++) {
 716                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 717                 set_pending_irq(i, cpumask_of_cpu(0));
 718         }
 719
 720         for ( ; ; ) {
 721                 time_remaining = schedule_timeout_interruptible(time_remaining);
 722                 try_to_freeze();
 723                 if (time_after(jiffies,
 724                                 prev_balance_time+balanced_irq_interval)) {
 725                         preempt_disable();
 726                         do_irq_balance();
 727                         prev_balance_time = jiffies;
 728                         time_remaining = balanced_irq_interval;
 729                         preempt_enable();
 730                 }
 731         }
 732         return 0;
 733 }
 734
 735 static int __init balanced_irq_init(void)
 736 {
 737         int i;
 738         struct cpuinfo_x86 *c;
 739         cpumask_t tmp;
 740
 741         cpus_shift_right(tmp, cpu_online_map, 2);
 742         c = &boot_cpu_data;
 743         /* When not overwritten by the command line ask subarchitecture. */
 744         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 745                 irqbalance_disabled = NO_BALANCE_IRQ;
 746         if (irqbalance_disabled)
 747                 return 0;
 748
 749          /* disable irqbalance completely if there is only one processor online */
 750         if (num_online_cpus() < 2) {
 751                 irqbalance_disabled = 1;
 752                 return 0;
 753         }
 754         /*
 755          * Enable physical balance only if more than 1 physical processor
 756          * is present
 757          */
 758         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 759                 physical_balance = 1;
 760
 761         for_each_online_cpu(i) {
 762                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 763                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 764                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 765                         printk(KERN_ERR "balanced_irq_init: out of memory");
 766                         goto failed;
 767                 }
 768                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 769                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 770         }
 771
 772         printk(KERN_INFO "Starting balanced_irq\n");
 773         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 774                 return 0;
 775         else
 776                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 777 failed:
 778         for_each_possible_cpu(i) {
 779                 kfree(irq_cpu_data[i].irq_delta);
 780                 irq_cpu_data[i].irq_delta = NULL;
 781                 kfree(irq_cpu_data[i].last_irq);
 782                 irq_cpu_data[i].last_irq = NULL;
 783         }
 784         return 0;
 785 }
 786
 787 int __init irqbalance_disable(char *str)
 788 {
 789         irqbalance_disabled = 1;
 790         return 1;
 791 }
 792
 793 __setup("noirqbalance", irqbalance_disable);
 794
 795 late_initcall(balanced_irq_init);
 796 #endif /* CONFIG_IRQBALANCE */
 797 #endif /* CONFIG_SMP */
 798 #endif /* !CONFIG_XEN */
 799
 800 #ifndef CONFIG_SMP
 801 void fastcall send_IPI_self(int vector)
 802 {
 803 #ifndef CONFIG_XEN
 804         unsigned int cfg;
 805
 806         /*
 807          * Wait for idle.
 808          */
 809         apic_wait_icr_idle();
 810         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 811         /*
 812          * Send the IPI. The write to APIC_ICR fires this off.
 813          */
 814         apic_write_around(APIC_ICR, cfg);
 815 #endif
 816 }
 817 #endif /* !CONFIG_SMP */
 818
 819
 820 /*
 821  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 822  * specific CPU-side IRQs.
 823  */
 824
 825 #define MAX_PIRQS 8
 826 static int pirq_entries [MAX_PIRQS];
 827 static int pirqs_enabled;
 828 int skip_ioapic_setup;
 829
 830 static int __init ioapic_setup(char *str)
 831 {
 832         skip_ioapic_setup = 1;
 833         return 1;
 834 }
 835
 836 __setup("noapic", ioapic_setup);
 837
 838 static int __init ioapic_pirq_setup(char *str)
 839 {
 840         int i, max;
 841         int ints[MAX_PIRQS+1];
 842
 843         get_options(str, ARRAY_SIZE(ints), ints);
 844
 845         for (i = 0; i < MAX_PIRQS; i++)
 846                 pirq_entries[i] = -1;
 847
 848         pirqs_enabled = 1;
 849         apic_printk(APIC_VERBOSE, KERN_INFO
 850                         "PIRQ redirection, working around broken MP-BIOS.\n");
 851         max = MAX_PIRQS;
 852         if (ints[0] < MAX_PIRQS)
 853                 max = ints[0];
 854
 855         for (i = 0; i < max; i++) {
 856                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 857                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 858                 /*
 859                  * PIRQs are mapped upside down, usually.
 860                  */
 861                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 862         }
 863         return 1;
 864 }
 865
 866 __setup("pirq=", ioapic_pirq_setup);
 867
 868 /*
 869  * Find the IRQ entry number of a certain pin.
 870  */
 871 static int find_irq_entry(int apic, int pin, int type)
 872 {
 873         int i;
 874
 875         for (i = 0; i < mp_irq_entries; i++)
 876                 if (mp_irqs[i].mpc_irqtype == type &&
 877                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 878                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 879                     mp_irqs[i].mpc_dstirq == pin)
 880                         return i;
 881
 882         return -1;
 883 }
 884
 885 /*
 886  * Find the pin to which IRQ[irq] (ISA) is connected
 887  */
 888 static int __init find_isa_irq_pin(int irq, int type)
 889 {
 890         int i;
 891
 892         for (i = 0; i < mp_irq_entries; i++) {
 893                 int lbus = mp_irqs[i].mpc_srcbus;
 894
 895                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 896                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 897                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
 898                     ) &&
 899                     (mp_irqs[i].mpc_irqtype == type) &&
 900                     (mp_irqs[i].mpc_srcbusirq == irq))
 901
 902                         return mp_irqs[i].mpc_dstirq;
 903         }
 904         return -1;
 905 }
 906
 907 static int __init find_isa_irq_apic(int irq, int type)
 908 {
 909         int i;
 910
 911         for (i = 0; i < mp_irq_entries; i++) {
 912                 int lbus = mp_irqs[i].mpc_srcbus;
 913
 914                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 915                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 916                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
 917                     ) &&
 918                     (mp_irqs[i].mpc_irqtype == type) &&
 919                     (mp_irqs[i].mpc_srcbusirq == irq))
 920                         break;
 921         }
 922         if (i < mp_irq_entries) {
 923                 int apic;
 924                 for(apic = 0; apic < nr_ioapics; apic++) {
 925                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 926                                 return apic;
 927                 }
 928         }
 929
 930         return -1;
 931 }
 932
 933 /*
 934  * Find a specific PCI IRQ entry.
 935  * Not an __init, possibly needed by modules
 936  */
 937 static int pin_2_irq(int idx, int apic, int pin);
 938
 939 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 940 {
 941         int apic, i, best_guess = -1;
 942
 943         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 944                 "slot:%d, pin:%d.\n", bus, slot, pin);
 945         if (mp_bus_id_to_pci_bus[bus] == -1) {
 946                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 947                 return -1;
 948         }
 949         for (i = 0; i < mp_irq_entries; i++) {
 950                 int lbus = mp_irqs[i].mpc_srcbus;
 951
 952                 for (apic = 0; apic < nr_ioapics; apic++)
 953                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 954                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 955                                 break;
 956
 957                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 958                     !mp_irqs[i].mpc_irqtype &&
 959                     (bus == lbus) &&
 960                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 961                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 962
 963                         if (!(apic || IO_APIC_IRQ(irq)))
 964                                 continue;
 965
 966                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 967                                 return irq;
 968                         /*
 969                          * Use the first all-but-pin matching entry as a
 970                          * best-guess fuzzy result for broken mptables.
 971                          */
 972                         if (best_guess < 0)
 973                                 best_guess = irq;
 974                 }
 975         }
 976         return best_guess;
 977 }
 978 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 979
 980 /*
 981  * This function currently is only a helper for the i386 smp boot process where
 982  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 983  * so mask in all cases should simply be TARGET_CPUS
 984  */
 985 #ifdef CONFIG_SMP
 986 #ifndef CONFIG_XEN
 987 void __init setup_ioapic_dest(void)
 988 {
 989         int pin, ioapic, irq, irq_entry;
 990
 991         if (skip_ioapic_setup == 1)
 992                 return;
 993
 994         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 995                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 996                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 997                         if (irq_entry == -1)
 998                                 continue;
 999                         irq = pin_2_irq(irq_entry, ioapic, pin);
1000                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1001                 }
1002
1003         }
1004 }
1005 #endif /* !CONFIG_XEN */
1006 #endif
1007
1008 /*
1009  * EISA Edge/Level control register, ELCR
1010  */
1011 static int EISA_ELCR(unsigned int irq)
1012 {
1013         if (irq < 16) {
1014                 unsigned int port = 0x4d0 + (irq >> 3);
1015                 return (inb(port) >> (irq & 7)) & 1;
1016         }
1017         apic_printk(APIC_VERBOSE, KERN_INFO
1018                         "Broken MPtable reports ISA irq %d\n", irq);
1019         return 0;
1020 }
1021
1022 /* EISA interrupts are always polarity zero and can be edge or level
1023  * trigger depending on the ELCR value.  If an interrupt is listed as
1024  * EISA conforming in the MP table, that means its trigger type must
1025  * be read in from the ELCR */
1026
1027 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
1028 #define default_EISA_polarity(idx)      (0)
1029
1030 /* ISA interrupts are always polarity zero edge triggered,
1031  * when listed as conforming in the MP table. */
1032
1033 #define default_ISA_trigger(idx)        (0)
1034 #define default_ISA_polarity(idx)       (0)
1035
1036 /* PCI interrupts are always polarity one level triggered,
1037  * when listed as conforming in the MP table. */
1038
1039 #define default_PCI_trigger(idx)        (1)
1040 #define default_PCI_polarity(idx)       (1)
1041
1042 /* MCA interrupts are always polarity zero level triggered,
1043  * when listed as conforming in the MP table. */
1044
1045 #define default_MCA_trigger(idx)        (1)
1046 #define default_MCA_polarity(idx)       (0)
1047
1048 static int __init MPBIOS_polarity(int idx)
1049 {
1050         int bus = mp_irqs[idx].mpc_srcbus;
1051         int polarity;
1052
1053         /*
1054          * Determine IRQ line polarity (high active or low active):
1055          */
1056         switch (mp_irqs[idx].mpc_irqflag & 3)
1057         {
1058                 case 0: /* conforms, ie. bus-type dependent polarity */
1059                 {
1060                         switch (mp_bus_id_to_type[bus])
1061                         {
1062                                 case MP_BUS_ISA: /* ISA pin */
1063                                 {
1064                                         polarity = default_ISA_polarity(idx);
1065                                         break;
1066                                 }
1067                                 case MP_BUS_EISA: /* EISA pin */
1068                                 {
1069                                         polarity = default_EISA_polarity(idx);
1070                                         break;
1071                                 }
1072                                 case MP_BUS_PCI: /* PCI pin */
1073                                 {
1074                                         polarity = default_PCI_polarity(idx);
1075                                         break;
1076                                 }
1077                                 case MP_BUS_MCA: /* MCA pin */
1078                                 {
1079                                         polarity = default_MCA_polarity(idx);
1080                                         break;
1081                                 }
1082                                 default:
1083                                 {
1084                                         printk(KERN_WARNING "broken BIOS!!\n");
1085                                         polarity = 1;
1086                                         break;
1087                                 }
1088                         }
1089                         break;
1090                 }
1091                 case 1: /* high active */
1092                 {
1093                         polarity = 0;
1094                         break;
1095                 }
1096                 case 2: /* reserved */
1097                 {
1098                         printk(KERN_WARNING "broken BIOS!!\n");
1099                         polarity = 1;
1100                         break;
1101                 }
1102                 case 3: /* low active */
1103                 {
1104                         polarity = 1;
1105                         break;
1106                 }
1107                 default: /* invalid */
1108                 {
1109                         printk(KERN_WARNING "broken BIOS!!\n");
1110                         polarity = 1;
1111                         break;
1112                 }
1113         }
1114         return polarity;
1115 }
1116
1117 static int MPBIOS_trigger(int idx)
1118 {
1119         int bus = mp_irqs[idx].mpc_srcbus;
1120         int trigger;
1121
1122         /*
1123          * Determine IRQ trigger mode (edge or level sensitive):
1124          */
1125         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1126         {
1127                 case 0: /* conforms, ie. bus-type dependent */
1128                 {
1129                         switch (mp_bus_id_to_type[bus])
1130                         {
1131                                 case MP_BUS_ISA: /* ISA pin */
1132                                 {
1133                                         trigger = default_ISA_trigger(idx);
1134                                         break;
1135                                 }
1136                                 case MP_BUS_EISA: /* EISA pin */
1137                                 {
1138                                         trigger = default_EISA_trigger(idx);
1139                                         break;
1140                                 }
1141                                 case MP_BUS_PCI: /* PCI pin */
1142                                 {
1143                                         trigger = default_PCI_trigger(idx);
1144                                         break;
1145                                 }
1146                                 case MP_BUS_MCA: /* MCA pin */
1147                                 {
1148                                         trigger = default_MCA_trigger(idx);
1149                                         break;
1150                                 }
1151                                 default:
1152                                 {
1153                                         printk(KERN_WARNING "broken BIOS!!\n");
1154                                         trigger = 1;
1155                                         break;
1156                                 }
1157                         }
1158                         break;
1159                 }
1160                 case 1: /* edge */
1161                 {
1162                         trigger = 0;
1163                         break;
1164                 }
1165                 case 2: /* reserved */
1166                 {
1167                         printk(KERN_WARNING "broken BIOS!!\n");
1168                         trigger = 1;
1169                         break;
1170                 }
1171                 case 3: /* level */
1172                 {
1173                         trigger = 1;
1174                         break;
1175                 }
1176                 default: /* invalid */
1177                 {
1178                         printk(KERN_WARNING "broken BIOS!!\n");
1179                         trigger = 0;
1180                         break;
1181                 }
1182         }
1183         return trigger;
1184 }
1185
1186 static inline int irq_polarity(int idx)
1187 {
1188         return MPBIOS_polarity(idx);
1189 }
1190
1191 static inline int irq_trigger(int idx)
1192 {
1193         return MPBIOS_trigger(idx);
1194 }
1195
1196 static int pin_2_irq(int idx, int apic, int pin)
1197 {
1198         int irq, i;
1199         int bus = mp_irqs[idx].mpc_srcbus;
1200
1201         /*
1202          * Debugging check, we are in big trouble if this message pops up!
1203          */
1204         if (mp_irqs[idx].mpc_dstirq != pin)
1205                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1206
1207         switch (mp_bus_id_to_type[bus])
1208         {
1209                 case MP_BUS_ISA: /* ISA pin */
1210                 case MP_BUS_EISA:
1211                 case MP_BUS_MCA:
1212                 {
1213                         irq = mp_irqs[idx].mpc_srcbusirq;
1214                         break;
1215                 }
1216                 case MP_BUS_PCI: /* PCI pin */
1217                 {
1218                         /*
1219                          * PCI IRQs are mapped in order
1220                          */
1221                         i = irq = 0;
1222                         while (i < apic)
1223                                 irq += nr_ioapic_registers[i++];
1224                         irq += pin;
1225
1226                         /*
1227                          * For MPS mode, so far only needed by ES7000 platform
1228                          */
1229                         if (ioapic_renumber_irq)
1230                                 irq = ioapic_renumber_irq(apic, irq);
1231
1232                         break;
1233                 }
1234                 default:
1235                 {
1236                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1237                         irq = 0;
1238                         break;
1239                 }
1240         }
1241
1242         /*
1243          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1244          */
1245         if ((pin >= 16) && (pin <= 23)) {
1246                 if (pirq_entries[pin-16] != -1) {
1247                         if (!pirq_entries[pin-16]) {
1248                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1249                                                 "disabling PIRQ%d\n", pin-16);
1250                         } else {
1251                                 irq = pirq_entries[pin-16];
1252                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1253                                                 "using PIRQ%d -> IRQ %d\n",
1254                                                 pin-16, irq);
1255                         }
1256                 }
1257         }
1258         return irq;
1259 }
1260
1261 static inline int IO_APIC_irq_trigger(int irq)
1262 {
1263         int apic, idx, pin;
1264
1265         for (apic = 0; apic < nr_ioapics; apic++) {
1266                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1267                         idx = find_irq_entry(apic,pin,mp_INT);
1268                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1269                                 return irq_trigger(idx);
1270                 }
1271         }
1272         /*
1273          * nonexistent IRQs are edge default
1274          */
1275         return 0;
1276 }
1277
1278 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1279 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1280
1281 static int __assign_irq_vector(int irq)
1282 {
1283         struct physdev_irq irq_op;
1284         int vector;
1285
1286         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1287
1288         if (irq_vector[irq] > 0)
1289                 return irq_vector[irq];
1290         irq_op.irq = irq;
1291         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
1292                 return -ENOSPC;
1293
1294         vector = irq_op.vector;
1295         irq_vector[irq] = vector;
1296
1297         return vector;
1298 }
1299
1300 static int assign_irq_vector(int irq)
1301 {
1302         unsigned long flags;
1303         int vector;
1304
1305         spin_lock_irqsave(&vector_lock, flags);
1306         vector = __assign_irq_vector(irq);
1307         spin_unlock_irqrestore(&vector_lock, flags);
1308
1309         return vector;
1310 }
1311 #ifndef CONFIG_XEN
1312 static struct irq_chip ioapic_chip;
1313
1314 #define IOAPIC_AUTO     -1
1315 #define IOAPIC_EDGE     0
1316 #define IOAPIC_LEVEL    1
1317
1318 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1319 {
1320         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1321                         trigger == IOAPIC_LEVEL)
1322                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1323                                          handle_fasteoi_irq, "fasteoi");
1324         else {
1325                 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
1326                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1327                                          handle_edge_irq, "edge");
1328         }
1329         set_intr_gate(vector, interrupt[irq]);
1330 }
1331 #else
1332 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
1333 #endif
1334
1335 static void __init setup_IO_APIC_irqs(void)
1336 {
1337         struct IO_APIC_route_entry entry;
1338         int apic, pin, idx, irq, first_notcon = 1, vector;
1339         unsigned long flags;
1340
1341         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1342
1343         for (apic = 0; apic < nr_ioapics; apic++) {
1344         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1345
1346                 /*
1347                  * add it to the IO-APIC irq-routing table:
1348                  */
1349                 memset(&entry,0,sizeof(entry));
1350
1351                 entry.delivery_mode = INT_DELIVERY_MODE;
1352                 entry.dest_mode = INT_DEST_MODE;
1353                 entry.mask = 0;                         /* enable IRQ */
1354                 entry.dest.logical.logical_dest =
1355                                         cpu_mask_to_apicid(TARGET_CPUS);
1356
1357                 idx = find_irq_entry(apic,pin,mp_INT);
1358                 if (idx == -1) {
1359                         if (first_notcon) {
1360                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1361                                                 " IO-APIC (apicid-pin) %d-%d",
1362                                                 mp_ioapics[apic].mpc_apicid,
1363                                                 pin);
1364                                 first_notcon = 0;
1365                         } else
1366                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1367                                         mp_ioapics[apic].mpc_apicid, pin);
1368                         continue;
1369                 }
1370
1371                 entry.trigger = irq_trigger(idx);
1372                 entry.polarity = irq_polarity(idx);
1373
1374                 if (irq_trigger(idx)) {
1375                         entry.trigger = 1;
1376                         entry.mask = 1;
1377                 }
1378
1379                 irq = pin_2_irq(idx, apic, pin);
1380                 /*
1381                  * skip adding the timer int on secondary nodes, which causes
1382                  * a small but painful rift in the time-space continuum
1383                  */
1384                 if (multi_timer_check(apic, irq))
1385                         continue;
1386                 else
1387                         add_pin_to_irq(irq, apic, pin);
1388
1389                 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1390                         continue;
1391
1392                 if (IO_APIC_IRQ(irq)) {
1393                         vector = assign_irq_vector(irq);
1394                         entry.vector = vector;
1395                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1396
1397                         if (!apic && (irq < 16))
1398                                 disable_8259A_irq(irq);
1399                 }
1400                 spin_lock_irqsave(&ioapic_lock, flags);
1401                 __ioapic_write_entry(apic, pin, entry);
1402                 set_native_irq_info(irq, TARGET_CPUS);
1403                 spin_unlock_irqrestore(&ioapic_lock, flags);
1404         }
1405         }
1406
1407         if (!first_notcon)
1408                 apic_printk(APIC_VERBOSE, " not connected.\n");
1409 }
1410
1411 /*
1412  * Set up the 8259A-master output pin:
1413  */
1414 #ifndef CONFIG_XEN
1415 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1416 {
1417         struct IO_APIC_route_entry entry;
1418
1419         memset(&entry,0,sizeof(entry));
1420
1421         disable_8259A_irq(0);
1422
1423         /* mask LVT0 */
1424         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1425
1426         /*
1427          * We use logical delivery to get the timer IRQ
1428          * to the first CPU.
1429          */
1430         entry.dest_mode = INT_DEST_MODE;
1431         entry.mask = 0;                                 /* unmask IRQ now */
1432         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1433         entry.delivery_mode = INT_DELIVERY_MODE;
1434         entry.polarity = 0;
1435         entry.trigger = 0;
1436         entry.vector = vector;
1437
1438         /*
1439          * The timer IRQ doesn't have to know that behind the
1440          * scene we have a 8259A-master in AEOI mode ...
1441          */
1442         irq_desc[0].chip = &ioapic_chip;
1443         set_irq_handler(0, handle_edge_irq);
1444
1445         /*
1446          * Add it to the IO-APIC irq-routing table:
1447          */
1448         ioapic_write_entry(apic, pin, entry);
1449
1450         enable_8259A_irq(0);
1451 }
1452
1453 static inline void UNEXPECTED_IO_APIC(void)
1454 {
1455 }
1456
1457 void __init print_IO_APIC(void)
1458 {
1459         int apic, i;
1460         union IO_APIC_reg_00 reg_00;
1461         union IO_APIC_reg_01 reg_01;
1462         union IO_APIC_reg_02 reg_02;
1463         union IO_APIC_reg_03 reg_03;
1464         unsigned long flags;
1465
1466         if (apic_verbosity == APIC_QUIET)
1467                 return;
1468
1469         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1470         for (i = 0; i < nr_ioapics; i++)
1471                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1472                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1473
1474         /*
1475          * We are a bit conservative about what we expect.  We have to
1476          * know about every hardware change ASAP.
1477          */
1478         printk(KERN_INFO "testing the IO APIC.......................\n");
1479
1480         for (apic = 0; apic < nr_ioapics; apic++) {
1481
1482         spin_lock_irqsave(&ioapic_lock, flags);
1483         reg_00.raw = io_apic_read(apic, 0);
1484         reg_01.raw = io_apic_read(apic, 1);
1485         if (reg_01.bits.version >= 0x10)
1486                 reg_02.raw = io_apic_read(apic, 2);
1487         if (reg_01.bits.version >= 0x20)
1488                 reg_03.raw = io_apic_read(apic, 3);
1489         spin_unlock_irqrestore(&ioapic_lock, flags);
1490
1491         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1492         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1493         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1494         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1495         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1496         if (reg_00.bits.ID >= get_physical_broadcast())
1497                 UNEXPECTED_IO_APIC();
1498         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1499                 UNEXPECTED_IO_APIC();
1500
1501         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1502         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1503         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1504                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1505                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1506                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1507                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1508                 (reg_01.bits.entries != 0x2E) &&
1509                 (reg_01.bits.entries != 0x3F)
1510         )
1511                 UNEXPECTED_IO_APIC();
1512
1513         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1514         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1515         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1516                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1517                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1518                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1519                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1520         )
1521                 UNEXPECTED_IO_APIC();
1522         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1523                 UNEXPECTED_IO_APIC();
1524
1525         /*
1526          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1527          * but the value of reg_02 is read as the previous read register
1528          * value, so ignore it if reg_02 == reg_01.
1529          */
1530         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1531                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1532                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1533                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1534                         UNEXPECTED_IO_APIC();
1535         }
1536
1537         /*
1538          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1539          * or reg_03, but the value of reg_0[23] is read as the previous read
1540          * register value, so ignore it if reg_03 == reg_0[12].
1541          */
1542         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1543             reg_03.raw != reg_01.raw) {
1544                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1545                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1546                 if (reg_03.bits.__reserved_1)
1547                         UNEXPECTED_IO_APIC();
1548         }
1549
1550         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1551
1552         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1553                           " Stat Dest Deli Vect:   \n");
1554
1555         for (i = 0; i <= reg_01.bits.entries; i++) {
1556                 struct IO_APIC_route_entry entry;
1557
1558                 entry = ioapic_read_entry(apic, i);
1559
1560                 printk(KERN_DEBUG " %02x %03X %02X  ",
1561                         i,
1562                         entry.dest.logical.logical_dest,
1563                         entry.dest.physical.physical_dest
1564                 );
1565
1566                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1567                         entry.mask,
1568                         entry.trigger,
1569                         entry.irr,
1570                         entry.polarity,
1571                         entry.delivery_status,
1572                         entry.dest_mode,
1573                         entry.delivery_mode,
1574                         entry.vector
1575                 );
1576         }
1577         }
1578         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1579         for (i = 0; i < NR_IRQS; i++) {
1580                 struct irq_pin_list *entry = irq_2_pin + i;
1581                 if (entry->pin < 0)
1582                         continue;
1583                 printk(KERN_DEBUG "IRQ%d ", i);
1584                 for (;;) {
1585                         printk("-> %d:%d", entry->apic, entry->pin);
1586                         if (!entry->next)
1587                                 break;
1588                         entry = irq_2_pin + entry->next;
1589                 }
1590                 printk("\n");
1591         }
1592
1593         printk(KERN_INFO ".................................... done.\n");
1594
1595         return;
1596 }
1597
1598 #if 0
1599
1600 static void print_APIC_bitfield (int base)
1601 {
1602         unsigned int v;
1603         int i, j;
1604
1605         if (apic_verbosity == APIC_QUIET)
1606                 return;
1607
1608         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1609         for (i = 0; i < 8; i++) {
1610                 v = apic_read(base + i*0x10);
1611                 for (j = 0; j < 32; j++) {
1612                         if (v & (1<<j))
1613                                 printk("1");
1614                         else
1615                                 printk("0");
1616                 }
1617                 printk("\n");
1618         }
1619 }
1620
1621 void /*__init*/ print_local_APIC(void * dummy)
1622 {
1623         unsigned int v, ver, maxlvt;
1624
1625         if (apic_verbosity == APIC_QUIET)
1626                 return;
1627
1628         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1629                 smp_processor_id(), hard_smp_processor_id());
1630         v = apic_read(APIC_ID);
1631         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1632         v = apic_read(APIC_LVR);
1633         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1634         ver = GET_APIC_VERSION(v);
1635         maxlvt = get_maxlvt();
1636
1637         v = apic_read(APIC_TASKPRI);
1638         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1639
1640         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1641                 v = apic_read(APIC_ARBPRI);
1642                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1643                         v & APIC_ARBPRI_MASK);
1644                 v = apic_read(APIC_PROCPRI);
1645                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1646         }
1647
1648         v = apic_read(APIC_EOI);
1649         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1650         v = apic_read(APIC_RRR);
1651         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1652         v = apic_read(APIC_LDR);
1653         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1654         v = apic_read(APIC_DFR);
1655         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1656         v = apic_read(APIC_SPIV);
1657         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1658
1659         printk(KERN_DEBUG "... APIC ISR field:\n");
1660         print_APIC_bitfield(APIC_ISR);
1661         printk(KERN_DEBUG "... APIC TMR field:\n");
1662         print_APIC_bitfield(APIC_TMR);
1663         printk(KERN_DEBUG "... APIC IRR field:\n");
1664         print_APIC_bitfield(APIC_IRR);
1665
1666         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1667                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1668                         apic_write(APIC_ESR, 0);
1669                 v = apic_read(APIC_ESR);
1670                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1671         }
1672
1673         v = apic_read(APIC_ICR);
1674         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1675         v = apic_read(APIC_ICR2);
1676         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1677
1678         v = apic_read(APIC_LVTT);
1679         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1680
1681         if (maxlvt > 3) {                       /* PC is LVT#4. */
1682                 v = apic_read(APIC_LVTPC);
1683                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1684         }
1685         v = apic_read(APIC_LVT0);
1686         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1687         v = apic_read(APIC_LVT1);
1688         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1689
1690         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1691                 v = apic_read(APIC_LVTERR);
1692                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1693         }
1694
1695         v = apic_read(APIC_TMICT);
1696         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1697         v = apic_read(APIC_TMCCT);
1698         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1699         v = apic_read(APIC_TDCR);
1700         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1701         printk("\n");
1702 }
1703
1704 void print_all_local_APICs (void)
1705 {
1706         on_each_cpu(print_local_APIC, NULL, 1, 1);
1707 }
1708
1709 void /*__init*/ print_PIC(void)
1710 {
1711         unsigned int v;
1712         unsigned long flags;
1713
1714         if (apic_verbosity == APIC_QUIET)
1715                 return;
1716
1717         printk(KERN_DEBUG "\nprinting PIC contents\n");
1718
1719         spin_lock_irqsave(&i8259A_lock, flags);
1720
1721         v = inb(0xa1) << 8 | inb(0x21);
1722         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1723
1724         v = inb(0xa0) << 8 | inb(0x20);
1725         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1726
1727         outb(0x0b,0xa0);
1728         outb(0x0b,0x20);
1729         v = inb(0xa0) << 8 | inb(0x20);
1730         outb(0x0a,0xa0);
1731         outb(0x0a,0x20);
1732
1733         spin_unlock_irqrestore(&i8259A_lock, flags);
1734
1735         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1736
1737         v = inb(0x4d1) << 8 | inb(0x4d0);
1738         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1739 }
1740
1741 #endif  /*  0  */
1742
1743 #else
1744 void __init print_IO_APIC(void) { }
1745 #endif /* !CONFIG_XEN */
1746
1747 static void __init enable_IO_APIC(void)
1748 {
1749         union IO_APIC_reg_01 reg_01;
1750         int i8259_apic, i8259_pin;
1751         int i, apic;
1752         unsigned long flags;
1753
1754         for (i = 0; i < PIN_MAP_SIZE; i++) {
1755                 irq_2_pin[i].pin = -1;
1756                 irq_2_pin[i].next = 0;
1757         }
1758         if (!pirqs_enabled)
1759                 for (i = 0; i < MAX_PIRQS; i++)
1760                         pirq_entries[i] = -1;
1761
1762         /*
1763          * The number of IO-APIC IRQ registers (== #pins):
1764          */
1765         for (apic = 0; apic < nr_ioapics; apic++) {
1766                 spin_lock_irqsave(&ioapic_lock, flags);
1767                 reg_01.raw = io_apic_read(apic, 1);
1768                 spin_unlock_irqrestore(&ioapic_lock, flags);
1769                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1770         }
1771         for(apic = 0; apic < nr_ioapics; apic++) {
1772                 int pin;
1773                 /* See if any of the pins is in ExtINT mode */
1774                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1775                         struct IO_APIC_route_entry entry;
1776                         entry = ioapic_read_entry(apic, pin);
1777
1778
1779                         /* If the interrupt line is enabled and in ExtInt mode
1780                          * I have found the pin where the i8259 is connected.
1781                          */
1782                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1783                                 ioapic_i8259.apic = apic;
1784                                 ioapic_i8259.pin  = pin;
1785                                 goto found_i8259;
1786                         }
1787                 }
1788         }
1789  found_i8259:
1790         /* Look to see what if the MP table has reported the ExtINT */
1791         /* If we could not find the appropriate pin by looking at the ioapic
1792          * the i8259 probably is not connected the ioapic but give the
1793          * mptable a chance anyway.
1794          */
1795         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1796         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1797         /* Trust the MP table if nothing is setup in the hardware */
1798         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1799                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1800                 ioapic_i8259.pin  = i8259_pin;
1801                 ioapic_i8259.apic = i8259_apic;
1802         }
1803         /* Complain if the MP table and the hardware disagree */
1804         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1805                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1806         {
1807                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1808         }
1809
1810         /*
1811          * Do not trust the IO-APIC being empty at bootup
1812          */
1813         clear_IO_APIC();
1814 }
1815
1816 /*
1817  * Not an __init, needed by the reboot code
1818  */
1819 void disable_IO_APIC(void)
1820 {
1821         /*
1822          * Clear the IO-APIC before rebooting:
1823          */
1824         clear_IO_APIC();
1825
1826 #ifndef CONFIG_XEN
1827         /*
1828          * If the i8259 is routed through an IOAPIC
1829          * Put that IOAPIC in virtual wire mode
1830          * so legacy interrupts can be delivered.
1831          */
1832         if (ioapic_i8259.pin != -1) {
1833                 struct IO_APIC_route_entry entry;
1834
1835                 memset(&entry, 0, sizeof(entry));
1836                 entry.mask            = 0; /* Enabled */
1837                 entry.trigger         = 0; /* Edge */
1838                 entry.irr             = 0;
1839                 entry.polarity        = 0; /* High */
1840                 entry.delivery_status = 0;
1841                 entry.dest_mode       = 0; /* Physical */
1842                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1843                 entry.vector          = 0;
1844                 entry.dest.physical.physical_dest =
1845                                         GET_APIC_ID(apic_read(APIC_ID));
1846
1847                 /*
1848                  * Add it to the IO-APIC irq-routing table:
1849                  */
1850                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1851         }
1852         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1853 #endif
1854 }
1855
1856 /*
1857  * function to set the IO-APIC physical IDs based on the
1858  * values stored in the MPC table.
1859  *
1860  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1861  */
1862
1863 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1864 static void __init setup_ioapic_ids_from_mpc(void)
1865 {
1866         union IO_APIC_reg_00 reg_00;
1867         physid_mask_t phys_id_present_map;
1868         int apic;
1869         int i;
1870         unsigned char old_id;
1871         unsigned long flags;
1872
1873         /*
1874          * Don't check I/O APIC IDs for xAPIC systems.  They have
1875          * no meaning without the serial APIC bus.
1876          */
1877         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1878                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1879                 return;
1880         /*
1881          * This is broken; anything with a real cpu count has to
1882          * circumvent this idiocy regardless.
1883          */
1884         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1885
1886         /*
1887          * Set the IOAPIC ID to the value stored in the MPC table.
1888          */
1889         for (apic = 0; apic < nr_ioapics; apic++) {
1890
1891                 /* Read the register 0 value */
1892                 spin_lock_irqsave(&ioapic_lock, flags);
1893                 reg_00.raw = io_apic_read(apic, 0);
1894                 spin_unlock_irqrestore(&ioapic_lock, flags);
1895
1896                 old_id = mp_ioapics[apic].mpc_apicid;
1897
1898                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1899                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1900                                 apic, mp_ioapics[apic].mpc_apicid);
1901                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1902                                 reg_00.bits.ID);
1903                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1904                 }
1905
1906                 /*
1907                  * Sanity check, is the ID really free? Every APIC in a
1908                  * system must have a unique ID or we get lots of nice
1909                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1910                  */
1911                 if (check_apicid_used(phys_id_present_map,
1912                                         mp_ioapics[apic].mpc_apicid)) {
1913                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1914                                 apic, mp_ioapics[apic].mpc_apicid);
1915                         for (i = 0; i < get_physical_broadcast(); i++)
1916                                 if (!physid_isset(i, phys_id_present_map))
1917                                         break;
1918                         if (i >= get_physical_broadcast())
1919                                 panic("Max APIC ID exceeded!\n");
1920                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1921                                 i);
1922                         physid_set(i, phys_id_present_map);
1923                         mp_ioapics[apic].mpc_apicid = i;
1924                 } else {
1925                         physid_mask_t tmp;
1926                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1927                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1928                                         "phys_id_present_map\n",
1929                                         mp_ioapics[apic].mpc_apicid);
1930                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1931                 }
1932
1933
1934                 /*
1935                  * We need to adjust the IRQ routing table
1936                  * if the ID changed.
1937                  */
1938                 if (old_id != mp_ioapics[apic].mpc_apicid)
1939                         for (i = 0; i < mp_irq_entries; i++)
1940                                 if (mp_irqs[i].mpc_dstapic == old_id)
1941                                         mp_irqs[i].mpc_dstapic
1942                                                 = mp_ioapics[apic].mpc_apicid;
1943
1944                 /*
1945                  * Read the right value from the MPC table and
1946                  * write it into the ID register.
1947                  */
1948                 apic_printk(APIC_VERBOSE, KERN_INFO
1949                         "...changing IO-APIC physical APIC ID to %d ...",
1950                         mp_ioapics[apic].mpc_apicid);
1951
1952                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1953                 spin_lock_irqsave(&ioapic_lock, flags);
1954                 io_apic_write(apic, 0, reg_00.raw);
1955                 spin_unlock_irqrestore(&ioapic_lock, flags);
1956
1957                 /*
1958                  * Sanity check
1959                  */
1960                 spin_lock_irqsave(&ioapic_lock, flags);
1961                 reg_00.raw = io_apic_read(apic, 0);
1962                 spin_unlock_irqrestore(&ioapic_lock, flags);
1963                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1964                         printk("could not set ID!\n");
1965                 else
1966                         apic_printk(APIC_VERBOSE, " ok.\n");
1967         }
1968 }
1969 #else
1970 static void __init setup_ioapic_ids_from_mpc(void) { }
1971 #endif
1972
1973 static int no_timer_check __initdata;
1974
1975 static int __init notimercheck(char *s)
1976 {
1977         no_timer_check = 1;
1978         return 1;
1979 }
1980 __setup("no_timer_check", notimercheck);
1981
1982 #ifndef CONFIG_XEN
1983 /*
1984  * There is a nasty bug in some older SMP boards, their mptable lies
1985  * about the timer IRQ. We do the following to work around the situation:
1986  *
1987  *      - timer IRQ defaults to IO-APIC IRQ
1988  *      - if this function detects that timer IRQs are defunct, then we fall
1989  *        back to ISA timer IRQs
1990  */
1991 int __init timer_irq_works(void)
1992 {
1993         unsigned long t1 = jiffies;
1994
1995         if (no_timer_check)
1996                 return 1;
1997
1998         local_irq_enable();
1999         /* Let ten ticks pass... */
2000         mdelay((10 * 1000) / HZ);
2001
2002         /*
2003          * Expect a few ticks at least, to be sure some possible
2004          * glue logic does not lock up after one or two first
2005          * ticks in a non-ExtINT mode.  Also the local APIC
2006          * might have cached one ExtINT interrupt.  Finally, at
2007          * least one tick may be lost due to delays.
2008          */
2009         if (jiffies - t1 > 4)
2010                 return 1;
2011
2012         return 0;
2013 }
2014
2015 /*
2016  * In the SMP+IOAPIC case it might happen that there are an unspecified
2017  * number of pending IRQ events unhandled. These cases are very rare,
2018  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2019  * better to do it this way as thus we do not have to be aware of
2020  * 'pending' interrupts in the IRQ path, except at this point.
2021  */
2022 /*
2023  * Edge triggered needs to resend any interrupt
2024  * that was delayed but this is now handled in the device
2025  * independent code.
2026  */
2027
2028 /*
2029  * Startup quirk:
2030  *
2031  * Starting up a edge-triggered IO-APIC interrupt is
2032  * nasty - we need to make sure that we get the edge.
2033  * If it is already asserted for some reason, we need
2034  * return 1 to indicate that is was pending.
2035  *
2036  * This is not complete - we should be able to fake
2037  * an edge even if it isn't on the 8259A...
2038  *
2039  * (We do this for level-triggered IRQs too - it cannot hurt.)
2040  */
2041 static unsigned int startup_ioapic_irq(unsigned int irq)
2042 {
2043         int was_pending = 0;
2044         unsigned long flags;
2045
2046         spin_lock_irqsave(&ioapic_lock, flags);
2047         if (irq < 16) {
2048                 disable_8259A_irq(irq);
2049                 if (i8259A_irq_pending(irq))
2050                         was_pending = 1;
2051         }
2052         __unmask_IO_APIC_irq(irq);
2053         spin_unlock_irqrestore(&ioapic_lock, flags);
2054
2055         return was_pending;
2056 }
2057
2058 static void ack_ioapic_irq(unsigned int irq)
2059 {
2060         move_native_irq(irq);
2061         ack_APIC_irq();
2062 }
2063
2064 static void ack_ioapic_quirk_irq(unsigned int irq)
2065 {
2066         unsigned long v;
2067         int i;
2068
2069         move_native_irq(irq);
2070 /*
2071  * It appears there is an erratum which affects at least version 0x11
2072  * of I/O APIC (that's the 82093AA and cores integrated into various
2073  * chipsets).  Under certain conditions a level-triggered interrupt is
2074  * erroneously delivered as edge-triggered one but the respective IRR
2075  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2076  * message but it will never arrive and further interrupts are blocked
2077  * from the source.  The exact reason is so far unknown, but the
2078  * phenomenon was observed when two consecutive interrupt requests
2079  * from a given source get delivered to the same CPU and the source is
2080  * temporarily disabled in between.
2081  *
2082  * A workaround is to simulate an EOI message manually.  We achieve it
2083  * by setting the trigger mode to edge and then to level when the edge
2084  * trigger mode gets detected in the TMR of a local APIC for a
2085  * level-triggered interrupt.  We mask the source for the time of the
2086  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2087  * The idea is from Manfred Spraul.  --macro
2088  */
2089         i = irq_vector[irq];
2090
2091         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2092
2093         ack_APIC_irq();
2094
2095         if (!(v & (1 << (i & 0x1f)))) {
2096                 atomic_inc(&irq_mis_count);
2097                 spin_lock(&ioapic_lock);
2098                 __mask_and_edge_IO_APIC_irq(irq);
2099                 __unmask_and_level_IO_APIC_irq(irq);
2100                 spin_unlock(&ioapic_lock);
2101         }
2102 }
2103
2104 static int ioapic_retrigger_irq(unsigned int irq)
2105 {
2106         send_IPI_self(irq_vector[irq]);
2107
2108         return 1;
2109 }
2110
2111 static struct irq_chip ioapic_chip __read_mostly = {
2112         .name           = "IO-APIC",
2113         .startup        = startup_ioapic_irq,
2114         .mask           = mask_IO_APIC_irq,
2115         .unmask         = unmask_IO_APIC_irq,
2116         .ack            = ack_ioapic_irq,
2117         .eoi            = ack_ioapic_quirk_irq,
2118 #ifdef CONFIG_SMP
2119         .set_affinity   = set_ioapic_affinity_irq,
2120 #endif
2121         .retrigger      = ioapic_retrigger_irq,
2122 };
2123
2124 #endif /* !CONFIG_XEN */
2125
2126 static inline void init_IO_APIC_traps(void)
2127 {
2128         int irq;
2129
2130         /*
2131          * NOTE! The local APIC isn't very good at handling
2132          * multiple interrupts at the same interrupt level.
2133          * As the interrupt level is determined by taking the
2134          * vector number and shifting that right by 4, we
2135          * want to spread these out a bit so that they don't
2136          * all fall in the same interrupt level.
2137          *
2138          * Also, we've got to be careful not to trash gate
2139          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2140          */
2141         for (irq = 0; irq < NR_IRQS ; irq++) {
2142                 int tmp = irq;
2143                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2144                         /*
2145                          * Hmm.. We don't have an entry for this,
2146                          * so default to an old-fashioned 8259
2147                          * interrupt if we can..
2148                          */
2149                         if (irq < 16)
2150                                 make_8259A_irq(irq);
2151 #ifndef CONFIG_XEN
2152                         else
2153                                 /* Strange. Oh, well.. */
2154                                 irq_desc[irq].chip = &no_irq_chip;
2155 #endif
2156                 }
2157         }
2158 }
2159
2160 #ifndef CONFIG_XEN
2161 /*
2162  * The local APIC irq-chip implementation:
2163  */
2164
2165 static void ack_apic(unsigned int irq)
2166 {
2167         ack_APIC_irq();
2168 }
2169
2170 static void mask_lapic_irq (unsigned int irq)
2171 {
2172         unsigned long v;
2173
2174         v = apic_read(APIC_LVT0);
2175         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2176 }
2177
2178 static void unmask_lapic_irq (unsigned int irq)
2179 {
2180         unsigned long v;
2181
2182         v = apic_read(APIC_LVT0);
2183         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2184 }
2185
2186 static struct irq_chip lapic_chip __read_mostly = {
2187         .name           = "local-APIC-edge",
2188         .mask           = mask_lapic_irq,
2189         .unmask         = unmask_lapic_irq,
2190         .eoi            = ack_apic,
2191 };
2192
2193 static void setup_nmi (void)
2194 {
2195         /*
2196          * Dirty trick to enable the NMI watchdog ...
2197          * We put the 8259A master into AEOI mode and
2198          * unmask on all local APICs LVT0 as NMI.
2199          *
2200          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2201          * is from Maciej W. Rozycki - so we do not have to EOI from
2202          * the NMI handler or the timer interrupt.
2203          */
2204         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2205
2206         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2207
2208         apic_printk(APIC_VERBOSE, " done.\n");
2209 }
2210
2211 /*
2212  * This looks a bit hackish but it's about the only one way of sending
2213  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2214  * not support the ExtINT mode, unfortunately.  We need to send these
2215  * cycles as some i82489DX-based boards have glue logic that keeps the
2216  * 8259A interrupt line asserted until INTA.  --macro
2217  */
2218 static inline void unlock_ExtINT_logic(void)
2219 {
2220         int apic, pin, i;
2221         struct IO_APIC_route_entry entry0, entry1;
2222         unsigned char save_control, save_freq_select;
2223
2224         pin  = find_isa_irq_pin(8, mp_INT);
2225         if (pin == -1) {
2226                 WARN_ON_ONCE(1);
2227                 return;
2228         }
2229         apic = find_isa_irq_apic(8, mp_INT);
2230         if (apic == -1) {
2231                 WARN_ON_ONCE(1);
2232                 return;
2233         }
2234
2235         entry0 = ioapic_read_entry(apic, pin);
2236         clear_IO_APIC_pin(apic, pin);
2237
2238         memset(&entry1, 0, sizeof(entry1));
2239
2240         entry1.dest_mode = 0;                   /* physical delivery */
2241         entry1.mask = 0;                        /* unmask IRQ now */
2242         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2243         entry1.delivery_mode = dest_ExtINT;
2244         entry1.polarity = entry0.polarity;
2245         entry1.trigger = 0;
2246         entry1.vector = 0;
2247
2248         ioapic_write_entry(apic, pin, entry1);
2249
2250         save_control = CMOS_READ(RTC_CONTROL);
2251         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2252         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2253                    RTC_FREQ_SELECT);
2254         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2255
2256         i = 100;
2257         while (i-- > 0) {
2258                 mdelay(10);
2259                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2260                         i -= 10;
2261         }
2262
2263         CMOS_WRITE(save_control, RTC_CONTROL);
2264         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2265         clear_IO_APIC_pin(apic, pin);
2266
2267         ioapic_write_entry(apic, pin, entry0);
2268 }
2269 #endif /* !CONFIG_XEN */
2270
2271 int timer_uses_ioapic_pin_0;
2272
2273 #ifndef CONFIG_XEN
2274 /*
2275  * This code may look a bit paranoid, but it's supposed to cooperate with
2276  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2277  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2278  * fanatically on his truly buggy board.
2279  */
2280 static inline void __init check_timer(void)
2281 {
2282         int apic1, pin1, apic2, pin2;
2283         int vector;
2284
2285         /*
2286          * get/set the timer IRQ vector:
2287          */
2288         disable_8259A_irq(0);
2289         vector = assign_irq_vector(0);
2290         set_intr_gate(vector, interrupt[0]);
2291
2292         /*
2293          * Subtle, code in do_timer_interrupt() expects an AEOI
2294          * mode for the 8259A whenever interrupts are routed
2295          * through I/O APICs.  Also IRQ0 has to be enabled in
2296          * the 8259A which implies the virtual wire has to be
2297          * disabled in the local APIC.
2298          */
2299         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2300         init_8259A(1);
2301         timer_ack = 1;
2302         if (timer_over_8254 > 0)
2303                 enable_8259A_irq(0);
2304
2305         pin1  = find_isa_irq_pin(0, mp_INT);
2306         apic1 = find_isa_irq_apic(0, mp_INT);
2307         pin2  = ioapic_i8259.pin;
2308         apic2 = ioapic_i8259.apic;
2309
2310         if (pin1 == 0)
2311                 timer_uses_ioapic_pin_0 = 1;
2312
2313         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2314                 vector, apic1, pin1, apic2, pin2);
2315
2316         if (pin1 != -1) {
2317                 /*
2318                  * Ok, does IRQ0 through the IOAPIC work?
2319                  */
2320                 unmask_IO_APIC_irq(0);
2321                 if (timer_irq_works()) {
2322                         if (nmi_watchdog == NMI_IO_APIC) {
2323                                 disable_8259A_irq(0);
2324                                 setup_nmi();
2325                                 enable_8259A_irq(0);
2326                         }
2327                         if (disable_timer_pin_1 > 0)
2328                                 clear_IO_APIC_pin(0, pin1);
2329                         return;
2330                 }
2331                 clear_IO_APIC_pin(apic1, pin1);
2332                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2333                                 "IO-APIC\n");
2334         }
2335
2336         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2337         if (pin2 != -1) {
2338                 printk("\n..... (found pin %d) ...", pin2);
2339                 /*
2340                  * legacy devices should be connected to IO APIC #0
2341                  */
2342                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2343                 if (timer_irq_works()) {
2344                         printk("works.\n");
2345                         if (pin1 != -1)
2346                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2347                         else
2348                                 add_pin_to_irq(0, apic2, pin2);
2349                         if (nmi_watchdog == NMI_IO_APIC) {
2350                                 setup_nmi();
2351                         }
2352                         return;
2353                 }
2354                 /*
2355                  * Cleanup, just in case ...
2356                  */
2357                 clear_IO_APIC_pin(apic2, pin2);
2358         }
2359         printk(" failed.\n");
2360
2361         if (nmi_watchdog == NMI_IO_APIC) {
2362                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2363                 nmi_watchdog = 0;
2364         }
2365
2366         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2367
2368         disable_8259A_irq(0);
2369         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2370                                       "fasteio");
2371         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2372         enable_8259A_irq(0);
2373
2374         if (timer_irq_works()) {
2375                 printk(" works.\n");
2376                 return;
2377         }
2378         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2379         printk(" failed.\n");
2380
2381         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2382
2383         timer_ack = 0;
2384         init_8259A(0);
2385         make_8259A_irq(0);
2386         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2387
2388         unlock_ExtINT_logic();
2389
2390         if (timer_irq_works()) {
2391                 printk(" works.\n");
2392                 return;
2393         }
2394         printk(" failed :(.\n");
2395         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2396                 "report.  Then try booting with the 'noapic' option");
2397 }
2398 #else
2399 #define check_timer() ((void)0)
2400 #endif /* CONFIG_XEN */
2401
2402 /*
2403  *
2404  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2405  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2406  *   Linux doesn't really care, as it's not actually used
2407  *   for any interrupt handling anyway.
2408  */
2409 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2410
2411 void __init setup_IO_APIC(void)
2412 {
2413         enable_IO_APIC();
2414
2415         if (acpi_ioapic)
2416                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2417         else
2418                 io_apic_irqs = ~PIC_IRQS;
2419
2420         printk("ENABLING IO-APIC IRQs\n");
2421
2422         /*
2423          * Set up IO-APIC IRQ routing.
2424          */
2425         if (!acpi_ioapic)
2426                 setup_ioapic_ids_from_mpc();
2427 #ifndef CONFIG_XEN
2428         sync_Arb_IDs();
2429 #endif
2430         setup_IO_APIC_irqs();
2431         init_IO_APIC_traps();
2432         check_timer();
2433         if (!acpi_ioapic)
2434                 print_IO_APIC();
2435 }
2436
2437 static int __init setup_disable_8254_timer(char *s)
2438 {
2439         timer_over_8254 = -1;
2440         return 1;
2441 }
2442 static int __init setup_enable_8254_timer(char *s)
2443 {
2444         timer_over_8254 = 2;
2445         return 1;
2446 }
2447
2448 __setup("disable_8254_timer", setup_disable_8254_timer);
2449 __setup("enable_8254_timer", setup_enable_8254_timer);
2450
2451 /*
2452  *      Called after all the initialization is done. If we didnt find any
2453  *      APIC bugs then we can allow the modify fast path
2454  */
2455
2456 static int __init io_apic_bug_finalize(void)
2457 {
2458         if(sis_apic_bug == -1)
2459                 sis_apic_bug = 0;
2460         if (is_initial_xendomain()) {
2461                 dom0_op_t op = { .cmd = DOM0_PLATFORM_QUIRK };
2462                 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2463                         QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2464                 HYPERVISOR_dom0_op(&op);
2465         }
2466         return 0;
2467 }
2468
2469 late_initcall(io_apic_bug_finalize);
2470
2471 struct sysfs_ioapic_data {
2472         struct sys_device dev;
2473         struct IO_APIC_route_entry entry[0];
2474 };
2475 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2476
2477 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2478 {
2479         struct IO_APIC_route_entry *entry;
2480         struct sysfs_ioapic_data *data;
2481         int i;
2482
2483         data = container_of(dev, struct sysfs_ioapic_data, dev);
2484         entry = data->entry;
2485         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2486                 entry[i] = ioapic_read_entry(dev->id, i);
2487
2488         return 0;
2489 }
2490
2491 static int ioapic_resume(struct sys_device *dev)
2492 {
2493         struct IO_APIC_route_entry *entry;
2494         struct sysfs_ioapic_data *data;
2495         unsigned long flags;
2496         union IO_APIC_reg_00 reg_00;
2497         int i;
2498
2499         data = container_of(dev, struct sysfs_ioapic_data, dev);
2500         entry = data->entry;
2501
2502         spin_lock_irqsave(&ioapic_lock, flags);
2503         reg_00.raw = io_apic_read(dev->id, 0);
2504         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2505                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2506                 io_apic_write(dev->id, 0, reg_00.raw);
2507         }
2508         spin_unlock_irqrestore(&ioapic_lock, flags);
2509         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2510                 ioapic_write_entry(dev->id, i, entry[i]);
2511
2512         return 0;
2513 }
2514
2515 static struct sysdev_class ioapic_sysdev_class = {
2516         set_kset_name("ioapic"),
2517         .suspend = ioapic_suspend,
2518         .resume = ioapic_resume,
2519 };
2520
2521 static int __init ioapic_init_sysfs(void)
2522 {
2523         struct sys_device * dev;
2524         int i, size, error = 0;
2525
2526         error = sysdev_class_register(&ioapic_sysdev_class);
2527         if (error)
2528                 return error;
2529
2530         for (i = 0; i < nr_ioapics; i++ ) {
2531                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2532                         * sizeof(struct IO_APIC_route_entry);
2533                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2534                 if (!mp_ioapic_data[i]) {
2535                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2536                         continue;
2537                 }
2538                 memset(mp_ioapic_data[i], 0, size);
2539                 dev = &mp_ioapic_data[i]->dev;
2540                 dev->id = i;
2541                 dev->cls = &ioapic_sysdev_class;
2542                 error = sysdev_register(dev);
2543                 if (error) {
2544                         kfree(mp_ioapic_data[i]);
2545                         mp_ioapic_data[i] = NULL;
2546                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2547                         continue;
2548                 }
2549         }
2550
2551         return 0;
2552 }
2553
2554 device_initcall(ioapic_init_sysfs);
2555
2556 /*
2557  * Dynamic irq allocate and deallocation
2558  */
2559 int create_irq(void)
2560 {
2561         /* Allocate an unused irq */
2562         int irq, new, vector = 0;
2563         unsigned long flags;
2564
2565         irq = -ENOSPC;
2566         spin_lock_irqsave(&vector_lock, flags);
2567         for (new = (NR_IRQS - 1); new >= 0; new--) {
2568                 if (platform_legacy_irq(new))
2569                         continue;
2570                 if (irq_vector[new] != 0)
2571                         continue;
2572                 vector = __assign_irq_vector(new);
2573                 if (likely(vector > 0))
2574                         irq = new;
2575                 break;
2576         }
2577         spin_unlock_irqrestore(&vector_lock, flags);
2578
2579         if (irq >= 0) {
2580 #ifndef CONFIG_XEN
2581                 set_intr_gate(vector, interrupt[irq]);
2582 #endif
2583                 dynamic_irq_init(irq);
2584         }
2585         return irq;
2586 }
2587
2588 void destroy_irq(unsigned int irq)
2589 {
2590         unsigned long flags;
2591
2592         dynamic_irq_cleanup(irq);
2593
2594         spin_lock_irqsave(&vector_lock, flags);
2595         irq_vector[irq] = 0;
2596         spin_unlock_irqrestore(&vector_lock, flags);
2597 }
2598
2599 /*
2600  * MSI mesage composition
2601  */
2602 #ifdef CONFIG_PCI_MSI
2603 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2604 {
2605         int vector;
2606         unsigned dest;
2607
2608         vector = assign_irq_vector(irq);
2609         if (vector >= 0) {
2610                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2611
2612                 msg->address_hi = MSI_ADDR_BASE_HI;
2613                 msg->address_lo =
2614                         MSI_ADDR_BASE_LO |
2615                         ((INT_DEST_MODE == 0) ?
2616                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2617                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2618                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2619                                 MSI_ADDR_REDIRECTION_CPU:
2620                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2621                         MSI_ADDR_DEST_ID(dest);
2622
2623                 msg->data =
2624                         MSI_DATA_TRIGGER_EDGE |
2625                         MSI_DATA_LEVEL_ASSERT |
2626                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2627                                 MSI_DATA_DELIVERY_FIXED:
2628                                 MSI_DATA_DELIVERY_LOWPRI) |
2629                         MSI_DATA_VECTOR(vector);
2630         }
2631         return vector;
2632 }
2633
2634 #ifdef CONFIG_SMP
2635 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2636 {
2637         struct msi_msg msg;
2638         unsigned int dest;
2639         cpumask_t tmp;
2640         int vector;
2641
2642         cpus_and(tmp, mask, cpu_online_map);
2643         if (cpus_empty(tmp))
2644                 tmp = TARGET_CPUS;
2645
2646         vector = assign_irq_vector(irq);
2647         if (vector < 0)
2648                 return;
2649
2650         dest = cpu_mask_to_apicid(mask);
2651
2652         read_msi_msg(irq, &msg);
2653
2654         msg.data &= ~MSI_DATA_VECTOR_MASK;
2655         msg.data |= MSI_DATA_VECTOR(vector);
2656         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2657         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2658
2659         write_msi_msg(irq, &msg);
2660         set_native_irq_info(irq, mask);
2661 }
2662 #endif /* CONFIG_SMP */
2663
2664 /*
2665  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2666  * which implement the MSI or MSI-X Capability Structure.
2667  */
2668 static struct irq_chip msi_chip = {
2669         .name           = "PCI-MSI",
2670         .unmask         = unmask_msi_irq,
2671         .mask           = mask_msi_irq,
2672         .ack            = ack_ioapic_irq,
2673 #ifdef CONFIG_SMP
2674         .set_affinity   = set_msi_irq_affinity,
2675 #endif
2676         .retrigger      = ioapic_retrigger_irq,
2677 };
2678
2679 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
2680 {
2681         struct msi_msg msg;
2682         int ret;
2683         ret = msi_compose_msg(dev, irq, &msg);
2684         if (ret < 0)
2685                 return ret;
2686
2687         write_msi_msg(irq, &msg);
2688
2689         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2690                                       "edge");
2691
2692         return 0;
2693 }
2694
2695 void arch_teardown_msi_irq(unsigned int irq)
2696 {
2697         return;
2698 }
2699
2700 #endif /* CONFIG_PCI_MSI */
2701
2702 /*
2703  * Hypertransport interrupt support
2704  */
2705 #ifdef CONFIG_HT_IRQ
2706
2707 #ifdef CONFIG_SMP
2708
2709 static void target_ht_irq(unsigned int irq, unsigned int dest)
2710 {
2711         struct ht_irq_msg msg;
2712         fetch_ht_irq_msg(irq, &msg);
2713
2714         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2715         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2716
2717         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2718         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2719
2720         write_ht_irq_msg(irq, &msg);
2721 }
2722
2723 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2724 {
2725         unsigned int dest;
2726         cpumask_t tmp;
2727
2728         cpus_and(tmp, mask, cpu_online_map);
2729         if (cpus_empty(tmp))
2730                 tmp = TARGET_CPUS;
2731
2732         cpus_and(mask, tmp, CPU_MASK_ALL);
2733
2734         dest = cpu_mask_to_apicid(mask);
2735
2736         target_ht_irq(irq, dest);
2737         set_native_irq_info(irq, mask);
2738 }
2739 #endif
2740
2741 static struct irq_chip ht_irq_chip = {
2742         .name           = "PCI-HT",
2743         .mask           = mask_ht_irq,
2744         .unmask         = unmask_ht_irq,
2745         .ack            = ack_ioapic_irq,
2746 #ifdef CONFIG_SMP
2747         .set_affinity   = set_ht_irq_affinity,
2748 #endif
2749         .retrigger      = ioapic_retrigger_irq,
2750 };
2751
2752 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2753 {
2754         int vector;
2755
2756         vector = assign_irq_vector(irq);
2757         if (vector >= 0) {
2758                 struct ht_irq_msg msg;
2759                 unsigned dest;
2760                 cpumask_t tmp;
2761
2762                 cpus_clear(tmp);
2763                 cpu_set(vector >> 8, tmp);
2764                 dest = cpu_mask_to_apicid(tmp);
2765
2766                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2767
2768                 msg.address_lo =
2769                         HT_IRQ_LOW_BASE |
2770                         HT_IRQ_LOW_DEST_ID(dest) |
2771                         HT_IRQ_LOW_VECTOR(vector) |
2772                         ((INT_DEST_MODE == 0) ?
2773                                 HT_IRQ_LOW_DM_PHYSICAL :
2774                                 HT_IRQ_LOW_DM_LOGICAL) |
2775                         HT_IRQ_LOW_RQEOI_EDGE |
2776                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2777                                 HT_IRQ_LOW_MT_FIXED :
2778                                 HT_IRQ_LOW_MT_ARBITRATED) |
2779                         HT_IRQ_LOW_IRQ_MASKED;
2780
2781                 write_ht_irq_msg(irq, &msg);
2782
2783                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2784                                               handle_edge_irq, "edge");
2785         }
2786         return vector;
2787 }
2788 #endif /* CONFIG_HT_IRQ */
2789
2790 /* --------------------------------------------------------------------------
2791                           ACPI-based IOAPIC Configuration
2792    -------------------------------------------------------------------------- */
2793
2794 #ifdef CONFIG_ACPI
2795
2796 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2797 {
2798 #ifndef CONFIG_XEN
2799         union IO_APIC_reg_00 reg_00;
2800         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2801         physid_mask_t tmp;
2802         unsigned long flags;
2803         int i = 0;
2804
2805         /*
2806          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2807          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2808          * supports up to 16 on one shared APIC bus.
2809          *
2810          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2811          *      advantage of new APIC bus architecture.
2812          */
2813
2814         if (physids_empty(apic_id_map))
2815                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2816
2817         spin_lock_irqsave(&ioapic_lock, flags);
2818         reg_00.raw = io_apic_read(ioapic, 0);
2819         spin_unlock_irqrestore(&ioapic_lock, flags);
2820
2821         if (apic_id >= get_physical_broadcast()) {
2822                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2823                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2824                 apic_id = reg_00.bits.ID;
2825         }
2826
2827         /*
2828          * Every APIC in a system must have a unique ID or we get lots of nice
2829          * 'stuck on smp_invalidate_needed IPI wait' messages.
2830          */
2831         if (check_apicid_used(apic_id_map, apic_id)) {
2832
2833                 for (i = 0; i < get_physical_broadcast(); i++) {
2834                         if (!check_apicid_used(apic_id_map, i))
2835                                 break;
2836                 }
2837
2838                 if (i == get_physical_broadcast())
2839                         panic("Max apic_id exceeded!\n");
2840
2841                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2842                         "trying %d\n", ioapic, apic_id, i);
2843
2844                 apic_id = i;
2845         }
2846
2847         tmp = apicid_to_cpu_present(apic_id);
2848         physids_or(apic_id_map, apic_id_map, tmp);
2849
2850         if (reg_00.bits.ID != apic_id) {
2851                 reg_00.bits.ID = apic_id;
2852
2853                 spin_lock_irqsave(&ioapic_lock, flags);
2854                 io_apic_write(ioapic, 0, reg_00.raw);
2855                 reg_00.raw = io_apic_read(ioapic, 0);
2856                 spin_unlock_irqrestore(&ioapic_lock, flags);
2857
2858                 /* Sanity check */
2859                 if (reg_00.bits.ID != apic_id) {
2860                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2861                         return -1;
2862                 }
2863         }
2864
2865         apic_printk(APIC_VERBOSE, KERN_INFO
2866                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2867 #endif /* !CONFIG_XEN */
2868
2869         return apic_id;
2870 }
2871
2872
2873 int __init io_apic_get_version (int ioapic)
2874 {
2875         union IO_APIC_reg_01    reg_01;
2876         unsigned long flags;
2877
2878         spin_lock_irqsave(&ioapic_lock, flags);
2879         reg_01.raw = io_apic_read(ioapic, 1);
2880         spin_unlock_irqrestore(&ioapic_lock, flags);
2881
2882         return reg_01.bits.version;
2883 }
2884
2885
2886 int __init io_apic_get_redir_entries (int ioapic)
2887 {
2888         union IO_APIC_reg_01    reg_01;
2889         unsigned long flags;
2890
2891         spin_lock_irqsave(&ioapic_lock, flags);
2892         reg_01.raw = io_apic_read(ioapic, 1);
2893         spin_unlock_irqrestore(&ioapic_lock, flags);
2894
2895         return reg_01.bits.entries;
2896 }
2897
2898
2899 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2900 {
2901         struct IO_APIC_route_entry entry;
2902         unsigned long flags;
2903
2904         if (!IO_APIC_IRQ(irq)) {
2905                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2906                         ioapic);
2907                 return -EINVAL;
2908         }
2909
2910         /*
2911          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2912          * Note that we mask (disable) IRQs now -- these get enabled when the
2913          * corresponding device driver registers for this IRQ.
2914          */
2915
2916         memset(&entry,0,sizeof(entry));
2917
2918         entry.delivery_mode = INT_DELIVERY_MODE;
2919         entry.dest_mode = INT_DEST_MODE;
2920         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2921         entry.trigger = edge_level;
2922         entry.polarity = active_high_low;
2923         entry.mask  = 1;
2924
2925         /*
2926          * IRQs < 16 are already in the irq_2_pin[] map
2927          */
2928         if (irq >= 16)
2929                 add_pin_to_irq(irq, ioapic, pin);
2930
2931         entry.vector = assign_irq_vector(irq);
2932
2933         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2934                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2935                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2936                 edge_level, active_high_low);
2937
2938         ioapic_register_intr(irq, entry.vector, edge_level);
2939
2940         if (!ioapic && (irq < 16))
2941                 disable_8259A_irq(irq);
2942
2943         spin_lock_irqsave(&ioapic_lock, flags);
2944         __ioapic_write_entry(ioapic, pin, entry);
2945         set_native_irq_info(irq, TARGET_CPUS);
2946         spin_unlock_irqrestore(&ioapic_lock, flags);
2947
2948         return 0;
2949 }
2950
2951 #endif /* CONFIG_ACPI */
2952
2953 static int __init parse_disable_timer_pin_1(char *arg)
2954 {
2955         disable_timer_pin_1 = 1;
2956         return 0;
2957 }
2958 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2959
2960 static int __init parse_enable_timer_pin_1(char *arg)
2961 {
2962         disable_timer_pin_1 = -1;
2963         return 0;
2964 }
2965 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2966
2967 static int __init parse_noapic(char *arg)
2968 {
2969         /* disable IO-APIC */
2970         disable_ioapic_setup();
2971         return 0;
2972 }
2973 early_param("noapic", parse_noapic);