arch/i386/kernel/io_apic-xen.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/timer.h>
  39 #include <asm/i8259.h>
  40 #include <asm/nmi.h>
  41
  42 #include <mach_apic.h>
  43
  44 #include "io_ports.h"
  45
  46 #ifdef CONFIG_XEN
  47
  48 #include <xen/interface/xen.h>
  49 #include <xen/interface/physdev.h>
  50
  51 /* Fake i8259 */
  52 #define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
  53 #define disable_8259A_irq(_irq)  ((void)0)
  54 #define i8259A_irq_pending(_irq) (0)
  55
  56 unsigned long io_apic_irqs;
  57
  58 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
  59 {
  60         struct physdev_apic apic_op;
  61         int ret;
  62
  63         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
  64         apic_op.reg = reg;
  65         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
  66         if (ret)
  67                 return ret;
  68         return apic_op.value;
  69 }
  70
  71 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
  72 {
  73         struct physdev_apic apic_op;
  74
  75         apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
  76         apic_op.reg = reg;
  77         apic_op.value = value;
  78         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
  79 }
  80
  81 #define io_apic_read(a,r)    xen_io_apic_read(a,r)
  82 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
  83
  84 #endif /* CONFIG_XEN */
  85
  86 int (*ioapic_renumber_irq)(int ioapic, int irq);
  87 atomic_t irq_mis_count;
  88
  89 /* Where if anywhere is the i8259 connect in external int mode */
  90 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  91
  92 static DEFINE_SPINLOCK(ioapic_lock);
  93 static DEFINE_SPINLOCK(vector_lock);
  94
  95 int timer_over_8254 __initdata = 1;
  96
  97 /*
  98  *      Is the SiS APIC rmw bug present ?
  99  *      -1 = don't know, 0 = no, 1 = yes
 100  */
 101 int sis_apic_bug = -1;
 102
 103 /*
 104  * # of IRQ routing registers
 105  */
 106 int nr_ioapic_registers[MAX_IO_APICS];
 107
 108 int disable_timer_pin_1 __initdata;
 109
 110 /*
 111  * Rough estimation of how many shared IRQs there are, can
 112  * be changed anytime.
 113  */
 114 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 115 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 116
 117 /*
 118  * This is performance-critical, we want to do it O(1)
 119  *
 120  * the indexing order of this array favors 1:1 mappings
 121  * between pins and IRQs.
 122  */
 123
 124 static struct irq_pin_list {
 125         int apic, pin, next;
 126 } irq_2_pin[PIN_MAP_SIZE];
 127
 128 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
 129 #ifdef CONFIG_PCI_MSI
 130 #define vector_to_irq(vector)   \
 131         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
 132 #else
 133 #define vector_to_irq(vector)   (vector)
 134 #endif
 135
 136 /*
 137  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 138  * shared ISA-space IRQs, so we have to support them. We are super
 139  * fast in the common case, and fast for shared ISA-space IRQs.
 140  */
 141 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 142 {
 143         static int first_free_entry = NR_IRQS;
 144         struct irq_pin_list *entry = irq_2_pin + irq;
 145
 146         while (entry->next)
 147                 entry = irq_2_pin + entry->next;
 148
 149         if (entry->pin != -1) {
 150                 entry->next = first_free_entry;
 151                 entry = irq_2_pin + entry->next;
 152                 if (++first_free_entry >= PIN_MAP_SIZE)
 153                         panic("io_apic.c: whoops");
 154         }
 155         entry->apic = apic;
 156         entry->pin = pin;
 157 }
 158
 159 #ifdef CONFIG_XEN
 160 #define clear_IO_APIC() ((void)0)
 161 #else
 162 /*
 163  * Reroute an IRQ to a different pin.
 164  */
 165 static void __init replace_pin_at_irq(unsigned int irq,
 166                                       int oldapic, int oldpin,
 167                                       int newapic, int newpin)
 168 {
 169         struct irq_pin_list *entry = irq_2_pin + irq;
 170
 171         while (1) {
 172                 if (entry->apic == oldapic && entry->pin == oldpin) {
 173                         entry->apic = newapic;
 174                         entry->pin = newpin;
 175                 }
 176                 if (!entry->next)
 177                         break;
 178                 entry = irq_2_pin + entry->next;
 179         }
 180 }
 181
 182 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 183 {
 184         struct irq_pin_list *entry = irq_2_pin + irq;
 185         unsigned int pin, reg;
 186
 187         for (;;) {
 188                 pin = entry->pin;
 189                 if (pin == -1)
 190                         break;
 191                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 192                 reg &= ~disable;
 193                 reg |= enable;
 194                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 195                 if (!entry->next)
 196                         break;
 197                 entry = irq_2_pin + entry->next;
 198         }
 199 }
 200
 201 /* mask = 1 */
 202 static void __mask_IO_APIC_irq (unsigned int irq)
 203 {
 204         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 205 }
 206
 207 /* mask = 0 */
 208 static void __unmask_IO_APIC_irq (unsigned int irq)
 209 {
 210         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 211 }
 212
 213 /* mask = 1, trigger = 0 */
 214 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 215 {
 216         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 217 }
 218
 219 /* mask = 0, trigger = 1 */
 220 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 221 {
 222         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 223 }
 224
 225 static void mask_IO_APIC_irq (unsigned int irq)
 226 {
 227         unsigned long flags;
 228
 229         spin_lock_irqsave(&ioapic_lock, flags);
 230         __mask_IO_APIC_irq(irq);
 231         spin_unlock_irqrestore(&ioapic_lock, flags);
 232 }
 233
 234 static void unmask_IO_APIC_irq (unsigned int irq)
 235 {
 236         unsigned long flags;
 237
 238         spin_lock_irqsave(&ioapic_lock, flags);
 239         __unmask_IO_APIC_irq(irq);
 240         spin_unlock_irqrestore(&ioapic_lock, flags);
 241 }
 242
 243 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 244 {
 245         struct IO_APIC_route_entry entry;
 246         unsigned long flags;
 247
 248         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 249         spin_lock_irqsave(&ioapic_lock, flags);
 250         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 251         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 252         spin_unlock_irqrestore(&ioapic_lock, flags);
 253         if (entry.delivery_mode == dest_SMI)
 254                 return;
 255
 256         /*
 257          * Disable it in the IO-APIC irq-routing table:
 258          */
 259         memset(&entry, 0, sizeof(entry));
 260         entry.mask = 1;
 261         spin_lock_irqsave(&ioapic_lock, flags);
 262         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 263         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 264         spin_unlock_irqrestore(&ioapic_lock, flags);
 265 }
 266
 267 static void clear_IO_APIC (void)
 268 {
 269         int apic, pin;
 270
 271         for (apic = 0; apic < nr_ioapics; apic++)
 272                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 273                         clear_IO_APIC_pin(apic, pin);
 274 }
 275
 276 #ifdef CONFIG_SMP
 277 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 278 {
 279         unsigned long flags;
 280         int pin;
 281         struct irq_pin_list *entry = irq_2_pin + irq;
 282         unsigned int apicid_value;
 283         cpumask_t tmp;
 284
 285         cpus_and(tmp, cpumask, cpu_online_map);
 286         if (cpus_empty(tmp))
 287                 tmp = TARGET_CPUS;
 288
 289         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 290
 291         apicid_value = cpu_mask_to_apicid(cpumask);
 292         /* Prepare to do the io_apic_write */
 293         apicid_value = apicid_value << 24;
 294         spin_lock_irqsave(&ioapic_lock, flags);
 295         for (;;) {
 296                 pin = entry->pin;
 297                 if (pin == -1)
 298                         break;
 299                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 300                 if (!entry->next)
 301                         break;
 302                 entry = irq_2_pin + entry->next;
 303         }
 304         set_irq_info(irq, cpumask);
 305         spin_unlock_irqrestore(&ioapic_lock, flags);
 306 }
 307
 308 #if defined(CONFIG_IRQBALANCE)
 309 # include <asm/processor.h>     /* kernel_thread() */
 310 # include <linux/kernel_stat.h> /* kstat */
 311 # include <linux/slab.h>                /* kmalloc() */
 312 # include <linux/timer.h>       /* time_after() */
 313
 314 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 315 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 316 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 317 # else
 318 #  define TDprintk(x...)
 319 #  define Dprintk(x...)
 320 # endif
 321
 322 #define IRQBALANCE_CHECK_ARCH -999
 323 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 324 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 325 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 326 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 327
 328 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 329 static int physical_balance __read_mostly;
 330 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 331
 332 static struct irq_cpu_info {
 333         unsigned long * last_irq;
 334         unsigned long * irq_delta;
 335         unsigned long irq;
 336 } irq_cpu_data[NR_CPUS];
 337
 338 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 339 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 340 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 341
 342 #define IDLE_ENOUGH(cpu,now) \
 343         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 344
 345 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 346
 347 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 348
 349 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 350         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 351 };
 352
 353 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 354 {
 355         balance_irq_affinity[irq] = mask;
 356 }
 357
 358 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 359                         unsigned long now, int direction)
 360 {
 361         int search_idle = 1;
 362         int cpu = curr_cpu;
 363
 364         goto inside;
 365
 366         do {
 367                 if (unlikely(cpu == curr_cpu))
 368                         search_idle = 0;
 369 inside:
 370                 if (direction == 1) {
 371                         cpu++;
 372                         if (cpu >= NR_CPUS)
 373                                 cpu = 0;
 374                 } else {
 375                         cpu--;
 376                         if (cpu == -1)
 377                                 cpu = NR_CPUS-1;
 378                 }
 379         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 380                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 381
 382         return cpu;
 383 }
 384
 385 static inline void balance_irq(int cpu, int irq)
 386 {
 387         unsigned long now = jiffies;
 388         cpumask_t allowed_mask;
 389         unsigned int new_cpu;
 390
 391         if (irqbalance_disabled)
 392                 return;
 393
 394         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 395         new_cpu = move(cpu, allowed_mask, now, 1);
 396         if (cpu != new_cpu) {
 397                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 398         }
 399 }
 400
 401 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 402 {
 403         int i, j;
 404         Dprintk("Rotating IRQs among CPUs.\n");
 405         for_each_online_cpu(i) {
 406                 for (j = 0; j < NR_IRQS; j++) {
 407                         if (!irq_desc[j].action)
 408                                 continue;
 409                         /* Is it a significant load ?  */
 410                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 411                                                 useful_load_threshold)
 412                                 continue;
 413                         balance_irq(i, j);
 414                 }
 415         }
 416         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 417                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 418         return;
 419 }
 420
 421 static void do_irq_balance(void)
 422 {
 423         int i, j;
 424         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 425         unsigned long move_this_load = 0;
 426         int max_loaded = 0, min_loaded = 0;
 427         int load;
 428         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 429         int selected_irq;
 430         int tmp_loaded, first_attempt = 1;
 431         unsigned long tmp_cpu_irq;
 432         unsigned long imbalance = 0;
 433         cpumask_t allowed_mask, target_cpu_mask, tmp;
 434
 435         for_each_possible_cpu(i) {
 436                 int package_index;
 437                 CPU_IRQ(i) = 0;
 438                 if (!cpu_online(i))
 439                         continue;
 440                 package_index = CPU_TO_PACKAGEINDEX(i);
 441                 for (j = 0; j < NR_IRQS; j++) {
 442                         unsigned long value_now, delta;
 443                         /* Is this an active IRQ? */
 444                         if (!irq_desc[j].action)
 445                                 continue;
 446                         if ( package_index == i )
 447                                 IRQ_DELTA(package_index,j) = 0;
 448                         /* Determine the total count per processor per IRQ */
 449                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 450
 451                         /* Determine the activity per processor per IRQ */
 452                         delta = value_now - LAST_CPU_IRQ(i,j);
 453
 454                         /* Update last_cpu_irq[][] for the next time */
 455                         LAST_CPU_IRQ(i,j) = value_now;
 456
 457                         /* Ignore IRQs whose rate is less than the clock */
 458                         if (delta < useful_load_threshold)
 459                                 continue;
 460                         /* update the load for the processor or package total */
 461                         IRQ_DELTA(package_index,j) += delta;
 462
 463                         /* Keep track of the higher numbered sibling as well */
 464                         if (i != package_index)
 465                                 CPU_IRQ(i) += delta;
 466                         /*
 467                          * We have sibling A and sibling B in the package
 468                          *
 469                          * cpu_irq[A] = load for cpu A + load for cpu B
 470                          * cpu_irq[B] = load for cpu B
 471                          */
 472                         CPU_IRQ(package_index) += delta;
 473                 }
 474         }
 475         /* Find the least loaded processor package */
 476         for_each_online_cpu(i) {
 477                 if (i != CPU_TO_PACKAGEINDEX(i))
 478                         continue;
 479                 if (min_cpu_irq > CPU_IRQ(i)) {
 480                         min_cpu_irq = CPU_IRQ(i);
 481                         min_loaded = i;
 482                 }
 483         }
 484         max_cpu_irq = ULONG_MAX;
 485
 486 tryanothercpu:
 487         /* Look for heaviest loaded processor.
 488          * We may come back to get the next heaviest loaded processor.
 489          * Skip processors with trivial loads.
 490          */
 491         tmp_cpu_irq = 0;
 492         tmp_loaded = -1;
 493         for_each_online_cpu(i) {
 494                 if (i != CPU_TO_PACKAGEINDEX(i))
 495                         continue;
 496                 if (max_cpu_irq <= CPU_IRQ(i))
 497                         continue;
 498                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 499                         tmp_cpu_irq = CPU_IRQ(i);
 500                         tmp_loaded = i;
 501                 }
 502         }
 503
 504         if (tmp_loaded == -1) {
 505          /* In the case of small number of heavy interrupt sources,
 506           * loading some of the cpus too much. We use Ingo's original
 507           * approach to rotate them around.
 508           */
 509                 if (!first_attempt && imbalance >= useful_load_threshold) {
 510                         rotate_irqs_among_cpus(useful_load_threshold);
 511                         return;
 512                 }
 513                 goto not_worth_the_effort;
 514         }
 515
 516         first_attempt = 0;              /* heaviest search */
 517         max_cpu_irq = tmp_cpu_irq;      /* load */
 518         max_loaded = tmp_loaded;        /* processor */
 519         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 520
 521         Dprintk("max_loaded cpu = %d\n", max_loaded);
 522         Dprintk("min_loaded cpu = %d\n", min_loaded);
 523         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 524         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 525         Dprintk("load imbalance = %lu\n", imbalance);
 526
 527         /* if imbalance is less than approx 10% of max load, then
 528          * observe diminishing returns action. - quit
 529          */
 530         if (imbalance < (max_cpu_irq >> 3)) {
 531                 Dprintk("Imbalance too trivial\n");
 532                 goto not_worth_the_effort;
 533         }
 534
 535 tryanotherirq:
 536         /* if we select an IRQ to move that can't go where we want, then
 537          * see if there is another one to try.
 538          */
 539         move_this_load = 0;
 540         selected_irq = -1;
 541         for (j = 0; j < NR_IRQS; j++) {
 542                 /* Is this an active IRQ? */
 543                 if (!irq_desc[j].action)
 544                         continue;
 545                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 546                         continue;
 547                 /* Try to find the IRQ that is closest to the imbalance
 548                  * without going over.
 549                  */
 550                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 551                         move_this_load = IRQ_DELTA(max_loaded,j);
 552                         selected_irq = j;
 553                 }
 554         }
 555         if (selected_irq == -1) {
 556                 goto tryanothercpu;
 557         }
 558
 559         imbalance = move_this_load;
 560
 561         /* For physical_balance case, we accumlated both load
 562          * values in the one of the siblings cpu_irq[],
 563          * to use the same code for physical and logical processors
 564          * as much as possible.
 565          *
 566          * NOTE: the cpu_irq[] array holds the sum of the load for
 567          * sibling A and sibling B in the slot for the lowest numbered
 568          * sibling (A), _AND_ the load for sibling B in the slot for
 569          * the higher numbered sibling.
 570          *
 571          * We seek the least loaded sibling by making the comparison
 572          * (A+B)/2 vs B
 573          */
 574         load = CPU_IRQ(min_loaded) >> 1;
 575         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 576                 if (load > CPU_IRQ(j)) {
 577                         /* This won't change cpu_sibling_map[min_loaded] */
 578                         load = CPU_IRQ(j);
 579                         min_loaded = j;
 580                 }
 581         }
 582
 583         cpus_and(allowed_mask,
 584                  cpu_online_map,
 585                  balance_irq_affinity[selected_irq]);
 586         target_cpu_mask = cpumask_of_cpu(min_loaded);
 587         cpus_and(tmp, target_cpu_mask, allowed_mask);
 588
 589         if (!cpus_empty(tmp)) {
 590
 591                 Dprintk("irq = %d moved to cpu = %d\n",
 592                                 selected_irq, min_loaded);
 593                 /* mark for change destination */
 594                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 595
 596                 /* Since we made a change, come back sooner to
 597                  * check for more variation.
 598                  */
 599                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 600                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 601                 return;
 602         }
 603         goto tryanotherirq;
 604
 605 not_worth_the_effort:
 606         /*
 607          * if we did not find an IRQ to move, then adjust the time interval
 608          * upward
 609          */
 610         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 611                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 612         Dprintk("IRQ worth rotating not found\n");
 613         return;
 614 }
 615
 616 static int balanced_irq(void *unused)
 617 {
 618         int i;
 619         unsigned long prev_balance_time = jiffies;
 620         long time_remaining = balanced_irq_interval;
 621
 622         daemonize("kirqd");
 623
 624         /* push everything to CPU 0 to give us a starting point.  */
 625         for (i = 0 ; i < NR_IRQS ; i++) {
 626                 irq_desc[i].pending_mask[i] = cpumask_of_cpu(0);
 627                 set_pending_irq(i, cpumask_of_cpu(0));
 628         }
 629
 630         for ( ; ; ) {
 631                 time_remaining = schedule_timeout_interruptible(time_remaining);
 632                 try_to_freeze();
 633                 if (time_after(jiffies,
 634                                 prev_balance_time+balanced_irq_interval)) {
 635                         preempt_disable();
 636                         do_irq_balance();
 637                         prev_balance_time = jiffies;
 638                         time_remaining = balanced_irq_interval;
 639                         preempt_enable();
 640                 }
 641         }
 642         return 0;
 643 }
 644
 645 static int __init balanced_irq_init(void)
 646 {
 647         int i;
 648         struct cpuinfo_x86 *c;
 649         cpumask_t tmp;
 650
 651         cpus_shift_right(tmp, cpu_online_map, 2);
 652         c = &boot_cpu_data;
 653         /* When not overwritten by the command line ask subarchitecture. */
 654         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 655                 irqbalance_disabled = NO_BALANCE_IRQ;
 656         if (irqbalance_disabled)
 657                 return 0;
 658
 659          /* disable irqbalance completely if there is only one processor online */
 660         if (num_online_cpus() < 2) {
 661                 irqbalance_disabled = 1;
 662                 return 0;
 663         }
 664         /*
 665          * Enable physical balance only if more than 1 physical processor
 666          * is present
 667          */
 668         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 669                 physical_balance = 1;
 670
 671         for_each_online_cpu(i) {
 672                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 673                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 674                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 675                         printk(KERN_ERR "balanced_irq_init: out of memory");
 676                         goto failed;
 677                 }
 678                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 679                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 680         }
 681
 682         printk(KERN_INFO "Starting balanced_irq\n");
 683         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 684                 return 0;
 685         else
 686                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 687 failed:
 688         for_each_possible_cpu(i) {
 689                 kfree(irq_cpu_data[i].irq_delta);
 690                 irq_cpu_data[i].irq_delta = NULL;
 691                 kfree(irq_cpu_data[i].last_irq);
 692                 irq_cpu_data[i].last_irq = NULL;
 693         }
 694         return 0;
 695 }
 696
 697 int __init irqbalance_disable(char *str)
 698 {
 699         irqbalance_disabled = 1;
 700         return 1;
 701 }
 702
 703 __setup("noirqbalance", irqbalance_disable);
 704
 705 late_initcall(balanced_irq_init);
 706 #endif /* CONFIG_IRQBALANCE */
 707 #endif /* CONFIG_SMP */
 708 #endif
 709
 710 #ifndef CONFIG_SMP
 711 void fastcall send_IPI_self(int vector)
 712 {
 713 #ifndef CONFIG_XEN
 714         unsigned int cfg;
 715
 716         /*
 717          * Wait for idle.
 718          */
 719         apic_wait_icr_idle();
 720         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 721         /*
 722          * Send the IPI. The write to APIC_ICR fires this off.
 723          */
 724         apic_write_around(APIC_ICR, cfg);
 725 #endif
 726 }
 727 #endif /* !CONFIG_SMP */
 728
 729
 730 /*
 731  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 732  * specific CPU-side IRQs.
 733  */
 734
 735 #define MAX_PIRQS 8
 736 static int pirq_entries [MAX_PIRQS];
 737 static int pirqs_enabled;
 738 int skip_ioapic_setup;
 739
 740 static int __init ioapic_setup(char *str)
 741 {
 742         skip_ioapic_setup = 1;
 743         return 1;
 744 }
 745
 746 __setup("noapic", ioapic_setup);
 747
 748 static int __init ioapic_pirq_setup(char *str)
 749 {
 750         int i, max;
 751         int ints[MAX_PIRQS+1];
 752
 753         get_options(str, ARRAY_SIZE(ints), ints);
 754
 755         for (i = 0; i < MAX_PIRQS; i++)
 756                 pirq_entries[i] = -1;
 757
 758         pirqs_enabled = 1;
 759         apic_printk(APIC_VERBOSE, KERN_INFO
 760                         "PIRQ redirection, working around broken MP-BIOS.\n");
 761         max = MAX_PIRQS;
 762         if (ints[0] < MAX_PIRQS)
 763                 max = ints[0];
 764
 765         for (i = 0; i < max; i++) {
 766                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 767                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 768                 /*
 769                  * PIRQs are mapped upside down, usually.
 770                  */
 771                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 772         }
 773         return 1;
 774 }
 775
 776 __setup("pirq=", ioapic_pirq_setup);
 777
 778 /*
 779  * Find the IRQ entry number of a certain pin.
 780  */
 781 static int find_irq_entry(int apic, int pin, int type)
 782 {
 783         int i;
 784
 785         for (i = 0; i < mp_irq_entries; i++)
 786                 if (mp_irqs[i].mpc_irqtype == type &&
 787                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 788                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 789                     mp_irqs[i].mpc_dstirq == pin)
 790                         return i;
 791
 792         return -1;
 793 }
 794
 795 /*
 796  * Find the pin to which IRQ[irq] (ISA) is connected
 797  */
 798 static int __init find_isa_irq_pin(int irq, int type)
 799 {
 800         int i;
 801
 802         for (i = 0; i < mp_irq_entries; i++) {
 803                 int lbus = mp_irqs[i].mpc_srcbus;
 804
 805                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 806                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 807                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 808                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 809                     ) &&
 810                     (mp_irqs[i].mpc_irqtype == type) &&
 811                     (mp_irqs[i].mpc_srcbusirq == irq))
 812
 813                         return mp_irqs[i].mpc_dstirq;
 814         }
 815         return -1;
 816 }
 817
 818 static int __init find_isa_irq_apic(int irq, int type)
 819 {
 820         int i;
 821
 822         for (i = 0; i < mp_irq_entries; i++) {
 823                 int lbus = mp_irqs[i].mpc_srcbus;
 824
 825                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 826                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 827                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 828                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 829                     ) &&
 830                     (mp_irqs[i].mpc_irqtype == type) &&
 831                     (mp_irqs[i].mpc_srcbusirq == irq))
 832                         break;
 833         }
 834         if (i < mp_irq_entries) {
 835                 int apic;
 836                 for(apic = 0; apic < nr_ioapics; apic++) {
 837                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 838                                 return apic;
 839                 }
 840         }
 841
 842         return -1;
 843 }
 844
 845 /*
 846  * Find a specific PCI IRQ entry.
 847  * Not an __init, possibly needed by modules
 848  */
 849 static int pin_2_irq(int idx, int apic, int pin);
 850
 851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 852 {
 853         int apic, i, best_guess = -1;
 854
 855         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 856                 "slot:%d, pin:%d.\n", bus, slot, pin);
 857         if (mp_bus_id_to_pci_bus[bus] == -1) {
 858                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 859                 return -1;
 860         }
 861         for (i = 0; i < mp_irq_entries; i++) {
 862                 int lbus = mp_irqs[i].mpc_srcbus;
 863
 864                 for (apic = 0; apic < nr_ioapics; apic++)
 865                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 866                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 867                                 break;
 868
 869                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 870                     !mp_irqs[i].mpc_irqtype &&
 871                     (bus == lbus) &&
 872                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 873                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 874
 875                         if (!(apic || IO_APIC_IRQ(irq)))
 876                                 continue;
 877
 878                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 879                                 return irq;
 880                         /*
 881                          * Use the first all-but-pin matching entry as a
 882                          * best-guess fuzzy result for broken mptables.
 883                          */
 884                         if (best_guess < 0)
 885                                 best_guess = irq;
 886                 }
 887         }
 888         return best_guess;
 889 }
 890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 891
 892 /*
 893  * This function currently is only a helper for the i386 smp boot process where
 894  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 895  * so mask in all cases should simply be TARGET_CPUS
 896  */
 897 #ifdef CONFIG_SMP
 898 #ifndef CONFIG_XEN
 899 void __init setup_ioapic_dest(void)
 900 {
 901         int pin, ioapic, irq, irq_entry;
 902
 903         if (skip_ioapic_setup == 1)
 904                 return;
 905
 906         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 907                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 908                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 909                         if (irq_entry == -1)
 910                                 continue;
 911                         irq = pin_2_irq(irq_entry, ioapic, pin);
 912                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 913                 }
 914
 915         }
 916 }
 917 #endif /* !CONFIG_XEN */
 918 #endif
 919
 920 /*
 921  * EISA Edge/Level control register, ELCR
 922  */
 923 static int EISA_ELCR(unsigned int irq)
 924 {
 925         if (irq < 16) {
 926                 unsigned int port = 0x4d0 + (irq >> 3);
 927                 return (inb(port) >> (irq & 7)) & 1;
 928         }
 929         apic_printk(APIC_VERBOSE, KERN_INFO
 930                         "Broken MPtable reports ISA irq %d\n", irq);
 931         return 0;
 932 }
 933
 934 /* EISA interrupts are always polarity zero and can be edge or level
 935  * trigger depending on the ELCR value.  If an interrupt is listed as
 936  * EISA conforming in the MP table, that means its trigger type must
 937  * be read in from the ELCR */
 938
 939 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 940 #define default_EISA_polarity(idx)      (0)
 941
 942 /* ISA interrupts are always polarity zero edge triggered,
 943  * when listed as conforming in the MP table. */
 944
 945 #define default_ISA_trigger(idx)        (0)
 946 #define default_ISA_polarity(idx)       (0)
 947
 948 /* PCI interrupts are always polarity one level triggered,
 949  * when listed as conforming in the MP table. */
 950
 951 #define default_PCI_trigger(idx)        (1)
 952 #define default_PCI_polarity(idx)       (1)
 953
 954 /* MCA interrupts are always polarity zero level triggered,
 955  * when listed as conforming in the MP table. */
 956
 957 #define default_MCA_trigger(idx)        (1)
 958 #define default_MCA_polarity(idx)       (0)
 959
 960 /* NEC98 interrupts are always polarity zero edge triggered,
 961  * when listed as conforming in the MP table. */
 962
 963 #define default_NEC98_trigger(idx)     (0)
 964 #define default_NEC98_polarity(idx)    (0)
 965
 966 static int __init MPBIOS_polarity(int idx)
 967 {
 968         int bus = mp_irqs[idx].mpc_srcbus;
 969         int polarity;
 970
 971         /*
 972          * Determine IRQ line polarity (high active or low active):
 973          */
 974         switch (mp_irqs[idx].mpc_irqflag & 3)
 975         {
 976                 case 0: /* conforms, ie. bus-type dependent polarity */
 977                 {
 978                         switch (mp_bus_id_to_type[bus])
 979                         {
 980                                 case MP_BUS_ISA: /* ISA pin */
 981                                 {
 982                                         polarity = default_ISA_polarity(idx);
 983                                         break;
 984                                 }
 985                                 case MP_BUS_EISA: /* EISA pin */
 986                                 {
 987                                         polarity = default_EISA_polarity(idx);
 988                                         break;
 989                                 }
 990                                 case MP_BUS_PCI: /* PCI pin */
 991                                 {
 992                                         polarity = default_PCI_polarity(idx);
 993                                         break;
 994                                 }
 995                                 case MP_BUS_MCA: /* MCA pin */
 996                                 {
 997                                         polarity = default_MCA_polarity(idx);
 998                                         break;
 999                                 }
1000                                 case MP_BUS_NEC98: /* NEC 98 pin */
1001                                 {
1002                                         polarity = default_NEC98_polarity(idx);
1003                                         break;
1004                                 }
1005                                 default:
1006                                 {
1007                                         printk(KERN_WARNING "broken BIOS!!\n");
1008                                         polarity = 1;
1009                                         break;
1010                                 }
1011                         }
1012                         break;
1013                 }
1014                 case 1: /* high active */
1015                 {
1016                         polarity = 0;
1017                         break;
1018                 }
1019                 case 2: /* reserved */
1020                 {
1021                         printk(KERN_WARNING "broken BIOS!!\n");
1022                         polarity = 1;
1023                         break;
1024                 }
1025                 case 3: /* low active */
1026                 {
1027                         polarity = 1;
1028                         break;
1029                 }
1030                 default: /* invalid */
1031                 {
1032                         printk(KERN_WARNING "broken BIOS!!\n");
1033                         polarity = 1;
1034                         break;
1035                 }
1036         }
1037         return polarity;
1038 }
1039
1040 static int MPBIOS_trigger(int idx)
1041 {
1042         int bus = mp_irqs[idx].mpc_srcbus;
1043         int trigger;
1044
1045         /*
1046          * Determine IRQ trigger mode (edge or level sensitive):
1047          */
1048         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1049         {
1050                 case 0: /* conforms, ie. bus-type dependent */
1051                 {
1052                         switch (mp_bus_id_to_type[bus])
1053                         {
1054                                 case MP_BUS_ISA: /* ISA pin */
1055                                 {
1056                                         trigger = default_ISA_trigger(idx);
1057                                         break;
1058                                 }
1059                                 case MP_BUS_EISA: /* EISA pin */
1060                                 {
1061                                         trigger = default_EISA_trigger(idx);
1062                                         break;
1063                                 }
1064                                 case MP_BUS_PCI: /* PCI pin */
1065                                 {
1066                                         trigger = default_PCI_trigger(idx);
1067                                         break;
1068                                 }
1069                                 case MP_BUS_MCA: /* MCA pin */
1070                                 {
1071                                         trigger = default_MCA_trigger(idx);
1072                                         break;
1073                                 }
1074                                 case MP_BUS_NEC98: /* NEC 98 pin */
1075                                 {
1076                                         trigger = default_NEC98_trigger(idx);
1077                                         break;
1078                                 }
1079                                 default:
1080                                 {
1081                                         printk(KERN_WARNING "broken BIOS!!\n");
1082                                         trigger = 1;
1083                                         break;
1084                                 }
1085                         }
1086                         break;
1087                 }
1088                 case 1: /* edge */
1089                 {
1090                         trigger = 0;
1091                         break;
1092                 }
1093                 case 2: /* reserved */
1094                 {
1095                         printk(KERN_WARNING "broken BIOS!!\n");
1096                         trigger = 1;
1097                         break;
1098                 }
1099                 case 3: /* level */
1100                 {
1101                         trigger = 1;
1102                         break;
1103                 }
1104                 default: /* invalid */
1105                 {
1106                         printk(KERN_WARNING "broken BIOS!!\n");
1107                         trigger = 0;
1108                         break;
1109                 }
1110         }
1111         return trigger;
1112 }
1113
1114 static inline int irq_polarity(int idx)
1115 {
1116         return MPBIOS_polarity(idx);
1117 }
1118
1119 static inline int irq_trigger(int idx)
1120 {
1121         return MPBIOS_trigger(idx);
1122 }
1123
1124 static int pin_2_irq(int idx, int apic, int pin)
1125 {
1126         int irq, i;
1127         int bus = mp_irqs[idx].mpc_srcbus;
1128
1129         /*
1130          * Debugging check, we are in big trouble if this message pops up!
1131          */
1132         if (mp_irqs[idx].mpc_dstirq != pin)
1133                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1134
1135         switch (mp_bus_id_to_type[bus])
1136         {
1137                 case MP_BUS_ISA: /* ISA pin */
1138                 case MP_BUS_EISA:
1139                 case MP_BUS_MCA:
1140                 case MP_BUS_NEC98:
1141                 {
1142                         irq = mp_irqs[idx].mpc_srcbusirq;
1143                         break;
1144                 }
1145                 case MP_BUS_PCI: /* PCI pin */
1146                 {
1147                         /*
1148                          * PCI IRQs are mapped in order
1149                          */
1150                         i = irq = 0;
1151                         while (i < apic)
1152                                 irq += nr_ioapic_registers[i++];
1153                         irq += pin;
1154
1155                         /*
1156                          * For MPS mode, so far only needed by ES7000 platform
1157                          */
1158                         if (ioapic_renumber_irq)
1159                                 irq = ioapic_renumber_irq(apic, irq);
1160
1161                         break;
1162                 }
1163                 default:
1164                 {
1165                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1166                         irq = 0;
1167                         break;
1168                 }
1169         }
1170
1171         /*
1172          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1173          */
1174         if ((pin >= 16) && (pin <= 23)) {
1175                 if (pirq_entries[pin-16] != -1) {
1176                         if (!pirq_entries[pin-16]) {
1177                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1178                                                 "disabling PIRQ%d\n", pin-16);
1179                         } else {
1180                                 irq = pirq_entries[pin-16];
1181                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1182                                                 "using PIRQ%d -> IRQ %d\n",
1183                                                 pin-16, irq);
1184                         }
1185                 }
1186         }
1187         return irq;
1188 }
1189
1190 static inline int IO_APIC_irq_trigger(int irq)
1191 {
1192         int apic, idx, pin;
1193
1194         for (apic = 0; apic < nr_ioapics; apic++) {
1195                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1196                         idx = find_irq_entry(apic,pin,mp_INT);
1197                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1198                                 return irq_trigger(idx);
1199                 }
1200         }
1201         /*
1202          * nonexistent IRQs are edge default
1203          */
1204         return 0;
1205 }
1206
1207 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1208 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1209
1210 int assign_irq_vector(int irq)
1211 {
1212         struct physdev_irq irq_op;
1213         unsigned long flags;
1214
1215         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1216
1217         spin_lock_irqsave(&vector_lock, flags);
1218
1219         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1220                 spin_unlock_irqrestore(&vector_lock, flags);
1221                 return IO_APIC_VECTOR(irq);
1222         }
1223         irq_op.irq = irq;
1224         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
1225                 return -ENOSPC;
1226
1227         vector_irq[irq_op.vector] = irq;
1228         if (irq != AUTO_ASSIGN)
1229                 IO_APIC_VECTOR(irq) = irq_op.vector;
1230
1231         spin_unlock_irqrestore(&vector_lock, flags);
1232
1233         return irq_op.vector;
1234 }
1235
1236 #ifndef CONFIG_XEN
1237 static struct hw_interrupt_type ioapic_level_type;
1238 static struct hw_interrupt_type ioapic_edge_type;
1239
1240 #define IOAPIC_AUTO     -1
1241 #define IOAPIC_EDGE     0
1242 #define IOAPIC_LEVEL    1
1243
1244 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1245 {
1246         unsigned idx;
1247
1248         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1249
1250         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1251                         trigger == IOAPIC_LEVEL)
1252                 irq_desc[idx].chip = &ioapic_level_type;
1253         else
1254                 irq_desc[idx].chip = &ioapic_edge_type;
1255         set_intr_gate(vector, interrupt[idx]);
1256 }
1257 #else
1258 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
1259 #endif
1260
1261 static void __init setup_IO_APIC_irqs(void)
1262 {
1263         struct IO_APIC_route_entry entry;
1264         int apic, pin, idx, irq, first_notcon = 1, vector;
1265         unsigned long flags;
1266
1267         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1268
1269         for (apic = 0; apic < nr_ioapics; apic++) {
1270         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1271
1272                 /*
1273                  * add it to the IO-APIC irq-routing table:
1274                  */
1275                 memset(&entry,0,sizeof(entry));
1276
1277                 entry.delivery_mode = INT_DELIVERY_MODE;
1278                 entry.dest_mode = INT_DEST_MODE;
1279                 entry.mask = 0;                         /* enable IRQ */
1280                 entry.dest.logical.logical_dest =
1281                                         cpu_mask_to_apicid(TARGET_CPUS);
1282
1283                 idx = find_irq_entry(apic,pin,mp_INT);
1284                 if (idx == -1) {
1285                         if (first_notcon) {
1286                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1287                                                 " IO-APIC (apicid-pin) %d-%d",
1288                                                 mp_ioapics[apic].mpc_apicid,
1289                                                 pin);
1290                                 first_notcon = 0;
1291                         } else
1292                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1293                                         mp_ioapics[apic].mpc_apicid, pin);
1294                         continue;
1295                 }
1296
1297                 entry.trigger = irq_trigger(idx);
1298                 entry.polarity = irq_polarity(idx);
1299
1300                 if (irq_trigger(idx)) {
1301                         entry.trigger = 1;
1302                         entry.mask = 1;
1303                 }
1304
1305                 irq = pin_2_irq(idx, apic, pin);
1306                 /*
1307                  * skip adding the timer int on secondary nodes, which causes
1308                  * a small but painful rift in the time-space continuum
1309                  */
1310                 if (multi_timer_check(apic, irq))
1311                         continue;
1312                 else
1313                         add_pin_to_irq(irq, apic, pin);
1314
1315                 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1316                         continue;
1317
1318                 if (IO_APIC_IRQ(irq)) {
1319                         vector = assign_irq_vector(irq);
1320                         entry.vector = vector;
1321                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1322
1323                         if (!apic && (irq < 16))
1324                                 disable_8259A_irq(irq);
1325                 }
1326                 spin_lock_irqsave(&ioapic_lock, flags);
1327                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1328                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1329                 set_native_irq_info(irq, TARGET_CPUS);
1330                 spin_unlock_irqrestore(&ioapic_lock, flags);
1331         }
1332         }
1333
1334         if (!first_notcon)
1335                 apic_printk(APIC_VERBOSE, " not connected.\n");
1336 }
1337
1338 /*
1339  * Set up the 8259A-master output pin:
1340  */
1341 #ifndef CONFIG_XEN
1342 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1343 {
1344         struct IO_APIC_route_entry entry;
1345         unsigned long flags;
1346
1347         memset(&entry,0,sizeof(entry));
1348
1349         disable_8259A_irq(0);
1350
1351         /* mask LVT0 */
1352         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1353
1354         /*
1355          * We use logical delivery to get the timer IRQ
1356          * to the first CPU.
1357          */
1358         entry.dest_mode = INT_DEST_MODE;
1359         entry.mask = 0;                                 /* unmask IRQ now */
1360         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1361         entry.delivery_mode = INT_DELIVERY_MODE;
1362         entry.polarity = 0;
1363         entry.trigger = 0;
1364         entry.vector = vector;
1365
1366         /*
1367          * The timer IRQ doesn't have to know that behind the
1368          * scene we have a 8259A-master in AEOI mode ...
1369          */
1370         irq_desc[0].chip = &ioapic_edge_type;
1371
1372         /*
1373          * Add it to the IO-APIC irq-routing table:
1374          */
1375         spin_lock_irqsave(&ioapic_lock, flags);
1376         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1377         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1378         spin_unlock_irqrestore(&ioapic_lock, flags);
1379
1380         enable_8259A_irq(0);
1381 }
1382
1383 static inline void UNEXPECTED_IO_APIC(void)
1384 {
1385 }
1386
1387 void __init print_IO_APIC(void)
1388 {
1389         int apic, i;
1390         union IO_APIC_reg_00 reg_00;
1391         union IO_APIC_reg_01 reg_01;
1392         union IO_APIC_reg_02 reg_02;
1393         union IO_APIC_reg_03 reg_03;
1394         unsigned long flags;
1395
1396         if (apic_verbosity == APIC_QUIET)
1397                 return;
1398
1399         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1400         for (i = 0; i < nr_ioapics; i++)
1401                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1402                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1403
1404         /*
1405          * We are a bit conservative about what we expect.  We have to
1406          * know about every hardware change ASAP.
1407          */
1408         printk(KERN_INFO "testing the IO APIC.......................\n");
1409
1410         for (apic = 0; apic < nr_ioapics; apic++) {
1411
1412         spin_lock_irqsave(&ioapic_lock, flags);
1413         reg_00.raw = io_apic_read(apic, 0);
1414         reg_01.raw = io_apic_read(apic, 1);
1415         if (reg_01.bits.version >= 0x10)
1416                 reg_02.raw = io_apic_read(apic, 2);
1417         if (reg_01.bits.version >= 0x20)
1418                 reg_03.raw = io_apic_read(apic, 3);
1419         spin_unlock_irqrestore(&ioapic_lock, flags);
1420
1421         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1422         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1423         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1424         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1425         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1426         if (reg_00.bits.ID >= get_physical_broadcast())
1427                 UNEXPECTED_IO_APIC();
1428         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1429                 UNEXPECTED_IO_APIC();
1430
1431         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1432         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1433         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1434                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1435                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1436                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1437                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1438                 (reg_01.bits.entries != 0x2E) &&
1439                 (reg_01.bits.entries != 0x3F)
1440         )
1441                 UNEXPECTED_IO_APIC();
1442
1443         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1444         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1445         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1446                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1447                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1448                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1449                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1450         )
1451                 UNEXPECTED_IO_APIC();
1452         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1453                 UNEXPECTED_IO_APIC();
1454
1455         /*
1456          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1457          * but the value of reg_02 is read as the previous read register
1458          * value, so ignore it if reg_02 == reg_01.
1459          */
1460         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1461                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1462                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1463                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1464                         UNEXPECTED_IO_APIC();
1465         }
1466
1467         /*
1468          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1469          * or reg_03, but the value of reg_0[23] is read as the previous read
1470          * register value, so ignore it if reg_03 == reg_0[12].
1471          */
1472         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1473             reg_03.raw != reg_01.raw) {
1474                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1475                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1476                 if (reg_03.bits.__reserved_1)
1477                         UNEXPECTED_IO_APIC();
1478         }
1479
1480         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1481
1482         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1483                           " Stat Dest Deli Vect:   \n");
1484
1485         for (i = 0; i <= reg_01.bits.entries; i++) {
1486                 struct IO_APIC_route_entry entry;
1487
1488                 spin_lock_irqsave(&ioapic_lock, flags);
1489                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1490                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1491                 spin_unlock_irqrestore(&ioapic_lock, flags);
1492
1493                 printk(KERN_DEBUG " %02x %03X %02X  ",
1494                         i,
1495                         entry.dest.logical.logical_dest,
1496                         entry.dest.physical.physical_dest
1497                 );
1498
1499                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1500                         entry.mask,
1501                         entry.trigger,
1502                         entry.irr,
1503                         entry.polarity,
1504                         entry.delivery_status,
1505                         entry.dest_mode,
1506                         entry.delivery_mode,
1507                         entry.vector
1508                 );
1509         }
1510         }
1511         if (use_pci_vector())
1512                 printk(KERN_INFO "Using vector-based indexing\n");
1513         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1514         for (i = 0; i < NR_IRQS; i++) {
1515                 struct irq_pin_list *entry = irq_2_pin + i;
1516                 if (entry->pin < 0)
1517                         continue;
1518                 if (use_pci_vector() && !platform_legacy_irq(i))
1519                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1520                 else
1521                         printk(KERN_DEBUG "IRQ%d ", i);
1522                 for (;;) {
1523                         printk("-> %d:%d", entry->apic, entry->pin);
1524                         if (!entry->next)
1525                                 break;
1526                         entry = irq_2_pin + entry->next;
1527                 }
1528                 printk("\n");
1529         }
1530
1531         printk(KERN_INFO ".................................... done.\n");
1532
1533         return;
1534 }
1535
1536 #if 0
1537
1538 static void print_APIC_bitfield (int base)
1539 {
1540         unsigned int v;
1541         int i, j;
1542
1543         if (apic_verbosity == APIC_QUIET)
1544                 return;
1545
1546         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1547         for (i = 0; i < 8; i++) {
1548                 v = apic_read(base + i*0x10);
1549                 for (j = 0; j < 32; j++) {
1550                         if (v & (1<<j))
1551                                 printk("1");
1552                         else
1553                                 printk("0");
1554                 }
1555                 printk("\n");
1556         }
1557 }
1558
1559 void /*__init*/ print_local_APIC(void * dummy)
1560 {
1561         unsigned int v, ver, maxlvt;
1562
1563         if (apic_verbosity == APIC_QUIET)
1564                 return;
1565
1566         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1567                 smp_processor_id(), hard_smp_processor_id());
1568         v = apic_read(APIC_ID);
1569         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1570         v = apic_read(APIC_LVR);
1571         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1572         ver = GET_APIC_VERSION(v);
1573         maxlvt = get_maxlvt();
1574
1575         v = apic_read(APIC_TASKPRI);
1576         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1577
1578         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1579                 v = apic_read(APIC_ARBPRI);
1580                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1581                         v & APIC_ARBPRI_MASK);
1582                 v = apic_read(APIC_PROCPRI);
1583                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1584         }
1585
1586         v = apic_read(APIC_EOI);
1587         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1588         v = apic_read(APIC_RRR);
1589         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1590         v = apic_read(APIC_LDR);
1591         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1592         v = apic_read(APIC_DFR);
1593         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1594         v = apic_read(APIC_SPIV);
1595         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1596
1597         printk(KERN_DEBUG "... APIC ISR field:\n");
1598         print_APIC_bitfield(APIC_ISR);
1599         printk(KERN_DEBUG "... APIC TMR field:\n");
1600         print_APIC_bitfield(APIC_TMR);
1601         printk(KERN_DEBUG "... APIC IRR field:\n");
1602         print_APIC_bitfield(APIC_IRR);
1603
1604         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1605                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1606                         apic_write(APIC_ESR, 0);
1607                 v = apic_read(APIC_ESR);
1608                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1609         }
1610
1611         v = apic_read(APIC_ICR);
1612         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1613         v = apic_read(APIC_ICR2);
1614         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1615
1616         v = apic_read(APIC_LVTT);
1617         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1618
1619         if (maxlvt > 3) {                       /* PC is LVT#4. */
1620                 v = apic_read(APIC_LVTPC);
1621                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1622         }
1623         v = apic_read(APIC_LVT0);
1624         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1625         v = apic_read(APIC_LVT1);
1626         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1627
1628         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1629                 v = apic_read(APIC_LVTERR);
1630                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1631         }
1632
1633         v = apic_read(APIC_TMICT);
1634         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1635         v = apic_read(APIC_TMCCT);
1636         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1637         v = apic_read(APIC_TDCR);
1638         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1639         printk("\n");
1640 }
1641
1642 void print_all_local_APICs (void)
1643 {
1644         on_each_cpu(print_local_APIC, NULL, 1, 1);
1645 }
1646
1647 void /*__init*/ print_PIC(void)
1648 {
1649         unsigned int v;
1650         unsigned long flags;
1651
1652         if (apic_verbosity == APIC_QUIET)
1653                 return;
1654
1655         printk(KERN_DEBUG "\nprinting PIC contents\n");
1656
1657         spin_lock_irqsave(&i8259A_lock, flags);
1658
1659         v = inb(0xa1) << 8 | inb(0x21);
1660         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1661
1662         v = inb(0xa0) << 8 | inb(0x20);
1663         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1664
1665         outb(0x0b,0xa0);
1666         outb(0x0b,0x20);
1667         v = inb(0xa0) << 8 | inb(0x20);
1668         outb(0x0a,0xa0);
1669         outb(0x0a,0x20);
1670
1671         spin_unlock_irqrestore(&i8259A_lock, flags);
1672
1673         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1674
1675         v = inb(0x4d1) << 8 | inb(0x4d0);
1676         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1677 }
1678
1679 #endif  /*  0  */
1680
1681 #else
1682 void __init print_IO_APIC(void) { }
1683 #endif /* !CONFIG_XEN */
1684
1685 static void __init enable_IO_APIC(void)
1686 {
1687         union IO_APIC_reg_01 reg_01;
1688         int i8259_apic, i8259_pin;
1689         int i, apic;
1690         unsigned long flags;
1691
1692         for (i = 0; i < PIN_MAP_SIZE; i++) {
1693                 irq_2_pin[i].pin = -1;
1694                 irq_2_pin[i].next = 0;
1695         }
1696         if (!pirqs_enabled)
1697                 for (i = 0; i < MAX_PIRQS; i++)
1698                         pirq_entries[i] = -1;
1699
1700         /*
1701          * The number of IO-APIC IRQ registers (== #pins):
1702          */
1703         for (apic = 0; apic < nr_ioapics; apic++) {
1704                 spin_lock_irqsave(&ioapic_lock, flags);
1705                 reg_01.raw = io_apic_read(apic, 1);
1706                 spin_unlock_irqrestore(&ioapic_lock, flags);
1707                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1708         }
1709         for(apic = 0; apic < nr_ioapics; apic++) {
1710                 int pin;
1711                 /* See if any of the pins is in ExtINT mode */
1712                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1713                         struct IO_APIC_route_entry entry;
1714                         spin_lock_irqsave(&ioapic_lock, flags);
1715                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1716                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1717                         spin_unlock_irqrestore(&ioapic_lock, flags);
1718
1719
1720                         /* If the interrupt line is enabled and in ExtInt mode
1721                          * I have found the pin where the i8259 is connected.
1722                          */
1723                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1724                                 ioapic_i8259.apic = apic;
1725                                 ioapic_i8259.pin  = pin;
1726                                 goto found_i8259;
1727                         }
1728                 }
1729         }
1730  found_i8259:
1731         /* Look to see what if the MP table has reported the ExtINT */
1732         /* If we could not find the appropriate pin by looking at the ioapic
1733          * the i8259 probably is not connected the ioapic but give the
1734          * mptable a chance anyway.
1735          */
1736         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1737         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1738         /* Trust the MP table if nothing is setup in the hardware */
1739         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1740                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1741                 ioapic_i8259.pin  = i8259_pin;
1742                 ioapic_i8259.apic = i8259_apic;
1743         }
1744         /* Complain if the MP table and the hardware disagree */
1745         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1746                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1747         {
1748                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1749         }
1750
1751         /*
1752          * Do not trust the IO-APIC being empty at bootup
1753          */
1754         clear_IO_APIC();
1755 }
1756
1757 /*
1758  * Not an __init, needed by the reboot code
1759  */
1760 void disable_IO_APIC(void)
1761 {
1762         /*
1763          * Clear the IO-APIC before rebooting:
1764          */
1765         clear_IO_APIC();
1766
1767 #ifndef CONFIG_XEN
1768         /*
1769          * If the i8259 is routed through an IOAPIC
1770          * Put that IOAPIC in virtual wire mode
1771          * so legacy interrupts can be delivered.
1772          */
1773         if (ioapic_i8259.pin != -1) {
1774                 struct IO_APIC_route_entry entry;
1775                 unsigned long flags;
1776
1777                 memset(&entry, 0, sizeof(entry));
1778                 entry.mask            = 0; /* Enabled */
1779                 entry.trigger         = 0; /* Edge */
1780                 entry.irr             = 0;
1781                 entry.polarity        = 0; /* High */
1782                 entry.delivery_status = 0;
1783                 entry.dest_mode       = 0; /* Physical */
1784                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1785                 entry.vector          = 0;
1786                 entry.dest.physical.physical_dest =
1787                                         GET_APIC_ID(apic_read(APIC_ID));
1788
1789                 /*
1790                  * Add it to the IO-APIC irq-routing table:
1791                  */
1792                 spin_lock_irqsave(&ioapic_lock, flags);
1793                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1794                         *(((int *)&entry)+1));
1795                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1796                         *(((int *)&entry)+0));
1797                 spin_unlock_irqrestore(&ioapic_lock, flags);
1798         }
1799         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1800 #endif
1801 }
1802
1803 /*
1804  * function to set the IO-APIC physical IDs based on the
1805  * values stored in the MPC table.
1806  *
1807  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1808  */
1809
1810 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1811 static void __init setup_ioapic_ids_from_mpc(void)
1812 {
1813         union IO_APIC_reg_00 reg_00;
1814         physid_mask_t phys_id_present_map;
1815         int apic;
1816         int i;
1817         unsigned char old_id;
1818         unsigned long flags;
1819
1820         /*
1821          * Don't check I/O APIC IDs for xAPIC systems.  They have
1822          * no meaning without the serial APIC bus.
1823          */
1824         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1825                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1826                 return;
1827         /*
1828          * This is broken; anything with a real cpu count has to
1829          * circumvent this idiocy regardless.
1830          */
1831         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1832
1833         /*
1834          * Set the IOAPIC ID to the value stored in the MPC table.
1835          */
1836         for (apic = 0; apic < nr_ioapics; apic++) {
1837
1838                 /* Read the register 0 value */
1839                 spin_lock_irqsave(&ioapic_lock, flags);
1840                 reg_00.raw = io_apic_read(apic, 0);
1841                 spin_unlock_irqrestore(&ioapic_lock, flags);
1842
1843                 old_id = mp_ioapics[apic].mpc_apicid;
1844
1845                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1846                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1847                                 apic, mp_ioapics[apic].mpc_apicid);
1848                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1849                                 reg_00.bits.ID);
1850                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1851                 }
1852
1853                 /*
1854                  * Sanity check, is the ID really free? Every APIC in a
1855                  * system must have a unique ID or we get lots of nice
1856                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1857                  */
1858                 if (check_apicid_used(phys_id_present_map,
1859                                         mp_ioapics[apic].mpc_apicid)) {
1860                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1861                                 apic, mp_ioapics[apic].mpc_apicid);
1862                         for (i = 0; i < get_physical_broadcast(); i++)
1863                                 if (!physid_isset(i, phys_id_present_map))
1864                                         break;
1865                         if (i >= get_physical_broadcast())
1866                                 panic("Max APIC ID exceeded!\n");
1867                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1868                                 i);
1869                         physid_set(i, phys_id_present_map);
1870                         mp_ioapics[apic].mpc_apicid = i;
1871                 } else {
1872                         physid_mask_t tmp;
1873                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1874                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1875                                         "phys_id_present_map\n",
1876                                         mp_ioapics[apic].mpc_apicid);
1877                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1878                 }
1879
1880
1881                 /*
1882                  * We need to adjust the IRQ routing table
1883                  * if the ID changed.
1884                  */
1885                 if (old_id != mp_ioapics[apic].mpc_apicid)
1886                         for (i = 0; i < mp_irq_entries; i++)
1887                                 if (mp_irqs[i].mpc_dstapic == old_id)
1888                                         mp_irqs[i].mpc_dstapic
1889                                                 = mp_ioapics[apic].mpc_apicid;
1890
1891                 /*
1892                  * Read the right value from the MPC table and
1893                  * write it into the ID register.
1894                  */
1895                 apic_printk(APIC_VERBOSE, KERN_INFO
1896                         "...changing IO-APIC physical APIC ID to %d ...",
1897                         mp_ioapics[apic].mpc_apicid);
1898
1899                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1900                 spin_lock_irqsave(&ioapic_lock, flags);
1901                 io_apic_write(apic, 0, reg_00.raw);
1902                 spin_unlock_irqrestore(&ioapic_lock, flags);
1903
1904                 /*
1905                  * Sanity check
1906                  */
1907                 spin_lock_irqsave(&ioapic_lock, flags);
1908                 reg_00.raw = io_apic_read(apic, 0);
1909                 spin_unlock_irqrestore(&ioapic_lock, flags);
1910                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1911                         printk("could not set ID!\n");
1912                 else
1913                         apic_printk(APIC_VERBOSE, " ok.\n");
1914         }
1915 }
1916 #else
1917 static void __init setup_ioapic_ids_from_mpc(void) { }
1918 #endif
1919
1920 #ifndef CONFIG_XEN
1921 /*
1922  * There is a nasty bug in some older SMP boards, their mptable lies
1923  * about the timer IRQ. We do the following to work around the situation:
1924  *
1925  *      - timer IRQ defaults to IO-APIC IRQ
1926  *      - if this function detects that timer IRQs are defunct, then we fall
1927  *        back to ISA timer IRQs
1928  */
1929 static int __init timer_irq_works(void)
1930 {
1931         unsigned long t1 = jiffies;
1932
1933         local_irq_enable();
1934         /* Let ten ticks pass... */
1935         mdelay((10 * 1000) / HZ);
1936
1937         /*
1938          * Expect a few ticks at least, to be sure some possible
1939          * glue logic does not lock up after one or two first
1940          * ticks in a non-ExtINT mode.  Also the local APIC
1941          * might have cached one ExtINT interrupt.  Finally, at
1942          * least one tick may be lost due to delays.
1943          */
1944         if (jiffies - t1 > 4)
1945                 return 1;
1946
1947         return 0;
1948 }
1949
1950 /*
1951  * In the SMP+IOAPIC case it might happen that there are an unspecified
1952  * number of pending IRQ events unhandled. These cases are very rare,
1953  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1954  * better to do it this way as thus we do not have to be aware of
1955  * 'pending' interrupts in the IRQ path, except at this point.
1956  */
1957 /*
1958  * Edge triggered needs to resend any interrupt
1959  * that was delayed but this is now handled in the device
1960  * independent code.
1961  */
1962
1963 /*
1964  * Starting up a edge-triggered IO-APIC interrupt is
1965  * nasty - we need to make sure that we get the edge.
1966  * If it is already asserted for some reason, we need
1967  * return 1 to indicate that is was pending.
1968  *
1969  * This is not complete - we should be able to fake
1970  * an edge even if it isn't on the 8259A...
1971  */
1972 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1973 {
1974         int was_pending = 0;
1975         unsigned long flags;
1976
1977         spin_lock_irqsave(&ioapic_lock, flags);
1978         if (irq < 16) {
1979                 disable_8259A_irq(irq);
1980                 if (i8259A_irq_pending(irq))
1981                         was_pending = 1;
1982         }
1983         __unmask_IO_APIC_irq(irq);
1984         spin_unlock_irqrestore(&ioapic_lock, flags);
1985
1986         return was_pending;
1987 }
1988
1989 /*
1990  * Once we have recorded IRQ_PENDING already, we can mask the
1991  * interrupt for real. This prevents IRQ storms from unhandled
1992  * devices.
1993  */
1994 static void ack_edge_ioapic_irq(unsigned int irq)
1995 {
1996         move_irq(irq);
1997         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1998                                         == (IRQ_PENDING | IRQ_DISABLED))
1999                 mask_IO_APIC_irq(irq);
2000         ack_APIC_irq();
2001 }
2002
2003 /*
2004  * Level triggered interrupts can just be masked,
2005  * and shutting down and starting up the interrupt
2006  * is the same as enabling and disabling them -- except
2007  * with a startup need to return a "was pending" value.
2008  *
2009  * Level triggered interrupts are special because we
2010  * do not touch any IO-APIC register while handling
2011  * them. We ack the APIC in the end-IRQ handler, not
2012  * in the start-IRQ-handler. Protection against reentrance
2013  * from the same interrupt is still provided, both by the
2014  * generic IRQ layer and by the fact that an unacked local
2015  * APIC does not accept IRQs.
2016  */
2017 static unsigned int startup_level_ioapic_irq (unsigned int irq)
2018 {
2019         unmask_IO_APIC_irq(irq);
2020
2021         return 0; /* don't check for pending */
2022 }
2023
2024 static void end_level_ioapic_irq (unsigned int irq)
2025 {
2026         unsigned long v;
2027         int i;
2028
2029         move_irq(irq);
2030 /*
2031  * It appears there is an erratum which affects at least version 0x11
2032  * of I/O APIC (that's the 82093AA and cores integrated into various
2033  * chipsets).  Under certain conditions a level-triggered interrupt is
2034  * erroneously delivered as edge-triggered one but the respective IRR
2035  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2036  * message but it will never arrive and further interrupts are blocked
2037  * from the source.  The exact reason is so far unknown, but the
2038  * phenomenon was observed when two consecutive interrupt requests
2039  * from a given source get delivered to the same CPU and the source is
2040  * temporarily disabled in between.
2041  *
2042  * A workaround is to simulate an EOI message manually.  We achieve it
2043  * by setting the trigger mode to edge and then to level when the edge
2044  * trigger mode gets detected in the TMR of a local APIC for a
2045  * level-triggered interrupt.  We mask the source for the time of the
2046  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2047  * The idea is from Manfred Spraul.  --macro
2048  */
2049         i = IO_APIC_VECTOR(irq);
2050
2051         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2052
2053         ack_APIC_irq();
2054
2055         if (!(v & (1 << (i & 0x1f)))) {
2056                 atomic_inc(&irq_mis_count);
2057                 spin_lock(&ioapic_lock);
2058                 __mask_and_edge_IO_APIC_irq(irq);
2059                 __unmask_and_level_IO_APIC_irq(irq);
2060                 spin_unlock(&ioapic_lock);
2061         }
2062 }
2063
2064 #ifdef CONFIG_PCI_MSI
2065 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2066 {
2067         int irq = vector_to_irq(vector);
2068
2069         return startup_edge_ioapic_irq(irq);
2070 }
2071
2072 static void ack_edge_ioapic_vector(unsigned int vector)
2073 {
2074         int irq = vector_to_irq(vector);
2075
2076         move_native_irq(vector);
2077         ack_edge_ioapic_irq(irq);
2078 }
2079
2080 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2081 {
2082         int irq = vector_to_irq(vector);
2083
2084         return startup_level_ioapic_irq (irq);
2085 }
2086
2087 static void end_level_ioapic_vector (unsigned int vector)
2088 {
2089         int irq = vector_to_irq(vector);
2090
2091         move_native_irq(vector);
2092         end_level_ioapic_irq(irq);
2093 }
2094
2095 static void mask_IO_APIC_vector (unsigned int vector)
2096 {
2097         int irq = vector_to_irq(vector);
2098
2099         mask_IO_APIC_irq(irq);
2100 }
2101
2102 static void unmask_IO_APIC_vector (unsigned int vector)
2103 {
2104         int irq = vector_to_irq(vector);
2105
2106         unmask_IO_APIC_irq(irq);
2107 }
2108
2109 #ifdef CONFIG_SMP
2110 static void set_ioapic_affinity_vector (unsigned int vector,
2111                                         cpumask_t cpu_mask)
2112 {
2113         int irq = vector_to_irq(vector);
2114
2115         set_native_irq_info(vector, cpu_mask);
2116         set_ioapic_affinity_irq(irq, cpu_mask);
2117 }
2118 #endif
2119 #endif
2120
2121 static int ioapic_retrigger(unsigned int irq)
2122 {
2123         send_IPI_self(IO_APIC_VECTOR(irq));
2124
2125         return 1;
2126 }
2127
2128 /*
2129  * Level and edge triggered IO-APIC interrupts need different handling,
2130  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2131  * handled with the level-triggered descriptor, but that one has slightly
2132  * more overhead. Level-triggered interrupts cannot be handled with the
2133  * edge-triggered handler, without risking IRQ storms and other ugly
2134  * races.
2135  */
2136 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2137         .typename       = "IO-APIC-edge",
2138         .startup        = startup_edge_ioapic,
2139         .shutdown       = shutdown_edge_ioapic,
2140         .enable         = enable_edge_ioapic,
2141         .disable        = disable_edge_ioapic,
2142         .ack            = ack_edge_ioapic,
2143         .end            = end_edge_ioapic,
2144 #ifdef CONFIG_SMP
2145         .set_affinity   = set_ioapic_affinity,
2146 #endif
2147         .retrigger      = ioapic_retrigger,
2148 };
2149
2150 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2151         .typename       = "IO-APIC-level",
2152         .startup        = startup_level_ioapic,
2153         .shutdown       = shutdown_level_ioapic,
2154         .enable         = enable_level_ioapic,
2155         .disable        = disable_level_ioapic,
2156         .ack            = mask_and_ack_level_ioapic,
2157         .end            = end_level_ioapic,
2158 #ifdef CONFIG_SMP
2159         .set_affinity   = set_ioapic_affinity,
2160 #endif
2161         .retrigger      = ioapic_retrigger,
2162 };
2163 #endif /* !CONFIG_XEN */
2164
2165 static inline void init_IO_APIC_traps(void)
2166 {
2167         int irq;
2168
2169         /*
2170          * NOTE! The local APIC isn't very good at handling
2171          * multiple interrupts at the same interrupt level.
2172          * As the interrupt level is determined by taking the
2173          * vector number and shifting that right by 4, we
2174          * want to spread these out a bit so that they don't
2175          * all fall in the same interrupt level.
2176          *
2177          * Also, we've got to be careful not to trash gate
2178          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2179          */
2180         for (irq = 0; irq < NR_IRQS ; irq++) {
2181                 int tmp = irq;
2182                 if (use_pci_vector()) {
2183                         if (!platform_legacy_irq(tmp))
2184                                 if ((tmp = vector_to_irq(tmp)) == -1)
2185                                         continue;
2186                 }
2187                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2188                         /*
2189                          * Hmm.. We don't have an entry for this,
2190                          * so default to an old-fashioned 8259
2191                          * interrupt if we can..
2192                          */
2193                         if (irq < 16)
2194                                 make_8259A_irq(irq);
2195 #ifndef CONFIG_XEN
2196                         else
2197                                 /* Strange. Oh, well.. */
2198                                 irq_desc[irq].chip = &no_irq_type;
2199 #endif
2200                 }
2201         }
2202 }
2203
2204 int timer_uses_ioapic_pin_0;
2205
2206 #ifndef CONFIG_XEN
2207 static void enable_lapic_irq (unsigned int irq)
2208 {
2209         unsigned long v;
2210
2211         v = apic_read(APIC_LVT0);
2212         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2213 }
2214
2215 static void disable_lapic_irq (unsigned int irq)
2216 {
2217         unsigned long v;
2218
2219         v = apic_read(APIC_LVT0);
2220         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2221 }
2222
2223 static void ack_lapic_irq (unsigned int irq)
2224 {
2225         ack_APIC_irq();
2226 }
2227
2228 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2229
2230 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2231         .typename       = "local-APIC-edge",
2232         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2233         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2234         .enable         = enable_lapic_irq,
2235         .disable        = disable_lapic_irq,
2236         .ack            = ack_lapic_irq,
2237         .end            = end_lapic_irq
2238 };
2239
2240 static void setup_nmi (void)
2241 {
2242         /*
2243          * Dirty trick to enable the NMI watchdog ...
2244          * We put the 8259A master into AEOI mode and
2245          * unmask on all local APICs LVT0 as NMI.
2246          *
2247          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2248          * is from Maciej W. Rozycki - so we do not have to EOI from
2249          * the NMI handler or the timer interrupt.
2250          */
2251         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2252
2253         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2254
2255         apic_printk(APIC_VERBOSE, " done.\n");
2256 }
2257
2258 /*
2259  * This looks a bit hackish but it's about the only one way of sending
2260  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2261  * not support the ExtINT mode, unfortunately.  We need to send these
2262  * cycles as some i82489DX-based boards have glue logic that keeps the
2263  * 8259A interrupt line asserted until INTA.  --macro
2264  */
2265 static inline void unlock_ExtINT_logic(void)
2266 {
2267         int apic, pin, i;
2268         struct IO_APIC_route_entry entry0, entry1;
2269         unsigned char save_control, save_freq_select;
2270         unsigned long flags;
2271
2272         pin  = find_isa_irq_pin(8, mp_INT);
2273         apic = find_isa_irq_apic(8, mp_INT);
2274         if (pin == -1)
2275                 return;
2276
2277         spin_lock_irqsave(&ioapic_lock, flags);
2278         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2279         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2280         spin_unlock_irqrestore(&ioapic_lock, flags);
2281         clear_IO_APIC_pin(apic, pin);
2282
2283         memset(&entry1, 0, sizeof(entry1));
2284
2285         entry1.dest_mode = 0;                   /* physical delivery */
2286         entry1.mask = 0;                        /* unmask IRQ now */
2287         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2288         entry1.delivery_mode = dest_ExtINT;
2289         entry1.polarity = entry0.polarity;
2290         entry1.trigger = 0;
2291         entry1.vector = 0;
2292
2293         spin_lock_irqsave(&ioapic_lock, flags);
2294         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2295         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2296         spin_unlock_irqrestore(&ioapic_lock, flags);
2297
2298         save_control = CMOS_READ(RTC_CONTROL);
2299         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2300         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2301                    RTC_FREQ_SELECT);
2302         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2303
2304         i = 100;
2305         while (i-- > 0) {
2306                 mdelay(10);
2307                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2308                         i -= 10;
2309         }
2310
2311         CMOS_WRITE(save_control, RTC_CONTROL);
2312         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2313         clear_IO_APIC_pin(apic, pin);
2314
2315         spin_lock_irqsave(&ioapic_lock, flags);
2316         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2317         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2318         spin_unlock_irqrestore(&ioapic_lock, flags);
2319 }
2320
2321 /*
2322  * This code may look a bit paranoid, but it's supposed to cooperate with
2323  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2324  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2325  * fanatically on his truly buggy board.
2326  */
2327 static inline void check_timer(void)
2328 {
2329         int apic1, pin1, apic2, pin2;
2330         int vector;
2331
2332         /*
2333          * get/set the timer IRQ vector:
2334          */
2335         disable_8259A_irq(0);
2336         vector = assign_irq_vector(0);
2337         set_intr_gate(vector, interrupt[0]);
2338
2339         /*
2340          * Subtle, code in do_timer_interrupt() expects an AEOI
2341          * mode for the 8259A whenever interrupts are routed
2342          * through I/O APICs.  Also IRQ0 has to be enabled in
2343          * the 8259A which implies the virtual wire has to be
2344          * disabled in the local APIC.
2345          */
2346         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2347         init_8259A(1);
2348         timer_ack = 1;
2349         if (timer_over_8254 > 0)
2350                 enable_8259A_irq(0);
2351
2352         pin1  = find_isa_irq_pin(0, mp_INT);
2353         apic1 = find_isa_irq_apic(0, mp_INT);
2354         pin2  = ioapic_i8259.pin;
2355         apic2 = ioapic_i8259.apic;
2356
2357         if (pin1 == 0)
2358                 timer_uses_ioapic_pin_0 = 1;
2359
2360         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2361                 vector, apic1, pin1, apic2, pin2);
2362
2363         if (pin1 != -1) {
2364                 /*
2365                  * Ok, does IRQ0 through the IOAPIC work?
2366                  */
2367                 unmask_IO_APIC_irq(0);
2368                 if (timer_irq_works()) {
2369                         if (nmi_watchdog == NMI_IO_APIC) {
2370                                 disable_8259A_irq(0);
2371                                 setup_nmi();
2372                                 enable_8259A_irq(0);
2373                         }
2374                         if (disable_timer_pin_1 > 0)
2375                                 clear_IO_APIC_pin(0, pin1);
2376                         return;
2377                 }
2378                 clear_IO_APIC_pin(apic1, pin1);
2379                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2380                                 "IO-APIC\n");
2381         }
2382
2383         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2384         if (pin2 != -1) {
2385                 printk("\n..... (found pin %d) ...", pin2);
2386                 /*
2387                  * legacy devices should be connected to IO APIC #0
2388                  */
2389                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2390                 if (timer_irq_works()) {
2391                         printk("works.\n");
2392                         if (pin1 != -1)
2393                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2394                         else
2395                                 add_pin_to_irq(0, apic2, pin2);
2396                         if (nmi_watchdog == NMI_IO_APIC) {
2397                                 setup_nmi();
2398                         }
2399                         return;
2400                 }
2401                 /*
2402                  * Cleanup, just in case ...
2403                  */
2404                 clear_IO_APIC_pin(apic2, pin2);
2405         }
2406         printk(" failed.\n");
2407
2408         if (nmi_watchdog == NMI_IO_APIC) {
2409                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2410                 nmi_watchdog = 0;
2411         }
2412
2413         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2414
2415         disable_8259A_irq(0);
2416         irq_desc[0].chip = &lapic_irq_type;
2417         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2418         enable_8259A_irq(0);
2419
2420         if (timer_irq_works()) {
2421                 printk(" works.\n");
2422                 return;
2423         }
2424         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2425         printk(" failed.\n");
2426
2427         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2428
2429         timer_ack = 0;
2430         init_8259A(0);
2431         make_8259A_irq(0);
2432         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2433
2434         unlock_ExtINT_logic();
2435
2436         if (timer_irq_works()) {
2437                 printk(" works.\n");
2438                 return;
2439         }
2440         printk(" failed :(.\n");
2441         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2442                 "report.  Then try booting with the 'noapic' option");
2443 }
2444 #else
2445 #define check_timer() ((void)0)
2446 #endif
2447
2448 /*
2449  *
2450  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2451  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2452  *   Linux doesn't really care, as it's not actually used
2453  *   for any interrupt handling anyway.
2454  */
2455 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2456
2457 void __init setup_IO_APIC(void)
2458 {
2459         enable_IO_APIC();
2460
2461         if (acpi_ioapic)
2462                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2463         else
2464                 io_apic_irqs = ~PIC_IRQS;
2465
2466         printk("ENABLING IO-APIC IRQs\n");
2467
2468         /*
2469          * Set up IO-APIC IRQ routing.
2470          */
2471         if (!acpi_ioapic)
2472                 setup_ioapic_ids_from_mpc();
2473 #ifndef CONFIG_XEN
2474         sync_Arb_IDs();
2475 #endif
2476         setup_IO_APIC_irqs();
2477         init_IO_APIC_traps();
2478         check_timer();
2479         if (!acpi_ioapic)
2480                 print_IO_APIC();
2481 }
2482
2483 static int __init setup_disable_8254_timer(char *s)
2484 {
2485         timer_over_8254 = -1;
2486         return 1;
2487 }
2488 static int __init setup_enable_8254_timer(char *s)
2489 {
2490         timer_over_8254 = 2;
2491         return 1;
2492 }
2493
2494 __setup("disable_8254_timer", setup_disable_8254_timer);
2495 __setup("enable_8254_timer", setup_enable_8254_timer);
2496
2497 /*
2498  *      Called after all the initialization is done. If we didnt find any
2499  *      APIC bugs then we can allow the modify fast path
2500  */
2501
2502 static int __init io_apic_bug_finalize(void)
2503 {
2504         if(sis_apic_bug == -1)
2505                 sis_apic_bug = 0;
2506         if (is_initial_xendomain()) {
2507                 dom0_op_t op = { .cmd = DOM0_PLATFORM_QUIRK };
2508                 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2509                         QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2510                 HYPERVISOR_dom0_op(&op);
2511         }
2512         return 0;
2513 }
2514
2515 late_initcall(io_apic_bug_finalize);
2516
2517 struct sysfs_ioapic_data {
2518         struct sys_device dev;
2519         struct IO_APIC_route_entry entry[0];
2520 };
2521 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2522
2523 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2524 {
2525         struct IO_APIC_route_entry *entry;
2526         struct sysfs_ioapic_data *data;
2527         unsigned long flags;
2528         int i;
2529
2530         data = container_of(dev, struct sysfs_ioapic_data, dev);
2531         entry = data->entry;
2532         spin_lock_irqsave(&ioapic_lock, flags);
2533         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2534                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2535                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2536         }
2537         spin_unlock_irqrestore(&ioapic_lock, flags);
2538
2539         return 0;
2540 }
2541
2542 static int ioapic_resume(struct sys_device *dev)
2543 {
2544         struct IO_APIC_route_entry *entry;
2545         struct sysfs_ioapic_data *data;
2546         unsigned long flags;
2547         union IO_APIC_reg_00 reg_00;
2548         int i;
2549
2550         data = container_of(dev, struct sysfs_ioapic_data, dev);
2551         entry = data->entry;
2552
2553         spin_lock_irqsave(&ioapic_lock, flags);
2554         reg_00.raw = io_apic_read(dev->id, 0);
2555         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2556                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2557                 io_apic_write(dev->id, 0, reg_00.raw);
2558         }
2559         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2560                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2561                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2562         }
2563         spin_unlock_irqrestore(&ioapic_lock, flags);
2564
2565         return 0;
2566 }
2567
2568 static struct sysdev_class ioapic_sysdev_class = {
2569         set_kset_name("ioapic"),
2570         .suspend = ioapic_suspend,
2571         .resume = ioapic_resume,
2572 };
2573
2574 static int __init ioapic_init_sysfs(void)
2575 {
2576         struct sys_device * dev;
2577         int i, size, error = 0;
2578
2579         error = sysdev_class_register(&ioapic_sysdev_class);
2580         if (error)
2581                 return error;
2582
2583         for (i = 0; i < nr_ioapics; i++ ) {
2584                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2585                         * sizeof(struct IO_APIC_route_entry);
2586                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2587                 if (!mp_ioapic_data[i]) {
2588                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2589                         continue;
2590                 }
2591                 memset(mp_ioapic_data[i], 0, size);
2592                 dev = &mp_ioapic_data[i]->dev;
2593                 dev->id = i;
2594                 dev->cls = &ioapic_sysdev_class;
2595                 error = sysdev_register(dev);
2596                 if (error) {
2597                         kfree(mp_ioapic_data[i]);
2598                         mp_ioapic_data[i] = NULL;
2599                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2600                         continue;
2601                 }
2602         }
2603
2604         return 0;
2605 }
2606
2607 device_initcall(ioapic_init_sysfs);
2608
2609 /* --------------------------------------------------------------------------
2610                           ACPI-based IOAPIC Configuration
2611    -------------------------------------------------------------------------- */
2612
2613 #ifdef CONFIG_ACPI
2614
2615 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2616 {
2617 #ifndef CONFIG_XEN
2618         union IO_APIC_reg_00 reg_00;
2619         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2620         physid_mask_t tmp;
2621         unsigned long flags;
2622         int i = 0;
2623
2624         /*
2625          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2626          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2627          * supports up to 16 on one shared APIC bus.
2628          *
2629          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2630          *      advantage of new APIC bus architecture.
2631          */
2632
2633         if (physids_empty(apic_id_map))
2634                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2635
2636         spin_lock_irqsave(&ioapic_lock, flags);
2637         reg_00.raw = io_apic_read(ioapic, 0);
2638         spin_unlock_irqrestore(&ioapic_lock, flags);
2639
2640         if (apic_id >= get_physical_broadcast()) {
2641                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2642                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2643                 apic_id = reg_00.bits.ID;
2644         }
2645
2646         /*
2647          * Every APIC in a system must have a unique ID or we get lots of nice
2648          * 'stuck on smp_invalidate_needed IPI wait' messages.
2649          */
2650         if (check_apicid_used(apic_id_map, apic_id)) {
2651
2652                 for (i = 0; i < get_physical_broadcast(); i++) {
2653                         if (!check_apicid_used(apic_id_map, i))
2654                                 break;
2655                 }
2656
2657                 if (i == get_physical_broadcast())
2658                         panic("Max apic_id exceeded!\n");
2659
2660                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2661                         "trying %d\n", ioapic, apic_id, i);
2662
2663                 apic_id = i;
2664         }
2665
2666         tmp = apicid_to_cpu_present(apic_id);
2667         physids_or(apic_id_map, apic_id_map, tmp);
2668
2669         if (reg_00.bits.ID != apic_id) {
2670                 reg_00.bits.ID = apic_id;
2671
2672                 spin_lock_irqsave(&ioapic_lock, flags);
2673                 io_apic_write(ioapic, 0, reg_00.raw);
2674                 reg_00.raw = io_apic_read(ioapic, 0);
2675                 spin_unlock_irqrestore(&ioapic_lock, flags);
2676
2677                 /* Sanity check */
2678                 if (reg_00.bits.ID != apic_id) {
2679                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2680                         return -1;
2681                 }
2682         }
2683
2684         apic_printk(APIC_VERBOSE, KERN_INFO
2685                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2686 #endif /* !CONFIG_XEN */
2687
2688         return apic_id;
2689 }
2690
2691
2692 int __init io_apic_get_version (int ioapic)
2693 {
2694         union IO_APIC_reg_01    reg_01;
2695         unsigned long flags;
2696
2697         spin_lock_irqsave(&ioapic_lock, flags);
2698         reg_01.raw = io_apic_read(ioapic, 1);
2699         spin_unlock_irqrestore(&ioapic_lock, flags);
2700
2701         return reg_01.bits.version;
2702 }
2703
2704
2705 int __init io_apic_get_redir_entries (int ioapic)
2706 {
2707         union IO_APIC_reg_01    reg_01;
2708         unsigned long flags;
2709
2710         spin_lock_irqsave(&ioapic_lock, flags);
2711         reg_01.raw = io_apic_read(ioapic, 1);
2712         spin_unlock_irqrestore(&ioapic_lock, flags);
2713
2714         return reg_01.bits.entries;
2715 }
2716
2717
2718 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2719 {
2720         struct IO_APIC_route_entry entry;
2721         unsigned long flags;
2722
2723         if (!IO_APIC_IRQ(irq)) {
2724                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2725                         ioapic);
2726                 return -EINVAL;
2727         }
2728
2729         /*
2730          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2731          * Note that we mask (disable) IRQs now -- these get enabled when the
2732          * corresponding device driver registers for this IRQ.
2733          */
2734
2735         memset(&entry,0,sizeof(entry));
2736
2737         entry.delivery_mode = INT_DELIVERY_MODE;
2738         entry.dest_mode = INT_DEST_MODE;
2739         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2740         entry.trigger = edge_level;
2741         entry.polarity = active_high_low;
2742         entry.mask  = 1;
2743
2744         /*
2745          * IRQs < 16 are already in the irq_2_pin[] map
2746          */
2747         if (irq >= 16)
2748                 add_pin_to_irq(irq, ioapic, pin);
2749
2750         entry.vector = assign_irq_vector(irq);
2751
2752         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2753                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2754                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2755                 edge_level, active_high_low);
2756
2757         ioapic_register_intr(irq, entry.vector, edge_level);
2758
2759         if (!ioapic && (irq < 16))
2760                 disable_8259A_irq(irq);
2761
2762         spin_lock_irqsave(&ioapic_lock, flags);
2763         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2764         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2765         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2766         spin_unlock_irqrestore(&ioapic_lock, flags);
2767
2768         return 0;
2769 }
2770
2771 #endif /* CONFIG_ACPI */