arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/compiler.h>
  33 #include <linux/acpi.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/timer.h>
  39
  40 #include <mach_apic.h>
  41
  42 #include "io_ports.h"
  43
  44 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  45
  46 /*
  47  *      Is the SiS APIC rmw bug present ?
  48  *      -1 = don't know, 0 = no, 1 = yes
  49  */
  50 int sis_apic_bug = -1;
  51
  52 /*
  53  * # of IRQ routing registers
  54  */
  55 int nr_ioapic_registers[MAX_IO_APICS];
  56
  57 /*
  58  * Rough estimation of how many shared IRQs there are, can
  59  * be changed anytime.
  60  */
  61 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  62 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  63
  64 /*
  65  * This is performance-critical, we want to do it O(1)
  66  *
  67  * the indexing order of this array favors 1:1 mappings
  68  * between pins and IRQs.
  69  */
  70
  71 static struct irq_pin_list {
  72         int apic, pin, next;
  73 } irq_2_pin[PIN_MAP_SIZE];
  74
  75 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  76 #ifdef CONFIG_PCI_USE_VECTOR
  77 #define vector_to_irq(vector)   \
  78         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  79 #else
  80 #define vector_to_irq(vector)   (vector)
  81 #endif
  82
  83 /*
  84  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  85  * shared ISA-space IRQs, so we have to support them. We are super
  86  * fast in the common case, and fast for shared ISA-space IRQs.
  87  */
  88 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
  89 {
  90         static int first_free_entry = NR_IRQS;
  91         struct irq_pin_list *entry = irq_2_pin + irq;
  92
  93         while (entry->next)
  94                 entry = irq_2_pin + entry->next;
  95
  96         if (entry->pin != -1) {
  97                 entry->next = first_free_entry;
  98                 entry = irq_2_pin + entry->next;
  99                 if (++first_free_entry >= PIN_MAP_SIZE)
 100                         panic("io_apic.c: whoops");
 101         }
 102         entry->apic = apic;
 103         entry->pin = pin;
 104 }
 105
 106 /*
 107  * Reroute an IRQ to a different pin.
 108  */
 109 static void __init replace_pin_at_irq(unsigned int irq,
 110                                       int oldapic, int oldpin,
 111                                       int newapic, int newpin)
 112 {
 113         struct irq_pin_list *entry = irq_2_pin + irq;
 114
 115         while (1) {
 116                 if (entry->apic == oldapic && entry->pin == oldpin) {
 117                         entry->apic = newapic;
 118                         entry->pin = newpin;
 119                 }
 120                 if (!entry->next)
 121                         break;
 122                 entry = irq_2_pin + entry->next;
 123         }
 124 }
 125
 126 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 127 {
 128         struct irq_pin_list *entry = irq_2_pin + irq;
 129         unsigned int pin, reg;
 130
 131         for (;;) {
 132                 pin = entry->pin;
 133                 if (pin == -1)
 134                         break;
 135                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 136                 reg &= ~disable;
 137                 reg |= enable;
 138                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 139                 if (!entry->next)
 140                         break;
 141                 entry = irq_2_pin + entry->next;
 142         }
 143 }
 144
 145 /* mask = 1 */
 146 static void __mask_IO_APIC_irq (unsigned int irq)
 147 {
 148         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 149 }
 150
 151 /* mask = 0 */
 152 static void __unmask_IO_APIC_irq (unsigned int irq)
 153 {
 154         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 155 }
 156
 157 /* mask = 1, trigger = 0 */
 158 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 159 {
 160         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 161 }
 162
 163 /* mask = 0, trigger = 1 */
 164 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 165 {
 166         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 167 }
 168
 169 static void mask_IO_APIC_irq (unsigned int irq)
 170 {
 171         unsigned long flags;
 172
 173         spin_lock_irqsave(&ioapic_lock, flags);
 174         __mask_IO_APIC_irq(irq);
 175         spin_unlock_irqrestore(&ioapic_lock, flags);
 176 }
 177
 178 static void unmask_IO_APIC_irq (unsigned int irq)
 179 {
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&ioapic_lock, flags);
 183         __unmask_IO_APIC_irq(irq);
 184         spin_unlock_irqrestore(&ioapic_lock, flags);
 185 }
 186
 187 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 188 {
 189         struct IO_APIC_route_entry entry;
 190         unsigned long flags;
 191
 192         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 193         spin_lock_irqsave(&ioapic_lock, flags);
 194         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 195         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 196         spin_unlock_irqrestore(&ioapic_lock, flags);
 197         if (entry.delivery_mode == dest_SMI)
 198                 return;
 199
 200         /*
 201          * Disable it in the IO-APIC irq-routing table:
 202          */
 203         memset(&entry, 0, sizeof(entry));
 204         entry.mask = 1;
 205         spin_lock_irqsave(&ioapic_lock, flags);
 206         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 207         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 208         spin_unlock_irqrestore(&ioapic_lock, flags);
 209 }
 210
 211 static void clear_IO_APIC (void)
 212 {
 213         int apic, pin;
 214
 215         for (apic = 0; apic < nr_ioapics; apic++)
 216                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 217                         clear_IO_APIC_pin(apic, pin);
 218 }
 219
 220 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 221 {
 222         unsigned long flags;
 223         int pin;
 224         struct irq_pin_list *entry = irq_2_pin + irq;
 225         unsigned int apicid_value;
 226
 227         apicid_value = cpu_mask_to_apicid(mk_cpumask_const(cpumask));
 228         /* Prepare to do the io_apic_write */
 229         apicid_value = apicid_value << 24;
 230         spin_lock_irqsave(&ioapic_lock, flags);
 231         for (;;) {
 232                 pin = entry->pin;
 233                 if (pin == -1)
 234                         break;
 235                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 236                 if (!entry->next)
 237                         break;
 238                 entry = irq_2_pin + entry->next;
 239         }
 240         spin_unlock_irqrestore(&ioapic_lock, flags);
 241 }
 242
 243 #if defined(CONFIG_IRQBALANCE)
 244 # include <asm/processor.h>     /* kernel_thread() */
 245 # include <linux/kernel_stat.h> /* kstat */
 246 # include <linux/slab.h>                /* kmalloc() */
 247 # include <linux/timer.h>       /* time_after() */
 248
 249 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 250 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 251 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 252 # else
 253 #  define TDprintk(x...)
 254 #  define Dprintk(x...)
 255 # endif
 256
 257 extern cpumask_t irq_affinity[NR_IRQS];
 258
 259 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
 260
 261 #define IRQBALANCE_CHECK_ARCH -999
 262 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 263 static int physical_balance = 0;
 264
 265 struct irq_cpu_info {
 266         unsigned long * last_irq;
 267         unsigned long * irq_delta;
 268         unsigned long irq;
 269 } irq_cpu_data[NR_CPUS];
 270
 271 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 272 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 273 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 274
 275 #define IDLE_ENOUGH(cpu,now) \
 276                 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
 277
 278 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 279
 280 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 281
 282 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 283 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 284 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 285 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 286
 287 long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 288
 289 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 290                         unsigned long now, int direction)
 291 {
 292         int search_idle = 1;
 293         int cpu = curr_cpu;
 294
 295         goto inside;
 296
 297         do {
 298                 if (unlikely(cpu == curr_cpu))
 299                         search_idle = 0;
 300 inside:
 301                 if (direction == 1) {
 302                         cpu++;
 303                         if (cpu >= NR_CPUS)
 304                                 cpu = 0;
 305                 } else {
 306                         cpu--;
 307                         if (cpu == -1)
 308                                 cpu = NR_CPUS-1;
 309                 }
 310         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 311                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 312
 313         return cpu;
 314 }
 315
 316 static inline void balance_irq(int cpu, int irq)
 317 {
 318         unsigned long now = jiffies;
 319         cpumask_t allowed_mask;
 320         unsigned int new_cpu;
 321
 322         if (irqbalance_disabled)
 323                 return;
 324
 325         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 326         new_cpu = move(cpu, allowed_mask, now, 1);
 327         if (cpu != new_cpu) {
 328                 irq_desc_t *desc = irq_desc + irq;
 329                 unsigned long flags;
 330
 331                 spin_lock_irqsave(&desc->lock, flags);
 332                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
 333                 spin_unlock_irqrestore(&desc->lock, flags);
 334         }
 335 }
 336
 337 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 338 {
 339         int i, j;
 340         Dprintk("Rotating IRQs among CPUs.\n");
 341         for (i = 0; i < NR_CPUS; i++) {
 342                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 343                         if (!irq_desc[j].action)
 344                                 continue;
 345                         /* Is it a significant load ?  */
 346                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 347                                                 useful_load_threshold)
 348                                 continue;
 349                         balance_irq(i, j);
 350                 }
 351         }
 352         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 353                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 354         return;
 355 }
 356
 357 static void do_irq_balance(void)
 358 {
 359         int i, j;
 360         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 361         unsigned long move_this_load = 0;
 362         int max_loaded = 0, min_loaded = 0;
 363         int load;
 364         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 365         int selected_irq;
 366         int tmp_loaded, first_attempt = 1;
 367         unsigned long tmp_cpu_irq;
 368         unsigned long imbalance = 0;
 369         cpumask_t allowed_mask, target_cpu_mask, tmp;
 370
 371         for (i = 0; i < NR_CPUS; i++) {
 372                 int package_index;
 373                 CPU_IRQ(i) = 0;
 374                 if (!cpu_online(i))
 375                         continue;
 376                 package_index = CPU_TO_PACKAGEINDEX(i);
 377                 for (j = 0; j < NR_IRQS; j++) {
 378                         unsigned long value_now, delta;
 379                         /* Is this an active IRQ? */
 380                         if (!irq_desc[j].action)
 381                                 continue;
 382                         if ( package_index == i )
 383                                 IRQ_DELTA(package_index,j) = 0;
 384                         /* Determine the total count per processor per IRQ */
 385                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 386
 387                         /* Determine the activity per processor per IRQ */
 388                         delta = value_now - LAST_CPU_IRQ(i,j);
 389
 390                         /* Update last_cpu_irq[][] for the next time */
 391                         LAST_CPU_IRQ(i,j) = value_now;
 392
 393                         /* Ignore IRQs whose rate is less than the clock */
 394                         if (delta < useful_load_threshold)
 395                                 continue;
 396                         /* update the load for the processor or package total */
 397                         IRQ_DELTA(package_index,j) += delta;
 398
 399                         /* Keep track of the higher numbered sibling as well */
 400                         if (i != package_index)
 401                                 CPU_IRQ(i) += delta;
 402                         /*
 403                          * We have sibling A and sibling B in the package
 404                          *
 405                          * cpu_irq[A] = load for cpu A + load for cpu B
 406                          * cpu_irq[B] = load for cpu B
 407                          */
 408                         CPU_IRQ(package_index) += delta;
 409                 }
 410         }
 411         /* Find the least loaded processor package */
 412         for (i = 0; i < NR_CPUS; i++) {
 413                 if (!cpu_online(i))
 414                         continue;
 415                 if (i != CPU_TO_PACKAGEINDEX(i))
 416                         continue;
 417                 if (min_cpu_irq > CPU_IRQ(i)) {
 418                         min_cpu_irq = CPU_IRQ(i);
 419                         min_loaded = i;
 420                 }
 421         }
 422         max_cpu_irq = ULONG_MAX;
 423
 424 tryanothercpu:
 425         /* Look for heaviest loaded processor.
 426          * We may come back to get the next heaviest loaded processor.
 427          * Skip processors with trivial loads.
 428          */
 429         tmp_cpu_irq = 0;
 430         tmp_loaded = -1;
 431         for (i = 0; i < NR_CPUS; i++) {
 432                 if (!cpu_online(i))
 433                         continue;
 434                 if (i != CPU_TO_PACKAGEINDEX(i))
 435                         continue;
 436                 if (max_cpu_irq <= CPU_IRQ(i))
 437                         continue;
 438                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 439                         tmp_cpu_irq = CPU_IRQ(i);
 440                         tmp_loaded = i;
 441                 }
 442         }
 443
 444         if (tmp_loaded == -1) {
 445          /* In the case of small number of heavy interrupt sources,
 446           * loading some of the cpus too much. We use Ingo's original
 447           * approach to rotate them around.
 448           */
 449                 if (!first_attempt && imbalance >= useful_load_threshold) {
 450                         rotate_irqs_among_cpus(useful_load_threshold);
 451                         return;
 452                 }
 453                 goto not_worth_the_effort;
 454         }
 455
 456         first_attempt = 0;              /* heaviest search */
 457         max_cpu_irq = tmp_cpu_irq;      /* load */
 458         max_loaded = tmp_loaded;        /* processor */
 459         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 460
 461         Dprintk("max_loaded cpu = %d\n", max_loaded);
 462         Dprintk("min_loaded cpu = %d\n", min_loaded);
 463         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 464         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 465         Dprintk("load imbalance = %lu\n", imbalance);
 466
 467         /* if imbalance is less than approx 10% of max load, then
 468          * observe diminishing returns action. - quit
 469          */
 470         if (imbalance < (max_cpu_irq >> 3)) {
 471                 Dprintk("Imbalance too trivial\n");
 472                 goto not_worth_the_effort;
 473         }
 474
 475 tryanotherirq:
 476         /* if we select an IRQ to move that can't go where we want, then
 477          * see if there is another one to try.
 478          */
 479         move_this_load = 0;
 480         selected_irq = -1;
 481         for (j = 0; j < NR_IRQS; j++) {
 482                 /* Is this an active IRQ? */
 483                 if (!irq_desc[j].action)
 484                         continue;
 485                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 486                         continue;
 487                 /* Try to find the IRQ that is closest to the imbalance
 488                  * without going over.
 489                  */
 490                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 491                         move_this_load = IRQ_DELTA(max_loaded,j);
 492                         selected_irq = j;
 493                 }
 494         }
 495         if (selected_irq == -1) {
 496                 goto tryanothercpu;
 497         }
 498
 499         imbalance = move_this_load;
 500
 501         /* For physical_balance case, we accumlated both load
 502          * values in the one of the siblings cpu_irq[],
 503          * to use the same code for physical and logical processors
 504          * as much as possible.
 505          *
 506          * NOTE: the cpu_irq[] array holds the sum of the load for
 507          * sibling A and sibling B in the slot for the lowest numbered
 508          * sibling (A), _AND_ the load for sibling B in the slot for
 509          * the higher numbered sibling.
 510          *
 511          * We seek the least loaded sibling by making the comparison
 512          * (A+B)/2 vs B
 513          */
 514         load = CPU_IRQ(min_loaded) >> 1;
 515         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 516                 if (load > CPU_IRQ(j)) {
 517                         /* This won't change cpu_sibling_map[min_loaded] */
 518                         load = CPU_IRQ(j);
 519                         min_loaded = j;
 520                 }
 521         }
 522
 523         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 524         target_cpu_mask = cpumask_of_cpu(min_loaded);
 525         cpus_and(tmp, target_cpu_mask, allowed_mask);
 526
 527         if (!cpus_empty(tmp)) {
 528                 irq_desc_t *desc = irq_desc + selected_irq;
 529                 unsigned long flags;
 530
 531                 Dprintk("irq = %d moved to cpu = %d\n",
 532                                 selected_irq, min_loaded);
 533                 /* mark for change destination */
 534                 spin_lock_irqsave(&desc->lock, flags);
 535                 pending_irq_balance_cpumask[selected_irq] =
 536                                         cpumask_of_cpu(min_loaded);
 537                 spin_unlock_irqrestore(&desc->lock, flags);
 538                 /* Since we made a change, come back sooner to
 539                  * check for more variation.
 540                  */
 541                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 542                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 543                 return;
 544         }
 545         goto tryanotherirq;
 546
 547 not_worth_the_effort:
 548         /*
 549          * if we did not find an IRQ to move, then adjust the time interval
 550          * upward
 551          */
 552         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 553                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 554         Dprintk("IRQ worth rotating not found\n");
 555         return;
 556 }
 557
 558 int balanced_irq(void *unused)
 559 {
 560         int i;
 561         unsigned long prev_balance_time = jiffies;
 562         long time_remaining = balanced_irq_interval;
 563
 564         daemonize("kirqd");
 565
 566         /* push everything to CPU 0 to give us a starting point.  */
 567         for (i = 0 ; i < NR_IRQS ; i++) {
 568                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
 569         }
 570
 571 repeat:
 572         set_current_state(TASK_INTERRUPTIBLE);
 573         time_remaining = schedule_timeout(time_remaining);
 574         if (time_after(jiffies, prev_balance_time+balanced_irq_interval)) {
 575                 Dprintk("balanced_irq: calling do_irq_balance() %lu\n",
 576                                         jiffies);
 577                 do_irq_balance();
 578                 prev_balance_time = jiffies;
 579                 time_remaining = balanced_irq_interval;
 580         }
 581         goto repeat;
 582 }
 583
 584 static int __init balanced_irq_init(void)
 585 {
 586         int i;
 587         struct cpuinfo_x86 *c;
 588         cpumask_t tmp;
 589
 590         cpus_shift_right(tmp, cpu_online_map, 2);
 591         c = &boot_cpu_data;
 592         /* When not overwritten by the command line ask subarchitecture. */
 593         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 594                 irqbalance_disabled = NO_BALANCE_IRQ;
 595         if (irqbalance_disabled)
 596                 return 0;
 597
 598          /* disable irqbalance completely if there is only one processor online */
 599         if (num_online_cpus() < 2) {
 600                 irqbalance_disabled = 1;
 601                 return 0;
 602         }
 603         /*
 604          * Enable physical balance only if more than 1 physical processor
 605          * is present
 606          */
 607         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 608                 physical_balance = 1;
 609
 610         for (i = 0; i < NR_CPUS; i++) {
 611                 if (!cpu_online(i))
 612                         continue;
 613                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 614                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 615                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 616                         printk(KERN_ERR "balanced_irq_init: out of memory");
 617                         goto failed;
 618                 }
 619                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 620                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 621         }
 622
 623         printk(KERN_INFO "Starting balanced_irq\n");
 624         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 625                 return 0;
 626         else
 627                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 628 failed:
 629         for (i = 0; i < NR_CPUS; i++) {
 630                 if(irq_cpu_data[i].irq_delta)
 631                         kfree(irq_cpu_data[i].irq_delta);
 632                 if(irq_cpu_data[i].last_irq)
 633                         kfree(irq_cpu_data[i].last_irq);
 634         }
 635         return 0;
 636 }
 637
 638 static int __init irqbalance_disable(char *str)
 639 {
 640         irqbalance_disabled = 1;
 641         return 0;
 642 }
 643
 644 __setup("noirqbalance", irqbalance_disable);
 645
 646 static inline void move_irq(int irq)
 647 {
 648         /* note - we hold the desc->lock */
 649         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
 650                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
 651                 cpus_clear(pending_irq_balance_cpumask[irq]);
 652         }
 653 }
 654
 655 __initcall(balanced_irq_init);
 656
 657 #else /* !CONFIG_IRQBALANCE */
 658 static inline void move_irq(int irq) { }
 659 #endif /* CONFIG_IRQBALANCE */
 660
 661 #ifndef CONFIG_SMP
 662 void fastcall send_IPI_self(int vector)
 663 {
 664         unsigned int cfg;
 665
 666         /*
 667          * Wait for idle.
 668          */
 669         apic_wait_icr_idle();
 670         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 671         /*
 672          * Send the IPI. The write to APIC_ICR fires this off.
 673          */
 674         apic_write_around(APIC_ICR, cfg);
 675 }
 676 #endif /* !CONFIG_SMP */
 677
 678
 679 /*
 680  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 681  * specific CPU-side IRQs.
 682  */
 683
 684 #define MAX_PIRQS 8
 685 int pirq_entries [MAX_PIRQS];
 686 int pirqs_enabled;
 687 int skip_ioapic_setup;
 688
 689 static int __init ioapic_setup(char *str)
 690 {
 691         skip_ioapic_setup = 1;
 692         return 1;
 693 }
 694
 695 __setup("noapic", ioapic_setup);
 696
 697 static int __init ioapic_pirq_setup(char *str)
 698 {
 699         int i, max;
 700         int ints[MAX_PIRQS+1];
 701
 702         get_options(str, ARRAY_SIZE(ints), ints);
 703
 704         for (i = 0; i < MAX_PIRQS; i++)
 705                 pirq_entries[i] = -1;
 706
 707         pirqs_enabled = 1;
 708         printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
 709         max = MAX_PIRQS;
 710         if (ints[0] < MAX_PIRQS)
 711                 max = ints[0];
 712
 713         for (i = 0; i < max; i++) {
 714                 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 715                 /*
 716                  * PIRQs are mapped upside down, usually.
 717                  */
 718                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 719         }
 720         return 1;
 721 }
 722
 723 __setup("pirq=", ioapic_pirq_setup);
 724
 725 /*
 726  * Find the IRQ entry number of a certain pin.
 727  */
 728 static int __init find_irq_entry(int apic, int pin, int type)
 729 {
 730         int i;
 731
 732         for (i = 0; i < mp_irq_entries; i++)
 733                 if (mp_irqs[i].mpc_irqtype == type &&
 734                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 735                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 736                     mp_irqs[i].mpc_dstirq == pin)
 737                         return i;
 738
 739         return -1;
 740 }
 741
 742 /*
 743  * Find the pin to which IRQ[irq] (ISA) is connected
 744  */
 745 static int __init find_isa_irq_pin(int irq, int type)
 746 {
 747         int i;
 748
 749         for (i = 0; i < mp_irq_entries; i++) {
 750                 int lbus = mp_irqs[i].mpc_srcbus;
 751
 752                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 753                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 754                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 755                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 756                     ) &&
 757                     (mp_irqs[i].mpc_irqtype == type) &&
 758                     (mp_irqs[i].mpc_srcbusirq == irq))
 759
 760                         return mp_irqs[i].mpc_dstirq;
 761         }
 762         return -1;
 763 }
 764
 765 /*
 766  * Find a specific PCI IRQ entry.
 767  * Not an __init, possibly needed by modules
 768  */
 769 static int pin_2_irq(int idx, int apic, int pin);
 770
 771 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 772 {
 773         int apic, i, best_guess = -1;
 774
 775         Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 776                 bus, slot, pin);
 777         if (mp_bus_id_to_pci_bus[bus] == -1) {
 778                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 779                 return -1;
 780         }
 781         for (i = 0; i < mp_irq_entries; i++) {
 782                 int lbus = mp_irqs[i].mpc_srcbus;
 783
 784                 for (apic = 0; apic < nr_ioapics; apic++)
 785                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 786                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 787                                 break;
 788
 789                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 790                     !mp_irqs[i].mpc_irqtype &&
 791                     (bus == lbus) &&
 792                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 793                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 794
 795                         if (!(apic || IO_APIC_IRQ(irq)))
 796                                 continue;
 797
 798                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 799                                 return irq;
 800                         /*
 801                          * Use the first all-but-pin matching entry as a
 802                          * best-guess fuzzy result for broken mptables.
 803                          */
 804                         if (best_guess < 0)
 805                                 best_guess = irq;
 806                 }
 807         }
 808         return best_guess;
 809 }
 810
 811 /*
 812  * This function currently is only a helper for the i386 smp boot process where
 813  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 814  * so mask in all cases should simply be TARGET_CPUS
 815  */
 816 void __init setup_ioapic_dest(void)
 817 {
 818         int pin, ioapic, irq, irq_entry;
 819
 820         if (skip_ioapic_setup == 1)
 821                 return;
 822
 823         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 824                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 825                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 826                         if (irq_entry == -1)
 827                                 continue;
 828                         irq = pin_2_irq(irq_entry, ioapic, pin);
 829                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 830                 }
 831
 832         }
 833 }
 834
 835 /*
 836  * EISA Edge/Level control register, ELCR
 837  */
 838 static int __init EISA_ELCR(unsigned int irq)
 839 {
 840         if (irq < 16) {
 841                 unsigned int port = 0x4d0 + (irq >> 3);
 842                 return (inb(port) >> (irq & 7)) & 1;
 843         }
 844         printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
 845         return 0;
 846 }
 847
 848 /* EISA interrupts are always polarity zero and can be edge or level
 849  * trigger depending on the ELCR value.  If an interrupt is listed as
 850  * EISA conforming in the MP table, that means its trigger type must
 851  * be read in from the ELCR */
 852
 853 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 854 #define default_EISA_polarity(idx)      (0)
 855
 856 /* ISA interrupts are always polarity zero edge triggered,
 857  * when listed as conforming in the MP table. */
 858
 859 #define default_ISA_trigger(idx)        (0)
 860 #define default_ISA_polarity(idx)       (0)
 861
 862 /* PCI interrupts are always polarity one level triggered,
 863  * when listed as conforming in the MP table. */
 864
 865 #define default_PCI_trigger(idx)        (1)
 866 #define default_PCI_polarity(idx)       (1)
 867
 868 /* MCA interrupts are always polarity zero level triggered,
 869  * when listed as conforming in the MP table. */
 870
 871 #define default_MCA_trigger(idx)        (1)
 872 #define default_MCA_polarity(idx)       (0)
 873
 874 /* NEC98 interrupts are always polarity zero edge triggered,
 875  * when listed as conforming in the MP table. */
 876
 877 #define default_NEC98_trigger(idx)     (0)
 878 #define default_NEC98_polarity(idx)    (0)
 879
 880 static int __init MPBIOS_polarity(int idx)
 881 {
 882         int bus = mp_irqs[idx].mpc_srcbus;
 883         int polarity;
 884
 885         /*
 886          * Determine IRQ line polarity (high active or low active):
 887          */
 888         switch (mp_irqs[idx].mpc_irqflag & 3)
 889         {
 890                 case 0: /* conforms, ie. bus-type dependent polarity */
 891                 {
 892                         switch (mp_bus_id_to_type[bus])
 893                         {
 894                                 case MP_BUS_ISA: /* ISA pin */
 895                                 {
 896                                         polarity = default_ISA_polarity(idx);
 897                                         break;
 898                                 }
 899                                 case MP_BUS_EISA: /* EISA pin */
 900                                 {
 901                                         polarity = default_EISA_polarity(idx);
 902                                         break;
 903                                 }
 904                                 case MP_BUS_PCI: /* PCI pin */
 905                                 {
 906                                         polarity = default_PCI_polarity(idx);
 907                                         break;
 908                                 }
 909                                 case MP_BUS_MCA: /* MCA pin */
 910                                 {
 911                                         polarity = default_MCA_polarity(idx);
 912                                         break;
 913                                 }
 914                                 case MP_BUS_NEC98: /* NEC 98 pin */
 915                                 {
 916                                         polarity = default_NEC98_polarity(idx);
 917                                         break;
 918                                 }
 919                                 default:
 920                                 {
 921                                         printk(KERN_WARNING "broken BIOS!!\n");
 922                                         polarity = 1;
 923                                         break;
 924                                 }
 925                         }
 926                         break;
 927                 }
 928                 case 1: /* high active */
 929                 {
 930                         polarity = 0;
 931                         break;
 932                 }
 933                 case 2: /* reserved */
 934                 {
 935                         printk(KERN_WARNING "broken BIOS!!\n");
 936                         polarity = 1;
 937                         break;
 938                 }
 939                 case 3: /* low active */
 940                 {
 941                         polarity = 1;
 942                         break;
 943                 }
 944                 default: /* invalid */
 945                 {
 946                         printk(KERN_WARNING "broken BIOS!!\n");
 947                         polarity = 1;
 948                         break;
 949                 }
 950         }
 951         return polarity;
 952 }
 953
 954 static int __init MPBIOS_trigger(int idx)
 955 {
 956         int bus = mp_irqs[idx].mpc_srcbus;
 957         int trigger;
 958
 959         /*
 960          * Determine IRQ trigger mode (edge or level sensitive):
 961          */
 962         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 963         {
 964                 case 0: /* conforms, ie. bus-type dependent */
 965                 {
 966                         switch (mp_bus_id_to_type[bus])
 967                         {
 968                                 case MP_BUS_ISA: /* ISA pin */
 969                                 {
 970                                         trigger = default_ISA_trigger(idx);
 971                                         break;
 972                                 }
 973                                 case MP_BUS_EISA: /* EISA pin */
 974                                 {
 975                                         trigger = default_EISA_trigger(idx);
 976                                         break;
 977                                 }
 978                                 case MP_BUS_PCI: /* PCI pin */
 979                                 {
 980                                         trigger = default_PCI_trigger(idx);
 981                                         break;
 982                                 }
 983                                 case MP_BUS_MCA: /* MCA pin */
 984                                 {
 985                                         trigger = default_MCA_trigger(idx);
 986                                         break;
 987                                 }
 988                                 case MP_BUS_NEC98: /* NEC 98 pin */
 989                                 {
 990                                         trigger = default_NEC98_trigger(idx);
 991                                         break;
 992                                 }
 993                                 default:
 994                                 {
 995                                         printk(KERN_WARNING "broken BIOS!!\n");
 996                                         trigger = 1;
 997                                         break;
 998                                 }
 999                         }
1000                         break;
1001                 }
1002                 case 1: /* edge */
1003                 {
1004                         trigger = 0;
1005                         break;
1006                 }
1007                 case 2: /* reserved */
1008                 {
1009                         printk(KERN_WARNING "broken BIOS!!\n");
1010                         trigger = 1;
1011                         break;
1012                 }
1013                 case 3: /* level */
1014                 {
1015                         trigger = 1;
1016                         break;
1017                 }
1018                 default: /* invalid */
1019                 {
1020                         printk(KERN_WARNING "broken BIOS!!\n");
1021                         trigger = 0;
1022                         break;
1023                 }
1024         }
1025         return trigger;
1026 }
1027
1028 static inline int irq_polarity(int idx)
1029 {
1030         return MPBIOS_polarity(idx);
1031 }
1032
1033 static inline int irq_trigger(int idx)
1034 {
1035         return MPBIOS_trigger(idx);
1036 }
1037
1038 static int pin_2_irq(int idx, int apic, int pin)
1039 {
1040         int irq, i;
1041         int bus = mp_irqs[idx].mpc_srcbus;
1042
1043         /*
1044          * Debugging check, we are in big trouble if this message pops up!
1045          */
1046         if (mp_irqs[idx].mpc_dstirq != pin)
1047                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1048
1049         switch (mp_bus_id_to_type[bus])
1050         {
1051                 case MP_BUS_ISA: /* ISA pin */
1052                 case MP_BUS_EISA:
1053                 case MP_BUS_MCA:
1054                 case MP_BUS_NEC98:
1055                 {
1056                         irq = mp_irqs[idx].mpc_srcbusirq;
1057                         break;
1058                 }
1059                 case MP_BUS_PCI: /* PCI pin */
1060                 {
1061                         /*
1062                          * PCI IRQs are mapped in order
1063                          */
1064                         i = irq = 0;
1065                         while (i < apic)
1066                                 irq += nr_ioapic_registers[i++];
1067                         irq += pin;
1068                         if ((!apic) && (irq < 16))
1069                                 irq += 16;
1070                         break;
1071                 }
1072                 default:
1073                 {
1074                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1075                         irq = 0;
1076                         break;
1077                 }
1078         }
1079
1080         /*
1081          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1082          */
1083         if ((pin >= 16) && (pin <= 23)) {
1084                 if (pirq_entries[pin-16] != -1) {
1085                         if (!pirq_entries[pin-16]) {
1086                                 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
1087                         } else {
1088                                 irq = pirq_entries[pin-16];
1089                                 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
1090                                                 pin-16, irq);
1091                         }
1092                 }
1093         }
1094         return irq;
1095 }
1096
1097 static inline int IO_APIC_irq_trigger(int irq)
1098 {
1099         int apic, idx, pin;
1100
1101         for (apic = 0; apic < nr_ioapics; apic++) {
1102                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1103                         idx = find_irq_entry(apic,pin,mp_INT);
1104                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1105                                 return irq_trigger(idx);
1106                 }
1107         }
1108         /*
1109          * nonexistent IRQs are edge default
1110          */
1111         return 0;
1112 }
1113
1114 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1115 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1116
1117 #ifdef CONFIG_PCI_USE_VECTOR
1118 int assign_irq_vector(int irq)
1119 #else
1120 int __init assign_irq_vector(int irq)
1121 #endif
1122 {
1123         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1124
1125         BUG_ON(irq >= NR_IRQ_VECTORS);
1126         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1127                 return IO_APIC_VECTOR(irq);
1128 next:
1129         current_vector += 8;
1130         if (current_vector == SYSCALL_VECTOR)
1131                 goto next;
1132
1133         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1134                 offset++;
1135                 if (!(offset%8))
1136                         return -ENOSPC;
1137                 current_vector = FIRST_DEVICE_VECTOR + offset;
1138         }
1139
1140         vector_irq[current_vector] = irq;
1141         if (irq != AUTO_ASSIGN)
1142                 IO_APIC_VECTOR(irq) = current_vector;
1143
1144         return current_vector;
1145 }
1146
1147 static struct hw_interrupt_type ioapic_level_type;
1148 static struct hw_interrupt_type ioapic_edge_type;
1149
1150 #define IOAPIC_AUTO     -1
1151 #define IOAPIC_EDGE     0
1152 #define IOAPIC_LEVEL    1
1153
1154 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1155 {
1156         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1157                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1158                                 trigger == IOAPIC_LEVEL)
1159                         irq_desc[vector].handler = &ioapic_level_type;
1160                 else
1161                         irq_desc[vector].handler = &ioapic_edge_type;
1162                 set_intr_gate(vector, interrupt[vector]);
1163         } else  {
1164                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1165                                 trigger == IOAPIC_LEVEL)
1166                         irq_desc[irq].handler = &ioapic_level_type;
1167                 else
1168                         irq_desc[irq].handler = &ioapic_edge_type;
1169                 set_intr_gate(vector, interrupt[irq]);
1170         }
1171 }
1172
1173 void __init setup_IO_APIC_irqs(void)
1174 {
1175         struct IO_APIC_route_entry entry;
1176         int apic, pin, idx, irq, first_notcon = 1, vector;
1177         unsigned long flags;
1178
1179         printk(KERN_DEBUG "init IO_APIC IRQs\n");
1180
1181         for (apic = 0; apic < nr_ioapics; apic++) {
1182         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1183
1184                 /*
1185                  * add it to the IO-APIC irq-routing table:
1186                  */
1187                 memset(&entry,0,sizeof(entry));
1188
1189                 entry.delivery_mode = INT_DELIVERY_MODE;
1190                 entry.dest_mode = INT_DEST_MODE;
1191                 entry.mask = 0;                         /* enable IRQ */
1192                 entry.dest.logical.logical_dest =
1193                                         cpu_mask_to_apicid(TARGET_CPUS);
1194
1195                 idx = find_irq_entry(apic,pin,mp_INT);
1196                 if (idx == -1) {
1197                         if (first_notcon) {
1198                                 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
1199                                 first_notcon = 0;
1200                         } else
1201                                 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
1202                         continue;
1203                 }
1204
1205                 entry.trigger = irq_trigger(idx);
1206                 entry.polarity = irq_polarity(idx);
1207
1208                 if (irq_trigger(idx)) {
1209                         entry.trigger = 1;
1210                         entry.mask = 1;
1211                 }
1212
1213                 irq = pin_2_irq(idx, apic, pin);
1214                 /*
1215                  * skip adding the timer int on secondary nodes, which causes
1216                  * a small but painful rift in the time-space continuum
1217                  */
1218                 if (multi_timer_check(apic, irq))
1219                         continue;
1220                 else
1221                         add_pin_to_irq(irq, apic, pin);
1222
1223                 if (!apic && !IO_APIC_IRQ(irq))
1224                         continue;
1225
1226                 if (IO_APIC_IRQ(irq)) {
1227                         vector = assign_irq_vector(irq);
1228                         entry.vector = vector;
1229                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1230
1231                         if (!apic && (irq < 16))
1232                                 disable_8259A_irq(irq);
1233                 }
1234                 spin_lock_irqsave(&ioapic_lock, flags);
1235                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1236                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1237                 spin_unlock_irqrestore(&ioapic_lock, flags);
1238         }
1239         }
1240
1241         if (!first_notcon)
1242                 printk(" not connected.\n");
1243 }
1244
1245 /*
1246  * Set up the 8259A-master output pin:
1247  */
1248 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1249 {
1250         struct IO_APIC_route_entry entry;
1251         unsigned long flags;
1252
1253         memset(&entry,0,sizeof(entry));
1254
1255         disable_8259A_irq(0);
1256
1257         /* mask LVT0 */
1258         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1259
1260         /*
1261          * We use logical delivery to get the timer IRQ
1262          * to the first CPU.
1263          */
1264         entry.dest_mode = INT_DEST_MODE;
1265         entry.mask = 0;                                 /* unmask IRQ now */
1266         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1267         entry.delivery_mode = INT_DELIVERY_MODE;
1268         entry.polarity = 0;
1269         entry.trigger = 0;
1270         entry.vector = vector;
1271
1272         /*
1273          * The timer IRQ doesn't have to know that behind the
1274          * scene we have a 8259A-master in AEOI mode ...
1275          */
1276         irq_desc[0].handler = &ioapic_edge_type;
1277
1278         /*
1279          * Add it to the IO-APIC irq-routing table:
1280          */
1281         spin_lock_irqsave(&ioapic_lock, flags);
1282         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1283         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1284         spin_unlock_irqrestore(&ioapic_lock, flags);
1285
1286         enable_8259A_irq(0);
1287 }
1288
1289 static inline void UNEXPECTED_IO_APIC(void)
1290 {
1291 }
1292
1293 void __init print_IO_APIC(void)
1294 {
1295         int apic, i;
1296         union IO_APIC_reg_00 reg_00;
1297         union IO_APIC_reg_01 reg_01;
1298         union IO_APIC_reg_02 reg_02;
1299         union IO_APIC_reg_03 reg_03;
1300         unsigned long flags;
1301
1302         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1303         for (i = 0; i < nr_ioapics; i++)
1304                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1305                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1306
1307         /*
1308          * We are a bit conservative about what we expect.  We have to
1309          * know about every hardware change ASAP.
1310          */
1311         printk(KERN_INFO "testing the IO APIC.......................\n");
1312
1313         for (apic = 0; apic < nr_ioapics; apic++) {
1314
1315         spin_lock_irqsave(&ioapic_lock, flags);
1316         reg_00.raw = io_apic_read(apic, 0);
1317         reg_01.raw = io_apic_read(apic, 1);
1318         if (reg_01.bits.version >= 0x10)
1319                 reg_02.raw = io_apic_read(apic, 2);
1320         if (reg_01.bits.version >= 0x20)
1321                 reg_03.raw = io_apic_read(apic, 3);
1322         spin_unlock_irqrestore(&ioapic_lock, flags);
1323
1324         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1325         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1326         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1327         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1328         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1329         if (reg_00.bits.ID >= get_physical_broadcast())
1330                 UNEXPECTED_IO_APIC();
1331         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1332                 UNEXPECTED_IO_APIC();
1333
1334         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1335         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1336         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1337                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1338                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1339                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1340                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1341                 (reg_01.bits.entries != 0x2E) &&
1342                 (reg_01.bits.entries != 0x3F)
1343         )
1344                 UNEXPECTED_IO_APIC();
1345
1346         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1347         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1348         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1349                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1350                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1351                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1352                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1353         )
1354                 UNEXPECTED_IO_APIC();
1355         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1356                 UNEXPECTED_IO_APIC();
1357
1358         /*
1359          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1360          * but the value of reg_02 is read as the previous read register
1361          * value, so ignore it if reg_02 == reg_01.
1362          */
1363         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1364                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1365                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1366                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1367                         UNEXPECTED_IO_APIC();
1368         }
1369
1370         /*
1371          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1372          * or reg_03, but the value of reg_0[23] is read as the previous read
1373          * register value, so ignore it if reg_03 == reg_0[12].
1374          */
1375         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1376             reg_03.raw != reg_01.raw) {
1377                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1378                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1379                 if (reg_03.bits.__reserved_1)
1380                         UNEXPECTED_IO_APIC();
1381         }
1382
1383         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1384
1385         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1386                           " Stat Dest Deli Vect:   \n");
1387
1388         for (i = 0; i <= reg_01.bits.entries; i++) {
1389                 struct IO_APIC_route_entry entry;
1390
1391                 spin_lock_irqsave(&ioapic_lock, flags);
1392                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1393                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1394                 spin_unlock_irqrestore(&ioapic_lock, flags);
1395
1396                 printk(KERN_DEBUG " %02x %03X %02X  ",
1397                         i,
1398                         entry.dest.logical.logical_dest,
1399                         entry.dest.physical.physical_dest
1400                 );
1401
1402                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1403                         entry.mask,
1404                         entry.trigger,
1405                         entry.irr,
1406                         entry.polarity,
1407                         entry.delivery_status,
1408                         entry.dest_mode,
1409                         entry.delivery_mode,
1410                         entry.vector
1411                 );
1412         }
1413         }
1414         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1415         for (i = 0; i < NR_IRQS; i++) {
1416                 struct irq_pin_list *entry = irq_2_pin + i;
1417                 if (entry->pin < 0)
1418                         continue;
1419                 printk(KERN_DEBUG "IRQ%d ", i);
1420                 for (;;) {
1421                         printk("-> %d:%d", entry->apic, entry->pin);
1422                         if (!entry->next)
1423                                 break;
1424                         entry = irq_2_pin + entry->next;
1425                 }
1426                 printk("\n");
1427         }
1428
1429         printk(KERN_INFO ".................................... done.\n");
1430
1431         return;
1432 }
1433
1434 static void print_APIC_bitfield (int base)
1435 {
1436         unsigned int v;
1437         int i, j;
1438
1439         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1440         for (i = 0; i < 8; i++) {
1441                 v = apic_read(base + i*0x10);
1442                 for (j = 0; j < 32; j++) {
1443                         if (v & (1<<j))
1444                                 printk("1");
1445                         else
1446                                 printk("0");
1447                 }
1448                 printk("\n");
1449         }
1450 }
1451
1452 void /*__init*/ print_local_APIC(void * dummy)
1453 {
1454         unsigned int v, ver, maxlvt;
1455
1456         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1457                 smp_processor_id(), hard_smp_processor_id());
1458         v = apic_read(APIC_ID);
1459         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1460         v = apic_read(APIC_LVR);
1461         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1462         ver = GET_APIC_VERSION(v);
1463         maxlvt = get_maxlvt();
1464
1465         v = apic_read(APIC_TASKPRI);
1466         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1467
1468         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1469                 v = apic_read(APIC_ARBPRI);
1470                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1471                         v & APIC_ARBPRI_MASK);
1472                 v = apic_read(APIC_PROCPRI);
1473                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1474         }
1475
1476         v = apic_read(APIC_EOI);
1477         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1478         v = apic_read(APIC_RRR);
1479         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1480         v = apic_read(APIC_LDR);
1481         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1482         v = apic_read(APIC_DFR);
1483         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1484         v = apic_read(APIC_SPIV);
1485         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1486
1487         printk(KERN_DEBUG "... APIC ISR field:\n");
1488         print_APIC_bitfield(APIC_ISR);
1489         printk(KERN_DEBUG "... APIC TMR field:\n");
1490         print_APIC_bitfield(APIC_TMR);
1491         printk(KERN_DEBUG "... APIC IRR field:\n");
1492         print_APIC_bitfield(APIC_IRR);
1493
1494         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1495                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1496                         apic_write(APIC_ESR, 0);
1497                 v = apic_read(APIC_ESR);
1498                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1499         }
1500
1501         v = apic_read(APIC_ICR);
1502         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1503         v = apic_read(APIC_ICR2);
1504         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1505
1506         v = apic_read(APIC_LVTT);
1507         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1508
1509         if (maxlvt > 3) {                       /* PC is LVT#4. */
1510                 v = apic_read(APIC_LVTPC);
1511                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1512         }
1513         v = apic_read(APIC_LVT0);
1514         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1515         v = apic_read(APIC_LVT1);
1516         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1517
1518         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1519                 v = apic_read(APIC_LVTERR);
1520                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1521         }
1522
1523         v = apic_read(APIC_TMICT);
1524         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1525         v = apic_read(APIC_TMCCT);
1526         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1527         v = apic_read(APIC_TDCR);
1528         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1529         printk("\n");
1530 }
1531
1532 void print_all_local_APICs (void)
1533 {
1534         on_each_cpu(print_local_APIC, NULL, 1, 1);
1535 }
1536
1537 void /*__init*/ print_PIC(void)
1538 {
1539         extern spinlock_t i8259A_lock;
1540         unsigned int v;
1541         unsigned long flags;
1542
1543         printk(KERN_DEBUG "\nprinting PIC contents\n");
1544
1545         spin_lock_irqsave(&i8259A_lock, flags);
1546
1547         v = inb(0xa1) << 8 | inb(0x21);
1548         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1549
1550         v = inb(0xa0) << 8 | inb(0x20);
1551         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1552
1553         outb(0x0b,0xa0);
1554         outb(0x0b,0x20);
1555         v = inb(0xa0) << 8 | inb(0x20);
1556         outb(0x0a,0xa0);
1557         outb(0x0a,0x20);
1558
1559         spin_unlock_irqrestore(&i8259A_lock, flags);
1560
1561         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1562
1563         v = inb(0x4d1) << 8 | inb(0x4d0);
1564         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1565 }
1566
1567 static void __init enable_IO_APIC(void)
1568 {
1569         union IO_APIC_reg_01 reg_01;
1570         int i;
1571         unsigned long flags;
1572
1573         for (i = 0; i < PIN_MAP_SIZE; i++) {
1574                 irq_2_pin[i].pin = -1;
1575                 irq_2_pin[i].next = 0;
1576         }
1577         if (!pirqs_enabled)
1578                 for (i = 0; i < MAX_PIRQS; i++)
1579                         pirq_entries[i] = -1;
1580
1581         /*
1582          * The number of IO-APIC IRQ registers (== #pins):
1583          */
1584         for (i = 0; i < nr_ioapics; i++) {
1585                 spin_lock_irqsave(&ioapic_lock, flags);
1586                 reg_01.raw = io_apic_read(i, 1);
1587                 spin_unlock_irqrestore(&ioapic_lock, flags);
1588                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1589         }
1590
1591         /*
1592          * Do not trust the IO-APIC being empty at bootup
1593          */
1594         clear_IO_APIC();
1595 }
1596
1597 /*
1598  * Not an __init, needed by the reboot code
1599  */
1600 void disable_IO_APIC(void)
1601 {
1602         /*
1603          * Clear the IO-APIC before rebooting:
1604          */
1605         clear_IO_APIC();
1606
1607         disconnect_bsp_APIC();
1608 }
1609
1610 /*
1611  * function to set the IO-APIC physical IDs based on the
1612  * values stored in the MPC table.
1613  *
1614  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1615  */
1616
1617 #ifndef CONFIG_X86_NUMAQ
1618 static void __init setup_ioapic_ids_from_mpc(void)
1619 {
1620         union IO_APIC_reg_00 reg_00;
1621         physid_mask_t phys_id_present_map;
1622         int apic;
1623         int i;
1624         unsigned char old_id;
1625         unsigned long flags;
1626
1627         /*
1628          * This is broken; anything with a real cpu count has to
1629          * circumvent this idiocy regardless.
1630          */
1631         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1632
1633         /*
1634          * Set the IOAPIC ID to the value stored in the MPC table.
1635          */
1636         for (apic = 0; apic < nr_ioapics; apic++) {
1637
1638                 /* Read the register 0 value */
1639                 spin_lock_irqsave(&ioapic_lock, flags);
1640                 reg_00.raw = io_apic_read(apic, 0);
1641                 spin_unlock_irqrestore(&ioapic_lock, flags);
1642
1643                 old_id = mp_ioapics[apic].mpc_apicid;
1644
1645                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1646                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1647                                 apic, mp_ioapics[apic].mpc_apicid);
1648                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1649                                 reg_00.bits.ID);
1650                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1651                 }
1652
1653                 /* Don't check I/O APIC IDs for some xAPIC systems.  They have
1654                  * no meaning without the serial APIC bus. */
1655                 if (NO_IOAPIC_CHECK)
1656                         continue;
1657                 /*
1658                  * Sanity check, is the ID really free? Every APIC in a
1659                  * system must have a unique ID or we get lots of nice
1660                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1661                  */
1662                 if (check_apicid_used(phys_id_present_map,
1663                                         mp_ioapics[apic].mpc_apicid)) {
1664                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1665                                 apic, mp_ioapics[apic].mpc_apicid);
1666                         for (i = 0; i < get_physical_broadcast(); i++)
1667                                 if (!physid_isset(i, phys_id_present_map))
1668                                         break;
1669                         if (i >= get_physical_broadcast())
1670                                 panic("Max APIC ID exceeded!\n");
1671                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1672                                 i);
1673                         physid_set(i, phys_id_present_map);
1674                         mp_ioapics[apic].mpc_apicid = i;
1675                 } else {
1676                         physid_mask_t tmp;
1677                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1678                         printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1679                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1680                 }
1681
1682
1683                 /*
1684                  * We need to adjust the IRQ routing table
1685                  * if the ID changed.
1686                  */
1687                 if (old_id != mp_ioapics[apic].mpc_apicid)
1688                         for (i = 0; i < mp_irq_entries; i++)
1689                                 if (mp_irqs[i].mpc_dstapic == old_id)
1690                                         mp_irqs[i].mpc_dstapic
1691                                                 = mp_ioapics[apic].mpc_apicid;
1692
1693                 /*
1694                  * Read the right value from the MPC table and
1695                  * write it into the ID register.
1696                  */
1697                 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1698                                         mp_ioapics[apic].mpc_apicid);
1699
1700                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1701                 spin_lock_irqsave(&ioapic_lock, flags);
1702                 io_apic_write(apic, 0, reg_00.raw);
1703                 spin_unlock_irqrestore(&ioapic_lock, flags);
1704
1705                 /*
1706                  * Sanity check
1707                  */
1708                 spin_lock_irqsave(&ioapic_lock, flags);
1709                 reg_00.raw = io_apic_read(apic, 0);
1710                 spin_unlock_irqrestore(&ioapic_lock, flags);
1711                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1712                         panic("could not set ID!\n");
1713                 else
1714                         printk(" ok.\n");
1715         }
1716 }
1717 #else
1718 static void __init setup_ioapic_ids_from_mpc(void) { }
1719 #endif
1720
1721 /*
1722  * There is a nasty bug in some older SMP boards, their mptable lies
1723  * about the timer IRQ. We do the following to work around the situation:
1724  *
1725  *      - timer IRQ defaults to IO-APIC IRQ
1726  *      - if this function detects that timer IRQs are defunct, then we fall
1727  *        back to ISA timer IRQs
1728  */
1729 static int __init timer_irq_works(void)
1730 {
1731         unsigned long t1 = jiffies;
1732
1733         local_irq_enable();
1734         /* Let ten ticks pass... */
1735         mdelay((10 * 1000) / HZ);
1736
1737         /*
1738          * Expect a few ticks at least, to be sure some possible
1739          * glue logic does not lock up after one or two first
1740          * ticks in a non-ExtINT mode.  Also the local APIC
1741          * might have cached one ExtINT interrupt.  Finally, at
1742          * least one tick may be lost due to delays.
1743          */
1744         if (jiffies - t1 > 4)
1745                 return 1;
1746
1747         return 0;
1748 }
1749
1750 /*
1751  * In the SMP+IOAPIC case it might happen that there are an unspecified
1752  * number of pending IRQ events unhandled. These cases are very rare,
1753  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1754  * better to do it this way as thus we do not have to be aware of
1755  * 'pending' interrupts in the IRQ path, except at this point.
1756  */
1757 /*
1758  * Edge triggered needs to resend any interrupt
1759  * that was delayed but this is now handled in the device
1760  * independent code.
1761  */
1762
1763 /*
1764  * Starting up a edge-triggered IO-APIC interrupt is
1765  * nasty - we need to make sure that we get the edge.
1766  * If it is already asserted for some reason, we need
1767  * return 1 to indicate that is was pending.
1768  *
1769  * This is not complete - we should be able to fake
1770  * an edge even if it isn't on the 8259A...
1771  */
1772 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1773 {
1774         int was_pending = 0;
1775         unsigned long flags;
1776
1777         spin_lock_irqsave(&ioapic_lock, flags);
1778         if (irq < 16) {
1779                 disable_8259A_irq(irq);
1780                 if (i8259A_irq_pending(irq))
1781                         was_pending = 1;
1782         }
1783         __unmask_IO_APIC_irq(irq);
1784         spin_unlock_irqrestore(&ioapic_lock, flags);
1785
1786         return was_pending;
1787 }
1788
1789 /*
1790  * Once we have recorded IRQ_PENDING already, we can mask the
1791  * interrupt for real. This prevents IRQ storms from unhandled
1792  * devices.
1793  */
1794 static void ack_edge_ioapic_irq(unsigned int irq)
1795 {
1796         move_irq(irq);
1797         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1798                                         == (IRQ_PENDING | IRQ_DISABLED))
1799                 mask_IO_APIC_irq(irq);
1800         ack_APIC_irq();
1801 }
1802
1803 /*
1804  * Level triggered interrupts can just be masked,
1805  * and shutting down and starting up the interrupt
1806  * is the same as enabling and disabling them -- except
1807  * with a startup need to return a "was pending" value.
1808  *
1809  * Level triggered interrupts are special because we
1810  * do not touch any IO-APIC register while handling
1811  * them. We ack the APIC in the end-IRQ handler, not
1812  * in the start-IRQ-handler. Protection against reentrance
1813  * from the same interrupt is still provided, both by the
1814  * generic IRQ layer and by the fact that an unacked local
1815  * APIC does not accept IRQs.
1816  */
1817 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1818 {
1819         unmask_IO_APIC_irq(irq);
1820
1821         return 0; /* don't check for pending */
1822 }
1823
1824 static void end_level_ioapic_irq (unsigned int irq)
1825 {
1826         unsigned long v;
1827         int i;
1828
1829         move_irq(irq);
1830 /*
1831  * It appears there is an erratum which affects at least version 0x11
1832  * of I/O APIC (that's the 82093AA and cores integrated into various
1833  * chipsets).  Under certain conditions a level-triggered interrupt is
1834  * erroneously delivered as edge-triggered one but the respective IRR
1835  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1836  * message but it will never arrive and further interrupts are blocked
1837  * from the source.  The exact reason is so far unknown, but the
1838  * phenomenon was observed when two consecutive interrupt requests
1839  * from a given source get delivered to the same CPU and the source is
1840  * temporarily disabled in between.
1841  *
1842  * A workaround is to simulate an EOI message manually.  We achieve it
1843  * by setting the trigger mode to edge and then to level when the edge
1844  * trigger mode gets detected in the TMR of a local APIC for a
1845  * level-triggered interrupt.  We mask the source for the time of the
1846  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1847  * The idea is from Manfred Spraul.  --macro
1848  */
1849         i = IO_APIC_VECTOR(irq);
1850
1851         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1852
1853         ack_APIC_irq();
1854
1855         if (!(v & (1 << (i & 0x1f)))) {
1856 #ifdef APIC_MISMATCH_DEBUG
1857                 atomic_inc(&irq_mis_count);
1858 #endif
1859                 spin_lock(&ioapic_lock);
1860                 __mask_and_edge_IO_APIC_irq(irq);
1861                 __unmask_and_level_IO_APIC_irq(irq);
1862                 spin_unlock(&ioapic_lock);
1863         }
1864 }
1865
1866 #ifdef CONFIG_PCI_USE_VECTOR
1867 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1868 {
1869         int irq = vector_to_irq(vector);
1870
1871         return startup_edge_ioapic_irq(irq);
1872 }
1873
1874 static void ack_edge_ioapic_vector(unsigned int vector)
1875 {
1876         int irq = vector_to_irq(vector);
1877
1878         ack_edge_ioapic_irq(irq);
1879 }
1880
1881 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1882 {
1883         int irq = vector_to_irq(vector);
1884
1885         return startup_level_ioapic_irq (irq);
1886 }
1887
1888 static void end_level_ioapic_vector (unsigned int vector)
1889 {
1890         int irq = vector_to_irq(vector);
1891
1892         end_level_ioapic_irq(irq);
1893 }
1894
1895 static void mask_IO_APIC_vector (unsigned int vector)
1896 {
1897         int irq = vector_to_irq(vector);
1898
1899         mask_IO_APIC_irq(irq);
1900 }
1901
1902 static void unmask_IO_APIC_vector (unsigned int vector)
1903 {
1904         int irq = vector_to_irq(vector);
1905
1906         unmask_IO_APIC_irq(irq);
1907 }
1908
1909 static void set_ioapic_affinity_vector (unsigned int vector,
1910                                         cpumask_t cpu_mask)
1911 {
1912         int irq = vector_to_irq(vector);
1913
1914         set_ioapic_affinity_irq(irq, cpu_mask);
1915 }
1916 #endif
1917
1918 /*
1919  * Level and edge triggered IO-APIC interrupts need different handling,
1920  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1921  * handled with the level-triggered descriptor, but that one has slightly
1922  * more overhead. Level-triggered interrupts cannot be handled with the
1923  * edge-triggered handler, without risking IRQ storms and other ugly
1924  * races.
1925  */
1926 static struct hw_interrupt_type ioapic_edge_type = {
1927         .typename       = "IO-APIC-edge",
1928         .startup        = startup_edge_ioapic,
1929         .shutdown       = shutdown_edge_ioapic,
1930         .enable         = enable_edge_ioapic,
1931         .disable        = disable_edge_ioapic,
1932         .ack            = ack_edge_ioapic,
1933         .end            = end_edge_ioapic,
1934         .set_affinity   = set_ioapic_affinity,
1935 };
1936
1937 static struct hw_interrupt_type ioapic_level_type = {
1938         .typename       = "IO-APIC-level",
1939         .startup        = startup_level_ioapic,
1940         .shutdown       = shutdown_level_ioapic,
1941         .enable         = enable_level_ioapic,
1942         .disable        = disable_level_ioapic,
1943         .ack            = mask_and_ack_level_ioapic,
1944         .end            = end_level_ioapic,
1945         .set_affinity   = set_ioapic_affinity,
1946 };
1947
1948 static inline void init_IO_APIC_traps(void)
1949 {
1950         int irq;
1951
1952         /*
1953          * NOTE! The local APIC isn't very good at handling
1954          * multiple interrupts at the same interrupt level.
1955          * As the interrupt level is determined by taking the
1956          * vector number and shifting that right by 4, we
1957          * want to spread these out a bit so that they don't
1958          * all fall in the same interrupt level.
1959          *
1960          * Also, we've got to be careful not to trash gate
1961          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1962          */
1963         for (irq = 0; irq < NR_IRQS ; irq++) {
1964                 int tmp = irq;
1965                 if (use_pci_vector()) {
1966                         if (!platform_legacy_irq(tmp))
1967                                 if ((tmp = vector_to_irq(tmp)) == -1)
1968                                         continue;
1969                 }
1970                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1971                         /*
1972                          * Hmm.. We don't have an entry for this,
1973                          * so default to an old-fashioned 8259
1974                          * interrupt if we can..
1975                          */
1976                         if (irq < 16)
1977                                 make_8259A_irq(irq);
1978                         else
1979                                 /* Strange. Oh, well.. */
1980                                 irq_desc[irq].handler = &no_irq_type;
1981                 }
1982         }
1983 }
1984
1985 static void enable_lapic_irq (unsigned int irq)
1986 {
1987         unsigned long v;
1988
1989         v = apic_read(APIC_LVT0);
1990         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1991 }
1992
1993 static void disable_lapic_irq (unsigned int irq)
1994 {
1995         unsigned long v;
1996
1997         v = apic_read(APIC_LVT0);
1998         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1999 }
2000
2001 static void ack_lapic_irq (unsigned int irq)
2002 {
2003         ack_APIC_irq();
2004 }
2005
2006 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2007
2008 static struct hw_interrupt_type lapic_irq_type = {
2009         .typename       = "local-APIC-edge",
2010         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2011         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2012         .enable         = enable_lapic_irq,
2013         .disable        = disable_lapic_irq,
2014         .ack            = ack_lapic_irq,
2015         .end            = end_lapic_irq
2016 };
2017
2018 static void setup_nmi (void)
2019 {
2020         /*
2021          * Dirty trick to enable the NMI watchdog ...
2022          * We put the 8259A master into AEOI mode and
2023          * unmask on all local APICs LVT0 as NMI.
2024          *
2025          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2026          * is from Maciej W. Rozycki - so we do not have to EOI from
2027          * the NMI handler or the timer interrupt.
2028          */
2029         printk(KERN_INFO "activating NMI Watchdog ...");
2030
2031         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2032
2033         printk(" done.\n");
2034 }
2035
2036 /*
2037  * This looks a bit hackish but it's about the only one way of sending
2038  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2039  * not support the ExtINT mode, unfortunately.  We need to send these
2040  * cycles as some i82489DX-based boards have glue logic that keeps the
2041  * 8259A interrupt line asserted until INTA.  --macro
2042  */
2043 static inline void unlock_ExtINT_logic(void)
2044 {
2045         int pin, i;
2046         struct IO_APIC_route_entry entry0, entry1;
2047         unsigned char save_control, save_freq_select;
2048         unsigned long flags;
2049
2050         pin = find_isa_irq_pin(8, mp_INT);
2051         if (pin == -1)
2052                 return;
2053
2054         spin_lock_irqsave(&ioapic_lock, flags);
2055         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2056         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2057         spin_unlock_irqrestore(&ioapic_lock, flags);
2058         clear_IO_APIC_pin(0, pin);
2059
2060         memset(&entry1, 0, sizeof(entry1));
2061
2062         entry1.dest_mode = 0;                   /* physical delivery */
2063         entry1.mask = 0;                        /* unmask IRQ now */
2064         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2065         entry1.delivery_mode = dest_ExtINT;
2066         entry1.polarity = entry0.polarity;
2067         entry1.trigger = 0;
2068         entry1.vector = 0;
2069
2070         spin_lock_irqsave(&ioapic_lock, flags);
2071         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2072         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2073         spin_unlock_irqrestore(&ioapic_lock, flags);
2074
2075         save_control = CMOS_READ(RTC_CONTROL);
2076         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2077         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2078                    RTC_FREQ_SELECT);
2079         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2080
2081         i = 100;
2082         while (i-- > 0) {
2083                 mdelay(10);
2084                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2085                         i -= 10;
2086         }
2087
2088         CMOS_WRITE(save_control, RTC_CONTROL);
2089         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2090         clear_IO_APIC_pin(0, pin);
2091
2092         spin_lock_irqsave(&ioapic_lock, flags);
2093         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2094         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2095         spin_unlock_irqrestore(&ioapic_lock, flags);
2096 }
2097
2098 /*
2099  * This code may look a bit paranoid, but it's supposed to cooperate with
2100  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2101  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2102  * fanatically on his truly buggy board.
2103  */
2104 static inline void check_timer(void)
2105 {
2106         int pin1, pin2;
2107         int vector;
2108
2109         /*
2110          * get/set the timer IRQ vector:
2111          */
2112         disable_8259A_irq(0);
2113         vector = assign_irq_vector(0);
2114         set_intr_gate(vector, interrupt[0]);
2115
2116         /*
2117          * Subtle, code in do_timer_interrupt() expects an AEOI
2118          * mode for the 8259A whenever interrupts are routed
2119          * through I/O APICs.  Also IRQ0 has to be enabled in
2120          * the 8259A which implies the virtual wire has to be
2121          * disabled in the local APIC.
2122          */
2123         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2124         init_8259A(1);
2125         timer_ack = 1;
2126         enable_8259A_irq(0);
2127
2128         pin1 = find_isa_irq_pin(0, mp_INT);
2129         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2130
2131         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2132
2133         if (pin1 != -1) {
2134                 /*
2135                  * Ok, does IRQ0 through the IOAPIC work?
2136                  */
2137                 unmask_IO_APIC_irq(0);
2138                 if (timer_irq_works()) {
2139                         if (nmi_watchdog == NMI_IO_APIC) {
2140                                 disable_8259A_irq(0);
2141                                 setup_nmi();
2142                                 enable_8259A_irq(0);
2143                                 check_nmi_watchdog();
2144                         }
2145                         return;
2146                 }
2147                 clear_IO_APIC_pin(0, pin1);
2148                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2149         }
2150
2151         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2152         if (pin2 != -1) {
2153                 printk("\n..... (found pin %d) ...", pin2);
2154                 /*
2155                  * legacy devices should be connected to IO APIC #0
2156                  */
2157                 setup_ExtINT_IRQ0_pin(pin2, vector);
2158                 if (timer_irq_works()) {
2159                         printk("works.\n");
2160                         if (pin1 != -1)
2161                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2162                         else
2163                                 add_pin_to_irq(0, 0, pin2);
2164                         if (nmi_watchdog == NMI_IO_APIC) {
2165                                 setup_nmi();
2166                                 check_nmi_watchdog();
2167                         }
2168                         return;
2169                 }
2170                 /*
2171                  * Cleanup, just in case ...
2172                  */
2173                 clear_IO_APIC_pin(0, pin2);
2174         }
2175         printk(" failed.\n");
2176
2177         if (nmi_watchdog == NMI_IO_APIC) {
2178                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2179                 nmi_watchdog = 0;
2180         }
2181
2182         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2183
2184         disable_8259A_irq(0);
2185         irq_desc[0].handler = &lapic_irq_type;
2186         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2187         enable_8259A_irq(0);
2188
2189         if (timer_irq_works()) {
2190                 printk(" works.\n");
2191                 return;
2192         }
2193         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2194         printk(" failed.\n");
2195
2196         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2197
2198         timer_ack = 0;
2199         init_8259A(0);
2200         make_8259A_irq(0);
2201         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2202
2203         unlock_ExtINT_logic();
2204
2205         if (timer_irq_works()) {
2206                 printk(" works.\n");
2207                 return;
2208         }
2209         printk(" failed :(.\n");
2210         panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
2211 }
2212
2213 /*
2214  *
2215  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2216  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2217  *   Linux doesn't really care, as it's not actually used
2218  *   for any interrupt handling anyway.
2219  */
2220 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2221
2222 void __init setup_IO_APIC(void)
2223 {
2224         enable_IO_APIC();
2225
2226         if (acpi_ioapic)
2227                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2228         else
2229                 io_apic_irqs = ~PIC_IRQS;
2230
2231         printk("ENABLING IO-APIC IRQs\n");
2232
2233         /*
2234          * Set up IO-APIC IRQ routing.
2235          */
2236         if (!acpi_ioapic)
2237                 setup_ioapic_ids_from_mpc();
2238         sync_Arb_IDs();
2239         setup_IO_APIC_irqs();
2240         init_IO_APIC_traps();
2241         check_timer();
2242         if (!acpi_ioapic)
2243                 print_IO_APIC();
2244 }
2245
2246 /*
2247  *      Called after all the initialization is done. If we didnt find any
2248  *      APIC bugs then we can allow the modify fast path
2249  */
2250
2251 static int __init io_apic_bug_finalize(void)
2252 {
2253         if(sis_apic_bug == -1)
2254                 sis_apic_bug = 0;
2255         return 0;
2256 }
2257
2258 late_initcall(io_apic_bug_finalize);
2259
2260 /* --------------------------------------------------------------------------
2261                           ACPI-based IOAPIC Configuration
2262    -------------------------------------------------------------------------- */
2263
2264 #ifdef CONFIG_ACPI_BOOT
2265
2266 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2267 {
2268         union IO_APIC_reg_00 reg_00;
2269         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2270         physid_mask_t tmp;
2271         unsigned long flags;
2272         int i = 0;
2273
2274         /*
2275          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2276          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2277          * supports up to 16 on one shared APIC bus.
2278          *
2279          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2280          *      advantage of new APIC bus architecture.
2281          */
2282
2283         if (physids_empty(apic_id_map))
2284                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2285
2286         spin_lock_irqsave(&ioapic_lock, flags);
2287         reg_00.raw = io_apic_read(ioapic, 0);
2288         spin_unlock_irqrestore(&ioapic_lock, flags);
2289
2290         if (apic_id >= get_physical_broadcast()) {
2291                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2292                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2293                 apic_id = reg_00.bits.ID;
2294         }
2295
2296         /*
2297          * Every APIC in a system must have a unique ID or we get lots of nice
2298          * 'stuck on smp_invalidate_needed IPI wait' messages.
2299          */
2300         if (check_apicid_used(apic_id_map, apic_id)) {
2301
2302                 for (i = 0; i < get_physical_broadcast(); i++) {
2303                         if (!check_apicid_used(apic_id_map, i))
2304                                 break;
2305                 }
2306
2307                 if (i == get_physical_broadcast())
2308                         panic("Max apic_id exceeded!\n");
2309
2310                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2311                         "trying %d\n", ioapic, apic_id, i);
2312
2313                 apic_id = i;
2314         }
2315
2316         tmp = apicid_to_cpu_present(apic_id);
2317         physids_or(apic_id_map, apic_id_map, tmp);
2318
2319         if (reg_00.bits.ID != apic_id) {
2320                 reg_00.bits.ID = apic_id;
2321
2322                 spin_lock_irqsave(&ioapic_lock, flags);
2323                 io_apic_write(ioapic, 0, reg_00.raw);
2324                 reg_00.raw = io_apic_read(ioapic, 0);
2325                 spin_unlock_irqrestore(&ioapic_lock, flags);
2326
2327                 /* Sanity check */
2328                 if (reg_00.bits.ID != apic_id)
2329                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2330         }
2331
2332         printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2333
2334         return apic_id;
2335 }
2336
2337
2338 int __init io_apic_get_version (int ioapic)
2339 {
2340         union IO_APIC_reg_01    reg_01;
2341         unsigned long flags;
2342
2343         spin_lock_irqsave(&ioapic_lock, flags);
2344         reg_01.raw = io_apic_read(ioapic, 1);
2345         spin_unlock_irqrestore(&ioapic_lock, flags);
2346
2347         return reg_01.bits.version;
2348 }
2349
2350
2351 int __init io_apic_get_redir_entries (int ioapic)
2352 {
2353         union IO_APIC_reg_01    reg_01;
2354         unsigned long flags;
2355
2356         spin_lock_irqsave(&ioapic_lock, flags);
2357         reg_01.raw = io_apic_read(ioapic, 1);
2358         spin_unlock_irqrestore(&ioapic_lock, flags);
2359
2360         return reg_01.bits.entries;
2361 }
2362
2363
2364 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2365 {
2366         struct IO_APIC_route_entry entry;
2367         unsigned long flags;
2368
2369         if (!IO_APIC_IRQ(irq)) {
2370                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2371                         ioapic);
2372                 return -EINVAL;
2373         }
2374
2375         /*
2376          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2377          * Note that we mask (disable) IRQs now -- these get enabled when the
2378          * corresponding device driver registers for this IRQ.
2379          */
2380
2381         memset(&entry,0,sizeof(entry));
2382
2383         entry.delivery_mode = INT_DELIVERY_MODE;
2384         entry.dest_mode = INT_DEST_MODE;
2385         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2386         entry.trigger = edge_level;
2387         entry.polarity = active_high_low;
2388         entry.mask  = 1;
2389
2390         /*
2391          * IRQs < 16 are already in the irq_2_pin[] map
2392          */
2393         if (irq >= 16)
2394                 add_pin_to_irq(irq, ioapic, pin);
2395
2396         entry.vector = assign_irq_vector(irq);
2397
2398         Dprintk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2399                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2400                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
2401
2402         if (use_pci_vector() && !platform_legacy_irq(irq))
2403                 irq = IO_APIC_VECTOR(irq);
2404         if (edge_level) {
2405                 irq_desc[irq].handler = &ioapic_level_type;
2406         } else {
2407                 irq_desc[irq].handler = &ioapic_edge_type;
2408         }
2409
2410         set_intr_gate(entry.vector, interrupt[irq]);
2411
2412         if (!ioapic && (irq < 16))
2413                 disable_8259A_irq(irq);
2414
2415         spin_lock_irqsave(&ioapic_lock, flags);
2416         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2417         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2418         spin_unlock_irqrestore(&ioapic_lock, flags);
2419
2420         return 0;
2421 }
2422
2423 #endif /*CONFIG_ACPI_BOOT*/