2 * machine_kexec.c - handle transition of Linux booting another kernel
3 * Copyright (C) 2002-2004 Eric Biederman <ebiederm@xmission.com>
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
10 #include <linux/kexec.h>
11 #include <linux/delay.h>
12 #include <asm/pgtable.h>
13 #include <asm/pgalloc.h>
14 #include <asm/tlbflush.h>
15 #include <asm/mmu_context.h>
18 #include <asm/cpufeature.h>
19 #include <asm/crash_dump.h>
21 static inline unsigned long read_cr3(void)
24 asm volatile("movl %%cr3,%0": "=r"(cr3));
28 #define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
30 #define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
31 #define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
32 #define L2_ATTR (_PAGE_PRESENT)
34 #define LEVEL0_SIZE (1UL << 12UL)
36 #ifndef CONFIG_X86_PAE
37 #define LEVEL1_SIZE (1UL << 22UL)
38 static u32 pgtable_level1[1024] PAGE_ALIGNED;
40 static void identity_map_page(unsigned long address)
42 unsigned long level1_index, level2_index;
45 /* Find the current page table */
46 pgtable_level2 = __va(read_cr3());
48 /* Find the indexes of the physical address to identity map */
49 level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
50 level2_index = address / LEVEL1_SIZE;
52 /* Identity map the page table entry */
53 pgtable_level1[level1_index] = address | L0_ATTR;
54 pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
56 /* Flush the tlb so the new mapping takes effect.
57 * Global tlb entries are not flushed but that is not an issue.
59 load_cr3(pgtable_level2);
63 #define LEVEL1_SIZE (1UL << 21UL)
64 #define LEVEL2_SIZE (1UL << 30UL)
65 static u64 pgtable_level1[512] PAGE_ALIGNED;
66 static u64 pgtable_level2[512] PAGE_ALIGNED;
68 static void identity_map_page(unsigned long address)
70 unsigned long level1_index, level2_index, level3_index;
73 /* Find the current page table */
74 pgtable_level3 = __va(read_cr3());
76 /* Find the indexes of the physical address to identity map */
77 level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
78 level2_index = (address % LEVEL2_SIZE)/LEVEL1_SIZE;
79 level3_index = address / LEVEL2_SIZE;
81 /* Identity map the page table entry */
82 pgtable_level1[level1_index] = address | L0_ATTR;
83 pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
84 set_64bit(&pgtable_level3[level3_index], __pa(pgtable_level2) | L2_ATTR);
86 /* Flush the tlb so the new mapping takes effect.
87 * Global tlb entries are not flushed but that is not an issue.
89 load_cr3(pgtable_level3);
94 static void set_idt(void *newidt, __u16 limit)
96 unsigned char curidt[6];
98 /* ia32 supports unaliged loads & stores */
99 (*(__u16 *)(curidt)) = limit;
100 (*(__u32 *)(curidt +2)) = (unsigned long)(newidt);
102 __asm__ __volatile__ (
109 static void set_gdt(void *newgdt, __u16 limit)
111 unsigned char curgdt[6];
113 /* ia32 supports unaligned loads & stores */
114 (*(__u16 *)(curgdt)) = limit;
115 (*(__u32 *)(curgdt +2)) = (unsigned long)(newgdt);
117 __asm__ __volatile__ (
123 static void load_segments(void)
126 #define STR(X) __STR(X)
128 __asm__ __volatile__ (
129 "\tljmp $"STR(__KERNEL_CS)",$1f\n"
131 "\tmovl $"STR(__KERNEL_DS)",%eax\n"
142 typedef asmlinkage void (*relocate_new_kernel_t)(
143 unsigned long indirection_page, unsigned long reboot_code_buffer,
144 unsigned long start_address, unsigned int has_pae);
146 const extern unsigned char relocate_new_kernel[];
147 extern void relocate_new_kernel_end(void);
148 const extern unsigned int relocate_new_kernel_size;
151 * Do what every setup is needed on image and the
152 * reboot code buffer to allow us to avoid allocations
153 * later. Currently nothing.
155 int machine_kexec_prepare(struct kimage *image)
160 void machine_kexec_cleanup(struct kimage *image)
165 * We are going to do a memory preserving reboot. So, we copy over the
166 * first 640k of memory into a backup location. Though the second kernel
167 * boots from a different location, it still requires the first 640k.
170 void __crash_relocate_mem(unsigned long backup_addr, unsigned long backup_size)
172 unsigned long pfn, pfn_max;
173 void *src_addr, *dest_addr;
176 pfn_max = backup_size >> PAGE_SHIFT;
177 for (pfn = 0; pfn < pfn_max; pfn++) {
178 src_addr = phys_to_virt(pfn << PAGE_SHIFT);
179 dest_addr = backup_addr + src_addr;
182 page = pfn_to_page(pfn);
183 if (PageReserved(page))
184 copy_page(dest_addr, src_addr);
189 * Do not allocate memory (or fail in any way) in machine_kexec().
190 * We are past the point of no return, committed to rebooting now.
192 void machine_kexec(struct kimage *image)
194 unsigned long indirection_page;
195 unsigned long reboot_code_buffer;
196 relocate_new_kernel_t rnk;
198 /* Interrupts aren't acceptable while we reboot */
201 /* Compute some offsets */
202 reboot_code_buffer = page_to_pfn(image->control_code_page) << PAGE_SHIFT;
203 indirection_page = image->head & PAGE_MASK;
205 /* Set up an identity mapping for the reboot_code_buffer */
206 identity_map_page(reboot_code_buffer);
209 memcpy((void *)reboot_code_buffer, relocate_new_kernel, relocate_new_kernel_size);
211 /* The segment registers are funny things, they are
212 * automatically loaded from a table, in memory wherever you
213 * set them to a specific selector, but this table is never
214 * accessed again you set the segment to a different selector.
216 * The more common model is are caches where the behide
217 * the scenes work is done, but is also dropped at arbitrary
220 * I take advantage of this here by force loading the
221 * segments, before I zap the gdt with an invalid value.
224 /* The gdt & idt are now invalid.
225 * If you want to load them you must set up your own idt & gdt.
227 set_gdt(phys_to_virt(0),0);
228 set_idt(phys_to_virt(0),0);
231 rnk = (relocate_new_kernel_t) reboot_code_buffer;
232 (*rnk)(indirection_page, reboot_code_buffer, image->start, cpu_has_pae);