2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/acpi.h>
20 #include <linux/delay.h>
21 #include <linux/config.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/mc146818rtc.h>
30 #include <asm/mpspec.h>
31 #include <asm/pgalloc.h>
32 #include <asm/io_apic.h>
34 #include <mach_apic.h>
35 #include <mach_mpparse.h>
36 #include <bios_ebda.h>
38 /* Have we found an MP table */
40 unsigned int __initdata maxcpus = NR_CPUS;
43 * Various Linux-internal data structures created from the
46 int apic_version [MAX_APICS];
47 int mp_bus_id_to_type [MAX_MP_BUSSES];
48 int mp_bus_id_to_node [MAX_MP_BUSSES];
49 int mp_bus_id_to_local [MAX_MP_BUSSES];
50 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
51 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
52 int mp_current_pci_id;
54 /* I/O APIC entries */
55 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
57 /* # of MP IRQ source entries */
58 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
60 /* MP IRQ source entries */
66 unsigned long mp_lapic_addr;
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 unsigned int boot_cpu_logical_apicid = -1U;
71 /* Internal processor count */
72 static unsigned int __initdata num_processors;
74 /* Bitmask of physically existing CPUs */
75 physid_mask_t phys_cpu_present_map;
77 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
80 * Intel MP BIOS table parsing routines:
85 * Checksum an MP configuration block.
88 static int __init mpf_checksum(unsigned char *mp, int len)
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
104 static int mpc_record;
105 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
107 void __init MP_processor_info (struct mpc_config_processor *m)
112 if (!(m->mpc_cpuflag & CPU_ENABLED))
115 apicid = mpc_apic_id(m, translation_table[mpc_record]);
117 if (m->mpc_featureflag&(1<<0))
118 Dprintk(" Floating point unit present.\n");
119 if (m->mpc_featureflag&(1<<7))
120 Dprintk(" Machine Exception supported.\n");
121 if (m->mpc_featureflag&(1<<8))
122 Dprintk(" 64 bit compare & exchange supported.\n");
123 if (m->mpc_featureflag&(1<<9))
124 Dprintk(" Internal APIC present.\n");
125 if (m->mpc_featureflag&(1<<11))
126 Dprintk(" SEP present.\n");
127 if (m->mpc_featureflag&(1<<12))
128 Dprintk(" MTRR present.\n");
129 if (m->mpc_featureflag&(1<<13))
130 Dprintk(" PGE present.\n");
131 if (m->mpc_featureflag&(1<<14))
132 Dprintk(" MCA present.\n");
133 if (m->mpc_featureflag&(1<<15))
134 Dprintk(" CMOV present.\n");
135 if (m->mpc_featureflag&(1<<16))
136 Dprintk(" PAT present.\n");
137 if (m->mpc_featureflag&(1<<17))
138 Dprintk(" PSE present.\n");
139 if (m->mpc_featureflag&(1<<18))
140 Dprintk(" PSN present.\n");
141 if (m->mpc_featureflag&(1<<19))
142 Dprintk(" Cache Line Flush Instruction present.\n");
144 if (m->mpc_featureflag&(1<<21))
145 Dprintk(" Debug Trace and EMON Store present.\n");
146 if (m->mpc_featureflag&(1<<22))
147 Dprintk(" ACPI Thermal Throttle Registers present.\n");
148 if (m->mpc_featureflag&(1<<23))
149 Dprintk(" MMX present.\n");
150 if (m->mpc_featureflag&(1<<24))
151 Dprintk(" FXSR present.\n");
152 if (m->mpc_featureflag&(1<<25))
153 Dprintk(" XMM present.\n");
154 if (m->mpc_featureflag&(1<<26))
155 Dprintk(" Willamette New Instructions present.\n");
156 if (m->mpc_featureflag&(1<<27))
157 Dprintk(" Self Snoop present.\n");
158 if (m->mpc_featureflag&(1<<28))
159 Dprintk(" HT present.\n");
160 if (m->mpc_featureflag&(1<<29))
161 Dprintk(" Thermal Monitor present.\n");
162 /* 30, 31 Reserved */
165 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
166 Dprintk(" Bootup CPU\n");
167 boot_cpu_physical_apicid = m->mpc_apicid;
168 boot_cpu_logical_apicid = apicid;
171 if (num_processors >= NR_CPUS) {
172 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
173 " Processor ignored.\n", NR_CPUS);
177 if (num_processors >= maxcpus) {
178 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
179 " Processor ignored.\n", maxcpus);
184 if (MAX_APICS - m->mpc_apicid <= 0) {
185 printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
186 m->mpc_apicid, MAX_APICS);
190 ver = m->mpc_apicver;
192 tmp = apicid_to_cpu_present(apicid);
193 physids_or(phys_cpu_present_map, phys_cpu_present_map, tmp);
199 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
202 apic_version[m->mpc_apicid] = ver;
203 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
206 static void __init MP_bus_info (struct mpc_config_bus *m)
210 memcpy(str, m->mpc_bustype, 6);
213 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
215 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
216 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
217 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
218 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
219 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
220 mpc_oem_pci_bus(m, translation_table[mpc_record]);
221 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
222 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
224 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
225 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
226 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
227 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
229 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
233 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
235 if (!(m->mpc_flags & MPC_APIC_USABLE))
238 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
239 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
240 if (nr_ioapics >= MAX_IO_APICS) {
241 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
242 MAX_IO_APICS, nr_ioapics);
243 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
245 if (!m->mpc_apicaddr) {
246 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
247 " found in MP table, skipping!\n");
250 mp_ioapics[nr_ioapics] = *m;
254 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
256 mp_irqs [mp_irq_entries] = *m;
257 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
258 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
259 m->mpc_irqtype, m->mpc_irqflag & 3,
260 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
261 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
262 if (++mp_irq_entries == MAX_IRQ_SOURCES)
263 panic("Max # of irq sources exceeded!!\n");
266 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
268 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
269 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
270 m->mpc_irqtype, m->mpc_irqflag & 3,
271 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
272 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
274 * Well it seems all SMP boards in existence
275 * use ExtINT/LVT1 == LINT0 and
276 * NMI/LVT2 == LINT1 - the following check
277 * will show us if this assumptions is false.
278 * Until then we do not have to add baggage.
280 if ((m->mpc_irqtype == mp_ExtINT) &&
281 (m->mpc_destapiclint != 0))
283 if ((m->mpc_irqtype == mp_NMI) &&
284 (m->mpc_destapiclint != 1))
288 #ifdef CONFIG_X86_NUMAQ
289 static void __init MP_translation_info (struct mpc_config_translation *m)
291 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
293 if (mpc_record >= MAX_MPC_ENTRY)
294 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
296 translation_table[mpc_record] = m; /* stash this for later */
297 if (m->trans_quad+1 > numnodes)
298 numnodes = m->trans_quad+1;
302 * Read/parse the MPC oem tables
305 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
306 unsigned short oemsize)
308 int count = sizeof (*oemtable); /* the header size */
309 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
312 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
313 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
315 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
316 oemtable->oem_signature[0],
317 oemtable->oem_signature[1],
318 oemtable->oem_signature[2],
319 oemtable->oem_signature[3]);
322 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
324 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
327 while (count < oemtable->oem_length) {
331 struct mpc_config_translation *m=
332 (struct mpc_config_translation *)oemptr;
333 MP_translation_info(m);
334 oemptr += sizeof(*m);
341 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
348 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
351 if (strncmp(oem, "IBM NUMA", 8))
352 printk("Warning! May not be a NUMA-Q system!\n");
354 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
357 #endif /* CONFIG_X86_NUMAQ */
363 static int __init smp_read_mpc(struct mp_config_table *mpc)
367 int count=sizeof(*mpc);
368 unsigned char *mpt=((unsigned char *)mpc)+count;
370 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
371 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
372 *(u32 *)mpc->mpc_signature);
375 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
376 printk(KERN_ERR "SMP mptable: checksum error!\n");
379 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
380 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
384 if (!mpc->mpc_lapic) {
385 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
388 memcpy(oem,mpc->mpc_oem,8);
390 printk(KERN_INFO "OEM ID: %s ",oem);
392 memcpy(str,mpc->mpc_productid,12);
394 printk("Product ID: %s ",str);
396 mps_oem_check(mpc, oem, str);
398 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
401 * Save the local APIC address (it might be non-default) -- but only
402 * if we're not using ACPI.
405 mp_lapic_addr = mpc->mpc_lapic;
408 * Now process the configuration blocks.
411 while (count < mpc->mpc_length) {
415 struct mpc_config_processor *m=
416 (struct mpc_config_processor *)mpt;
417 /* ACPI may have already provided this data */
419 MP_processor_info(m);
426 struct mpc_config_bus *m=
427 (struct mpc_config_bus *)mpt;
435 struct mpc_config_ioapic *m=
436 (struct mpc_config_ioapic *)mpt;
444 struct mpc_config_intsrc *m=
445 (struct mpc_config_intsrc *)mpt;
454 struct mpc_config_lintsrc *m=
455 (struct mpc_config_lintsrc *)mpt;
463 count = mpc->mpc_length;
469 clustered_apic_check();
471 printk(KERN_ERR "SMP mptable: no processors registered!\n");
472 return num_processors;
475 static int __init ELCR_trigger(unsigned int irq)
479 port = 0x4d0 + (irq >> 3);
480 return (inb(port) >> (irq & 7)) & 1;
483 static void __init construct_default_ioirq_mptable(int mpc_default_type)
485 struct mpc_config_intsrc intsrc;
487 int ELCR_fallback = 0;
489 intsrc.mpc_type = MP_INTSRC;
490 intsrc.mpc_irqflag = 0; /* conforming */
491 intsrc.mpc_srcbus = 0;
492 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
494 intsrc.mpc_irqtype = mp_INT;
497 * If true, we have an ISA/PCI system with no IRQ entries
498 * in the MP table. To prevent the PCI interrupts from being set up
499 * incorrectly, we try to use the ELCR. The sanity check to see if
500 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
501 * never be level sensitive, so we simply see if the ELCR agrees.
502 * If it does, we assume it's valid.
504 if (mpc_default_type == 5) {
505 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
507 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
508 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
510 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
515 for (i = 0; i < 16; i++) {
516 switch (mpc_default_type) {
518 if (i == 0 || i == 13)
519 continue; /* IRQ0 & IRQ13 not connected */
523 continue; /* IRQ2 is never connected */
528 * If the ELCR indicates a level-sensitive interrupt, we
529 * copy that information over to the MP table in the
530 * irqflag field (level sensitive, active high polarity).
533 intsrc.mpc_irqflag = 13;
535 intsrc.mpc_irqflag = 0;
538 intsrc.mpc_srcbusirq = i;
539 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
540 MP_intsrc_info(&intsrc);
543 intsrc.mpc_irqtype = mp_ExtINT;
544 intsrc.mpc_srcbusirq = 0;
545 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
546 MP_intsrc_info(&intsrc);
549 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
551 struct mpc_config_processor processor;
552 struct mpc_config_bus bus;
553 struct mpc_config_ioapic ioapic;
554 struct mpc_config_lintsrc lintsrc;
555 int linttypes[2] = { mp_ExtINT, mp_NMI };
559 * local APIC has default address
561 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
564 * 2 CPUs, numbered 0 & 1.
566 processor.mpc_type = MP_PROCESSOR;
567 /* Either an integrated APIC or a discrete 82489DX. */
568 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
569 processor.mpc_cpuflag = CPU_ENABLED;
570 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
571 (boot_cpu_data.x86_model << 4) |
572 boot_cpu_data.x86_mask;
573 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
574 processor.mpc_reserved[0] = 0;
575 processor.mpc_reserved[1] = 0;
576 for (i = 0; i < 2; i++) {
577 processor.mpc_apicid = i;
578 MP_processor_info(&processor);
581 bus.mpc_type = MP_BUS;
583 switch (mpc_default_type) {
586 printk(KERN_ERR "Unknown standard configuration %d\n",
591 memcpy(bus.mpc_bustype, "ISA ", 6);
596 memcpy(bus.mpc_bustype, "EISA ", 6);
600 memcpy(bus.mpc_bustype, "MCA ", 6);
603 if (mpc_default_type > 4) {
605 memcpy(bus.mpc_bustype, "PCI ", 6);
609 ioapic.mpc_type = MP_IOAPIC;
610 ioapic.mpc_apicid = 2;
611 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
612 ioapic.mpc_flags = MPC_APIC_USABLE;
613 ioapic.mpc_apicaddr = 0xFEC00000;
614 MP_ioapic_info(&ioapic);
617 * We set up most of the low 16 IO-APIC pins according to MPS rules.
619 construct_default_ioirq_mptable(mpc_default_type);
621 lintsrc.mpc_type = MP_LINTSRC;
622 lintsrc.mpc_irqflag = 0; /* conforming */
623 lintsrc.mpc_srcbusid = 0;
624 lintsrc.mpc_srcbusirq = 0;
625 lintsrc.mpc_destapic = MP_APIC_ALL;
626 for (i = 0; i < 2; i++) {
627 lintsrc.mpc_irqtype = linttypes[i];
628 lintsrc.mpc_destapiclint = i;
629 MP_lintsrc_info(&lintsrc);
633 static struct intel_mp_floating *mpf_found;
636 * Scan the memory blocks for an SMP configuration block.
638 void __init get_smp_config (void)
640 struct intel_mp_floating *mpf = mpf_found;
643 * ACPI may be used to obtain the entire SMP configuration or just to
644 * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
645 * ACPI supports both logical (e.g. Hyper-Threading) and physical
646 * processors, where MPS only supports physical.
648 if (acpi_lapic && acpi_ioapic) {
649 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
653 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
655 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
656 if (mpf->mpf_feature2 & (1<<7)) {
657 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
660 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
665 * Now see if we need to read further.
667 if (mpf->mpf_feature1 != 0) {
669 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
670 construct_default_ISA_mptable(mpf->mpf_feature1);
672 } else if (mpf->mpf_physptr) {
675 * Read the physical hardware table. Anything here will
676 * override the defaults.
678 if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
679 smp_found_config = 0;
680 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
681 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
685 * If there are no explicit MP IRQ entries, then we are
686 * broken. We set up most of the low 16 IO-APIC pins to
687 * ISA defaults and hope it will work.
689 if (!mp_irq_entries) {
690 struct mpc_config_bus bus;
692 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
694 bus.mpc_type = MP_BUS;
696 memcpy(bus.mpc_bustype, "ISA ", 6);
699 construct_default_ioirq_mptable(0);
705 printk(KERN_INFO "Processors: %d\n", num_processors);
707 * Only use the first configuration found.
711 static int __init smp_scan_config (unsigned long base, unsigned long length)
713 unsigned long *bp = phys_to_virt(base);
714 struct intel_mp_floating *mpf;
716 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
717 if (sizeof(*mpf) != 16)
718 printk("Error: MPF size\n");
721 mpf = (struct intel_mp_floating *)bp;
722 if ((*bp == SMP_MAGIC_IDENT) &&
723 (mpf->mpf_length == 1) &&
724 !mpf_checksum((unsigned char *)bp, 16) &&
725 ((mpf->mpf_specification == 1)
726 || (mpf->mpf_specification == 4)) ) {
728 smp_found_config = 1;
729 printk(KERN_INFO "found SMP MP-table at %08lx\n",
731 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
732 if (mpf->mpf_physptr) {
734 * We cannot access to MPC table to compute
735 * table size yet, as only few megabytes from
736 * the bottom is mapped now.
737 * PC-9800's MPC table places on the very last
738 * of physical memory; so that simply reserving
739 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
740 * in reserve_bootmem.
742 unsigned long size = PAGE_SIZE;
743 unsigned long end = max_low_pfn * PAGE_SIZE;
744 if (mpf->mpf_physptr + size > end)
745 size = end - mpf->mpf_physptr;
746 reserve_bootmem(mpf->mpf_physptr, size);
758 void __init find_smp_config (void)
760 unsigned int address;
763 * FIXME: Linux assumes you have 640K of base ram..
764 * this continues the error...
766 * 1) Scan the bottom 1K for a signature
767 * 2) Scan the top 1K of base RAM
768 * 3) Scan the 64K of bios
770 if (smp_scan_config(0x0,0x400) ||
771 smp_scan_config(639*0x400,0x400) ||
772 smp_scan_config(0xF0000,0x10000))
775 * If it is an SMP machine we should know now, unless the
776 * configuration is in an EISA/MCA bus machine with an
777 * extended bios data area.
779 * there is a real-mode segmented pointer pointing to the
780 * 4K EBDA area at 0x40E, calculate and scan it here.
782 * NOTE! There are Linux loaders that will corrupt the EBDA
783 * area, and as such this kind of SMP config may be less
784 * trustworthy, simply because the SMP table may have been
785 * stomped on during early boot. These loaders are buggy and
788 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
791 address = get_bios_ebda();
793 smp_scan_config(address, 0x400);
797 /* --------------------------------------------------------------------------
798 ACPI-based MP Configuration
799 -------------------------------------------------------------------------- */
801 #ifdef CONFIG_ACPI_BOOT
803 void __init mp_register_lapic_address (
806 mp_lapic_addr = (unsigned long) address;
808 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
810 if (boot_cpu_physical_apicid == -1U)
811 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
813 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
817 void __init mp_register_lapic (
821 struct mpc_config_processor processor;
824 if (MAX_APICS - id <= 0) {
825 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
830 if (id == boot_cpu_physical_apicid)
833 processor.mpc_type = MP_PROCESSOR;
834 processor.mpc_apicid = id;
835 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
836 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
837 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
838 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
839 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
840 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
841 processor.mpc_reserved[0] = 0;
842 processor.mpc_reserved[1] = 0;
844 MP_processor_info(&processor);
847 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
850 #define MP_MAX_IOAPIC_PIN 127
852 struct mp_ioapic_routing {
856 u32 pin_programmed[4];
857 } mp_ioapic_routing[MAX_IO_APICS];
860 static int __init mp_find_ioapic (
865 /* Find the IOAPIC that manages this GSI. */
866 for (i = 0; i < nr_ioapics; i++) {
867 if ((gsi >= mp_ioapic_routing[i].gsi_base)
868 && (gsi <= mp_ioapic_routing[i].gsi_end))
872 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
878 void __init mp_register_ioapic (
885 if (nr_ioapics >= MAX_IO_APICS) {
886 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
887 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
888 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
891 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
892 " found in MADT table, skipping!\n");
898 mp_ioapics[idx].mpc_type = MP_IOAPIC;
899 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
900 mp_ioapics[idx].mpc_apicaddr = address;
902 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
903 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
904 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
907 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
908 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
910 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
911 mp_ioapic_routing[idx].gsi_base = gsi_base;
912 mp_ioapic_routing[idx].gsi_end = gsi_base +
913 io_apic_get_redir_entries(idx);
915 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
916 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
917 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
918 mp_ioapic_routing[idx].gsi_base,
919 mp_ioapic_routing[idx].gsi_end);
925 void __init mp_override_legacy_irq (
931 struct mpc_config_intsrc intsrc;
936 * Convert 'gsi' to 'ioapic.pin'.
938 ioapic = mp_find_ioapic(gsi);
941 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
944 * TBD: This check is for faulty timer entries, where the override
945 * erroneously sets the trigger to level, resulting in a HUGE
946 * increase of timer interrupts!
948 if ((bus_irq == 0) && (trigger == 3))
951 intsrc.mpc_type = MP_INTSRC;
952 intsrc.mpc_irqtype = mp_INT;
953 intsrc.mpc_irqflag = (trigger << 2) | polarity;
954 intsrc.mpc_srcbus = MP_ISA_BUS;
955 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
956 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
957 intsrc.mpc_dstirq = pin; /* INTIN# */
959 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
960 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
961 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
962 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
964 mp_irqs[mp_irq_entries] = intsrc;
965 if (++mp_irq_entries == MAX_IRQ_SOURCES)
966 panic("Max # of irq sources exceeded!\n");
972 void __init mp_config_acpi_legacy_irqs (void)
974 struct mpc_config_intsrc intsrc;
979 * Fabricate the legacy ISA bus (bus #31).
981 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
982 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
985 * Locate the IOAPIC that manages the ISA IRQs (0-15).
987 ioapic = mp_find_ioapic(0);
991 intsrc.mpc_type = MP_INTSRC;
992 intsrc.mpc_irqflag = 0; /* Conforming */
993 intsrc.mpc_srcbus = MP_ISA_BUS;
994 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
997 * Use the default configuration for the IRQs 0-15. Unless
998 * overriden by (MADT) interrupt source override entries.
1000 for (i = 0; i < 16; i++) {
1003 for (idx = 0; idx < mp_irq_entries; idx++)
1004 if (mp_irqs[idx].mpc_srcbus == MP_ISA_BUS &&
1005 (mp_irqs[idx].mpc_srcbusirq == i ||
1006 mp_irqs[idx].mpc_dstirq == i))
1009 if (idx != mp_irq_entries)
1010 continue; /* IRQ already used */
1012 intsrc.mpc_irqtype = mp_INT;
1013 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1014 intsrc.mpc_dstirq = i;
1016 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1017 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1018 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1019 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1022 mp_irqs[mp_irq_entries] = intsrc;
1023 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1024 panic("Max # of irq sources exceeded!\n");
1028 extern FADT_DESCRIPTOR acpi_fadt;
1030 #ifdef CONFIG_ACPI_PCI
1032 int (*platform_rename_gsi)(int ioapic, int gsi);
1034 void __init mp_parse_prt (void)
1036 struct list_head *node = NULL;
1037 struct acpi_prt_entry *entry = NULL;
1043 int active_high_low = 0;
1046 * Parsing through the PCI Interrupt Routing Table (PRT) and program
1047 * routing for all entries.
1049 list_for_each(node, &acpi_prt.entries) {
1050 entry = list_entry(node, struct acpi_prt_entry, node);
1052 /* Need to get gsi for dynamic entry */
1053 if (entry->link.handle) {
1054 gsi = acpi_pci_link_get_irq(entry->link.handle, entry->link.index, &edge_level, &active_high_low);
1059 /* Hardwired GSI. Assume PCI standard settings */
1060 gsi = entry->link.index;
1062 active_high_low = 1;
1065 /* Don't set up the ACPI SCI because it's already set up */
1066 if (acpi_fadt.sci_int == gsi) {
1067 /* we still need to set entry's irq */
1068 acpi_gsi_to_irq(gsi, &entry->irq);
1072 ioapic = mp_find_ioapic(gsi);
1075 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1077 if (platform_rename_gsi)
1078 gsi = platform_rename_gsi(ioapic, gsi);
1081 * Avoid pin reprogramming. PRTs typically include entries
1082 * with redundant pin->gsi mappings (but unique PCI devices);
1083 * we only only program the IOAPIC on the first.
1085 bit = ioapic_pin % 32;
1086 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1088 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1089 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1093 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1094 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1095 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1096 acpi_gsi_to_irq(gsi, &entry->irq);
1100 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1102 if (!io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, edge_level, active_high_low)) {
1103 acpi_gsi_to_irq(gsi, &entry->irq);
1105 printk(KERN_DEBUG "%02x:%02x:%02x[%c] -> %d-%d -> IRQ %d %s %s\n",
1106 entry->id.segment, entry->id.bus,
1107 entry->id.device, ('A' + entry->pin),
1108 mp_ioapic_routing[ioapic].apic_id, ioapic_pin,
1109 entry->irq, edge_level ? "level" : "edge",
1110 active_high_low ? "low" : "high");
1118 #endif /*CONFIG_ACPI_PCI*/
1119 #endif /*CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER*/
1120 #endif /*CONFIG_ACPI_BOOT*/