2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
26 #include <linux/nmi.h>
27 #include <linux/sysdev.h>
31 #include <asm/mpspec.h>
34 unsigned int nmi_watchdog = NMI_NONE;
35 static unsigned int nmi_hz = HZ;
36 unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
37 extern void show_registers(struct pt_regs *regs);
40 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
41 * - it may be reserved by some other driver, or not
42 * - when not reserved by some other driver, it may be used for
43 * the NMI watchdog, or not
45 * This is maintained separately from nmi_active because the NMI
46 * watchdog may also be driven from the I/O APIC timer.
48 static spinlock_t lapic_nmi_owner_lock = SPIN_LOCK_UNLOCKED;
49 static unsigned int lapic_nmi_owner;
50 #define LAPIC_NMI_WATCHDOG (1<<0)
51 #define LAPIC_NMI_RESERVED (1<<1)
54 * +1: the lapic NMI watchdog is active, but can be disabled
55 * 0: the lapic NMI watchdog has not been set up, and cannot
57 * -1: the lapic NMI watchdog is disabled, but can be enabled
61 #define K7_EVNTSEL_ENABLE (1 << 22)
62 #define K7_EVNTSEL_INT (1 << 20)
63 #define K7_EVNTSEL_OS (1 << 17)
64 #define K7_EVNTSEL_USR (1 << 16)
65 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
66 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
68 #define P6_EVNTSEL0_ENABLE (1 << 22)
69 #define P6_EVNTSEL_INT (1 << 20)
70 #define P6_EVNTSEL_OS (1 << 17)
71 #define P6_EVNTSEL_USR (1 << 16)
72 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
73 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
75 #define MSR_P4_MISC_ENABLE 0x1A0
76 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
77 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
78 #define MSR_P4_PERFCTR0 0x300
79 #define MSR_P4_CCCR0 0x360
80 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
81 #define P4_ESCR_OS (1<<3)
82 #define P4_ESCR_USR (1<<2)
83 #define P4_CCCR_OVF_PMI (1<<26)
84 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
85 #define P4_CCCR_COMPLEMENT (1<<19)
86 #define P4_CCCR_COMPARE (1<<18)
87 #define P4_CCCR_REQUIRED (3<<16)
88 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
89 #define P4_CCCR_ENABLE (1<<12)
90 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
91 CRU_ESCR0 (with any non-null event selector) through a complemented
92 max threshold. [IA32-Vol3, Section 14.9.9] */
93 #define MSR_P4_IQ_COUNTER0 0x30C
94 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
95 #define P4_NMI_IQ_CCCR0 \
96 (P4_CCCR_OVF_PMI|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
97 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
99 int __init check_nmi_watchdog (void)
101 unsigned int prev_nmi_count[NR_CPUS];
104 printk(KERN_INFO "testing NMI watchdog ... ");
106 for (cpu = 0; cpu < NR_CPUS; cpu++)
107 prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
109 mdelay((10*1000)/nmi_hz); // wait 10 ticks
111 /* FIXME: Only boot CPU is online at this stage. Check CPUs
113 for (cpu = 0; cpu < NR_CPUS; cpu++) {
114 if (!cpu_online(cpu))
116 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
117 printk("CPU#%d: NMI appears to be stuck!\n", cpu);
119 lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
125 /* now that we know it works we can reduce NMI frequency to
126 something more reasonable; makes a difference in some configs */
127 if (nmi_watchdog == NMI_LOCAL_APIC)
133 static int __init setup_nmi_watchdog(char *str)
137 get_option(&str, &nmi);
139 if (nmi >= NMI_INVALID)
144 * If any other x86 CPU has a local APIC, then
145 * please test the NMI stuff there and send me the
146 * missing bits. Right now Intel P6/P4 and AMD K7 only.
148 if ((nmi == NMI_LOCAL_APIC) &&
149 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
150 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
152 if ((nmi == NMI_LOCAL_APIC) &&
153 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
154 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
157 * We can enable the IO-APIC watchdog
160 if (nmi == NMI_IO_APIC) {
167 __setup("nmi_watchdog=", setup_nmi_watchdog);
169 static void disable_lapic_nmi_watchdog(void)
173 switch (boot_cpu_data.x86_vendor) {
175 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
177 case X86_VENDOR_INTEL:
178 switch (boot_cpu_data.x86) {
180 if (boot_cpu_data.x86_model > 0xd)
183 wrmsr(MSR_P6_EVNTSEL0, 0, 0);
186 if (boot_cpu_data.x86_model > 0x3)
189 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
190 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
196 /* tell do_nmi() and others that we're not active any more */
200 static void enable_lapic_nmi_watchdog(void)
202 if (nmi_active < 0) {
203 nmi_watchdog = NMI_LOCAL_APIC;
204 setup_apic_nmi_watchdog();
208 int reserve_lapic_nmi(void)
210 unsigned int old_owner;
212 spin_lock(&lapic_nmi_owner_lock);
213 old_owner = lapic_nmi_owner;
214 lapic_nmi_owner |= LAPIC_NMI_RESERVED;
215 spin_unlock(&lapic_nmi_owner_lock);
216 if (old_owner & LAPIC_NMI_RESERVED)
218 if (old_owner & LAPIC_NMI_WATCHDOG)
219 disable_lapic_nmi_watchdog();
223 void release_lapic_nmi(void)
225 unsigned int new_owner;
227 spin_lock(&lapic_nmi_owner_lock);
228 new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
229 lapic_nmi_owner = new_owner;
230 spin_unlock(&lapic_nmi_owner_lock);
231 if (new_owner & LAPIC_NMI_WATCHDOG)
232 enable_lapic_nmi_watchdog();
235 void disable_timer_nmi_watchdog(void)
237 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
240 unset_nmi_callback();
242 nmi_watchdog = NMI_NONE;
245 void enable_timer_nmi_watchdog(void)
247 if (nmi_active < 0) {
248 nmi_watchdog = NMI_IO_APIC;
249 touch_nmi_watchdog();
256 static int nmi_pm_active; /* nmi_active before suspend */
258 static int lapic_nmi_suspend(struct sys_device *dev, u32 state)
260 nmi_pm_active = nmi_active;
261 disable_lapic_nmi_watchdog();
265 static int lapic_nmi_resume(struct sys_device *dev)
267 if (nmi_pm_active > 0)
268 enable_lapic_nmi_watchdog();
273 static struct sysdev_class nmi_sysclass = {
274 set_kset_name("lapic_nmi"),
275 .resume = lapic_nmi_resume,
276 .suspend = lapic_nmi_suspend,
279 static struct sys_device device_lapic_nmi = {
281 .cls = &nmi_sysclass,
284 static int __init init_lapic_nmi_sysfs(void)
288 if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
291 error = sysdev_class_register(&nmi_sysclass);
293 error = sysdev_register(&device_lapic_nmi);
296 /* must come after the local APIC's device_initcall() */
297 late_initcall(init_lapic_nmi_sysfs);
299 #endif /* CONFIG_PM */
302 * Activate the NMI watchdog via the local APIC.
303 * Original code written by Keith Owens.
306 static void clear_msr_range(unsigned int base, unsigned int n)
310 for(i = 0; i < n; ++i)
314 static void setup_k7_watchdog(void)
316 unsigned int evntsel;
318 nmi_perfctr_msr = MSR_K7_PERFCTR0;
320 clear_msr_range(MSR_K7_EVNTSEL0, 4);
321 clear_msr_range(MSR_K7_PERFCTR0, 4);
323 evntsel = K7_EVNTSEL_INT
328 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
329 Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
330 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
331 apic_write(APIC_LVTPC, APIC_DM_NMI);
332 evntsel |= K7_EVNTSEL_ENABLE;
333 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
336 static void setup_p6_watchdog(void)
338 unsigned int evntsel;
340 nmi_perfctr_msr = MSR_P6_PERFCTR0;
342 clear_msr_range(MSR_P6_EVNTSEL0, 2);
343 clear_msr_range(MSR_P6_PERFCTR0, 2);
345 evntsel = P6_EVNTSEL_INT
350 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
351 Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
352 wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
353 apic_write(APIC_LVTPC, APIC_DM_NMI);
354 evntsel |= P6_EVNTSEL0_ENABLE;
355 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
358 static int setup_p4_watchdog(void)
360 unsigned int misc_enable, dummy;
362 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
363 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
366 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
368 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
369 clear_msr_range(0x3F1, 2);
370 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
371 docs doesn't fully define it, so leave it alone for now. */
372 clear_msr_range(0x3A0, 31);
373 clear_msr_range(0x3C0, 6);
374 clear_msr_range(0x3C8, 6);
375 clear_msr_range(0x3E0, 2);
376 clear_msr_range(MSR_P4_CCCR0, 18);
377 clear_msr_range(MSR_P4_PERFCTR0, 18);
379 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
380 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
381 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
382 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
383 apic_write(APIC_LVTPC, APIC_DM_NMI);
384 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
388 void setup_apic_nmi_watchdog (void)
390 switch (boot_cpu_data.x86_vendor) {
392 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
396 case X86_VENDOR_INTEL:
397 switch (boot_cpu_data.x86) {
399 if (boot_cpu_data.x86_model > 0xd)
405 if (boot_cpu_data.x86_model > 0x3)
408 if (!setup_p4_watchdog())
418 lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
422 static spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED;
425 * the best way to detect whether a CPU has a 'hard lockup' problem
426 * is to check it's local APIC timer IRQ counts. If they are not
427 * changing then that CPU has some problem.
429 * as these watchdog NMI IRQs are generated on every CPU, we only
430 * have to check the current processor.
432 * since NMIs don't listen to _any_ locks, we have to be extremely
433 * careful not to rely on unsafe variables. The printk might lock
434 * up though, so we have to break up any console locks first ...
435 * [when there will be more tty-related locks, break them up
440 last_irq_sums [NR_CPUS],
441 alert_counter [NR_CPUS];
443 void touch_nmi_watchdog (void)
448 * Just reset the alert counters, (other CPUs might be
449 * spinning on locks we hold):
451 for (i = 0; i < NR_CPUS; i++)
452 alert_counter[i] = 0;
455 void nmi_watchdog_tick (struct pt_regs * regs)
459 * Since current_thread_info()-> is always on the stack, and we
460 * always switch the stack NMI-atomically, it's safe to use
461 * smp_processor_id().
463 int sum, cpu = smp_processor_id();
465 sum = irq_stat[cpu].apic_timer_irqs;
467 if (last_irq_sums[cpu] == sum) {
469 * Ayiee, looks like this CPU is stuck ...
470 * wait a few IRQs (5 seconds) before doing the oops ...
472 alert_counter[cpu]++;
473 if (alert_counter[cpu] == 5*nmi_hz) {
474 spin_lock(&nmi_print_lock);
476 * We are in trouble anyway, lets at least try
477 * to get a message out.
480 printk("NMI Watchdog detected LOCKUP on CPU%d, eip %08lx, registers:\n", cpu, regs->eip);
481 show_registers(regs);
482 printk("console shuts up ...\n");
484 spin_unlock(&nmi_print_lock);
489 last_irq_sums[cpu] = sum;
490 alert_counter[cpu] = 0;
492 if (nmi_perfctr_msr) {
493 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
496 * - An overflown perfctr will assert its interrupt
497 * until the OVF flag in its CCCR is cleared.
498 * - LVTPC is masked on interrupt and must be
499 * unmasked by the LVTPC handler.
501 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
502 apic_write(APIC_LVTPC, APIC_DM_NMI);
504 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
505 /* Only P6 based Pentium M need to re-unmask
506 * the apic vector but it doesn't hurt
507 * other P6 variant */
508 apic_write(APIC_LVTPC, APIC_DM_NMI);
510 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
514 EXPORT_SYMBOL(nmi_active);
515 EXPORT_SYMBOL(nmi_watchdog);
516 EXPORT_SYMBOL(reserve_lapic_nmi);
517 EXPORT_SYMBOL(release_lapic_nmi);
518 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
519 EXPORT_SYMBOL(enable_timer_nmi_watchdog);