1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/config.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/smp_lock.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/bootmem.h>
23 #include <linux/completion.h>
25 #include <asm/voyager.h>
28 #include <asm/pgalloc.h>
29 #include <asm/tlbflush.h>
30 #include <asm/arch_hooks.h>
32 #include <linux/irq.h>
34 /* TLB state -- visible externally, indexed physically */
35 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
37 /* CPU IRQ affinity -- set to all ones initially */
38 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
40 /* Set when the idlers are all forked - Set in main.c but not actually
41 * used by any other parts of the kernel */
42 int smp_threads_ready = 0;
44 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
45 * indexed physically */
46 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
48 /* physical ID of the CPU used to boot the system */
49 unsigned char boot_cpu_id;
51 /* The memory line addresses for the Quad CPIs */
52 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
54 /* The masks for the Extended VIC processors, filled in by cat_init */
55 __u32 voyager_extended_vic_processors = 0;
57 /* Masks for the extended Quad processors which cannot be VIC booted */
58 __u32 voyager_allowed_boot_processors = 0;
60 /* The mask for the Quad Processors (both extended and non-extended) */
61 __u32 voyager_quad_processors = 0;
63 /* Total count of live CPUs, used in process.c to display
64 * the CPU information and in irq.c for the per CPU irq
65 * activity count. Finally exported by i386_ksyms.c */
66 static int voyager_extended_cpus = 1;
68 /* Have we found an SMP box - used by time.c to do the profiling
69 interrupt for timeslicing; do not set to 1 until the per CPU timer
70 interrupt is active */
71 int smp_found_config = 0;
73 /* Used for the invalidate map that's also checked in the spinlock */
74 static volatile unsigned long smp_invalidate_needed;
76 /* Bitmask of currently online CPUs - used by setup.c for
77 /proc/cpuinfo, visible externally but still physical */
78 cpumask_t cpu_online_map = CPU_MASK_NONE;
80 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
81 * by scheduler but indexed physically */
82 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
84 /* estimate of time used to flush the SMP-local cache - used in
85 * processor affinity calculations */
86 cycles_t cacheflush_time = 0;
88 /* cache decay ticks for scheduler---a fairly useless quantity for the
89 voyager system with its odd affinity and huge L3 cache */
90 unsigned long cache_decay_ticks = 20;
93 /* The internal functions */
94 static void send_CPI(__u32 cpuset, __u8 cpi);
95 static void ack_CPI(__u8 cpi);
96 static int ack_QIC_CPI(__u8 cpi);
97 static void ack_special_QIC_CPI(__u8 cpi);
98 static void ack_VIC_CPI(__u8 cpi);
99 static void send_CPI_allbutself(__u8 cpi);
100 static void enable_vic_irq(unsigned int irq);
101 static void disable_vic_irq(unsigned int irq);
102 static unsigned int startup_vic_irq(unsigned int irq);
103 static void enable_local_vic_irq(unsigned int irq);
104 static void disable_local_vic_irq(unsigned int irq);
105 static void before_handle_vic_irq(unsigned int irq);
106 static void after_handle_vic_irq(unsigned int irq);
107 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
108 static void ack_vic_irq(unsigned int irq);
109 static void vic_enable_cpi(void);
110 static void do_boot_cpu(__u8 cpuid);
111 static void do_quad_bootstrap(void);
112 static inline void wrapper_smp_local_timer_interrupt(struct pt_regs *);
114 int hard_smp_processor_id(void);
116 /* Inline functions */
118 send_one_QIC_CPI(__u8 cpu, __u8 cpi)
120 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
121 (smp_processor_id() << 16) + cpi;
125 send_QIC_CPI(__u32 cpuset, __u8 cpi)
129 for_each_online_cpu(cpu) {
130 if(cpuset & (1<<cpu)) {
132 if(!cpu_isset(cpu, cpu_online_map))
133 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
135 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
141 send_one_CPI(__u8 cpu, __u8 cpi)
143 if(voyager_quad_processors & (1<<cpu))
144 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
146 send_CPI(1<<cpu, cpi);
150 send_CPI_allbutself(__u8 cpi)
152 __u8 cpu = smp_processor_id();
153 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
160 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
161 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
165 is_cpu_extended(void)
167 __u8 cpu = hard_smp_processor_id();
169 return(voyager_extended_vic_processors & (1<<cpu));
173 is_cpu_vic_boot(void)
175 __u8 cpu = hard_smp_processor_id();
177 return(voyager_extended_vic_processors
178 & voyager_allowed_boot_processors & (1<<cpu));
186 case VIC_CPU_BOOT_CPI:
187 if(is_cpu_quad() && !is_cpu_vic_boot())
194 /* These are slightly strange. Even on the Quad card,
195 * They are vectored as VIC CPIs */
197 ack_special_QIC_CPI(cpi);
202 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
207 /* local variables */
209 /* The VIC IRQ descriptors -- these look almost identical to the
210 * 8259 IRQs except that masks and things must be kept per processor
212 static struct hw_interrupt_type vic_irq_type = {
214 startup_vic_irq, /* startup */
215 disable_vic_irq, /* shutdown */
216 enable_vic_irq, /* enable */
217 disable_vic_irq, /* disable */
218 before_handle_vic_irq, /* ack */
219 after_handle_vic_irq, /* end */
220 set_vic_irq_affinity, /* affinity */
223 /* used to count up as CPUs are brought on line (starts at 0) */
224 static int cpucount = 0;
226 /* steal a page from the bottom of memory for the trampoline and
227 * squirrel its address away here. This will be in kernel virtual
229 static __u32 trampoline_base;
231 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
232 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
233 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
234 static DEFINE_PER_CPU(int, prof_counter) = 1;
236 /* the map used to check if a CPU has booted */
237 static __u32 cpu_booted_map;
239 /* the synchronize flag used to hold all secondary CPUs spinning in
240 * a tight loop until the boot sequence is ready for them */
241 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
243 /* This is for the new dynamic CPU boot code */
244 cpumask_t cpu_callin_map = CPU_MASK_NONE;
245 cpumask_t cpu_callout_map = CPU_MASK_NONE;
247 /* The per processor IRQ masks (these are usually kept in sync) */
248 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
250 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
251 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
253 /* Lock for enable/disable of VIC interrupts */
254 static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
256 /* The boot processor is correctly set up in PC mode when it
257 * comes up, but the secondaries need their master/slave 8259
258 * pairs initializing correctly */
260 /* Interrupt counters (per cpu) and total - used to try to
261 * even up the interrupt handling routines */
262 static long vic_intr_total = 0;
263 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
264 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
266 /* Since we can only use CPI0, we fake all the other CPIs */
267 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
269 /* debugging routine to read the isr of the cpu's pic */
276 isr = inb(0xa0) << 8;
287 /* not a quad, no setup */
290 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
291 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
293 if(is_cpu_extended()) {
294 /* the QIC duplicate of the VIC base register */
295 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
296 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
298 /* FIXME: should set up the QIC timer and memory parity
299 * error vectors here */
306 outb(1, VIC_REDIRECT_REGISTER_1);
307 /* clear the claim registers for dynamic routing */
308 outb(0, VIC_CLAIM_REGISTER_0);
309 outb(0, VIC_CLAIM_REGISTER_1);
311 outb(0, VIC_PRIORITY_REGISTER);
312 /* Set the Primary and Secondary Microchannel vector
313 * bases to be the same as the ordinary interrupts
315 * FIXME: This would be more efficient using separate
317 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
318 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
319 /* Now initiallise the master PIC belonging to this CPU by
320 * sending the four ICWs */
322 /* ICW1: level triggered, ICW4 needed */
325 /* ICW2: vector base */
326 outb(FIRST_EXTERNAL_VECTOR, 0x21);
328 /* ICW3: slave at line 2 */
331 /* ICW4: 8086 mode */
334 /* now the same for the slave PIC */
336 /* ICW1: level trigger, ICW4 needed */
339 /* ICW2: slave vector base */
340 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
345 /* ICW4: 8086 mode */
350 do_quad_bootstrap(void)
352 if(is_cpu_quad() && is_cpu_vic_boot()) {
355 __u8 cpuid = hard_smp_processor_id();
357 local_irq_save(flags);
359 for(i = 0; i<4; i++) {
360 /* FIXME: this would be >>3 &0x7 on the 32 way */
361 if(((cpuid >> 2) & 0x03) == i)
362 /* don't lower our own mask! */
365 /* masquerade as local Quad CPU */
366 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
367 /* enable the startup CPI */
368 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
370 outb(0, QIC_PROCESSOR_ID);
372 local_irq_restore(flags);
377 /* Set up all the basic stuff: read the SMP config and make all the
378 * SMP information reflect only the boot cpu. All others will be
379 * brought on-line later. */
381 find_smp_config(void)
385 boot_cpu_id = hard_smp_processor_id();
387 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
389 /* initialize the CPU structures (moved from smp_boot_cpus) */
390 for(i=0; i<NR_CPUS; i++) {
391 cpu_irq_affinity[i] = ~0;
393 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
395 /* The boot CPU must be extended */
396 voyager_extended_vic_processors = 1<<boot_cpu_id;
397 /* initially, all of the first 8 cpu's can boot */
398 voyager_allowed_boot_processors = 0xff;
399 /* set up everything for just this CPU, we can alter
400 * this as we start the other CPUs later */
401 /* now get the CPU disposition from the extended CMOS */
402 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
403 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
404 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
405 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
406 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
407 /* Here we set up the VIC to enable SMP */
408 /* enable the CPIs by writing the base vector to their register */
409 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
410 outb(1, VIC_REDIRECT_REGISTER_1);
411 /* set the claim registers for static routing --- Boot CPU gets
412 * all interrupts untill all other CPUs started */
413 outb(0xff, VIC_CLAIM_REGISTER_0);
414 outb(0xff, VIC_CLAIM_REGISTER_1);
415 /* Set the Primary and Secondary Microchannel vector
416 * bases to be the same as the ordinary interrupts
418 * FIXME: This would be more efficient using separate
420 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
421 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
423 /* Finally tell the firmware that we're driving */
424 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
425 VOYAGER_SUS_IN_CONTROL_PORT);
427 current_thread_info()->cpu = boot_cpu_id;
431 * The bootstrap kernel entry code has set these up. Save them
432 * for a given CPU, id is physical */
434 smp_store_cpu_info(int id)
436 struct cpuinfo_x86 *c=&cpu_data[id];
443 /* set up the trampoline and return the physical address of the code */
445 setup_trampoline(void)
447 /* these two are global symbols in trampoline.S */
448 extern __u8 trampoline_end[];
449 extern __u8 trampoline_data[];
451 memcpy((__u8 *)trampoline_base, trampoline_data,
452 trampoline_end - trampoline_data);
453 return virt_to_phys((__u8 *)trampoline_base);
456 /* Routine initially called when a non-boot CPU is brought online */
458 start_secondary(void *unused)
460 __u8 cpuid = hard_smp_processor_id();
461 /* external functions not defined in the headers */
462 extern void calibrate_delay(void);
466 /* OK, we're in the routine */
467 ack_CPI(VIC_CPU_BOOT_CPI);
469 /* setup the 8259 master slave pair belonging to this CPU ---
470 * we won't actually receive any until the boot CPU
471 * relinquishes it's static routing mask */
476 if(is_cpu_quad() && !is_cpu_vic_boot()) {
477 /* clear the boot CPI */
480 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
481 printk("read dummy %d\n", dummy);
484 /* lower the mask to receive CPIs */
487 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
489 /* enable interrupts */
492 /* get our bogomips */
495 /* save our processor parameters */
496 smp_store_cpu_info(cpuid);
498 /* if we're a quad, we may need to bootstrap other CPUs */
501 /* FIXME: this is rather a poor hack to prevent the CPU
502 * activating softirqs while it's supposed to be waiting for
503 * permission to proceed. Without this, the new per CPU stuff
504 * in the softirqs will fail */
506 cpu_set(cpuid, cpu_callin_map);
508 /* signal that we're done */
511 while (!cpu_isset(cpuid, smp_commenced_mask))
517 cpu_set(cpuid, cpu_online_map);
523 /* Routine to kick start the given CPU and wait for it to report ready
524 * (or timeout in startup). When this routine returns, the requested
525 * CPU is either fully running and configured or known to be dead.
527 * We call this routine sequentially 1 CPU at a time, so no need for
531 do_boot_cpu(__u8 cpu)
533 struct task_struct *idle;
536 int quad_boot = (1<<cpu) & voyager_quad_processors
537 & ~( voyager_extended_vic_processors
538 & voyager_allowed_boot_processors);
540 /* For the 486, we can't use the 4Mb page table trick, so
541 * must map a region of memory */
544 unsigned long *page_table_copies = (unsigned long *)
545 __get_free_page(GFP_KERNEL);
547 pgd_t orig_swapper_pg_dir0;
549 /* This is an area in head.S which was used to set up the
550 * initial kernel stack. We need to alter this to give the
551 * booting CPU a new stack (taken from its idle process) */
556 /* This is the format of the CPI IDT gate (in real mode) which
557 * we're hijacking to boot the CPU */
566 __u32 *hijack_vector;
567 __u32 start_phys_address = setup_trampoline();
569 /* There's a clever trick to this: The linux trampoline is
570 * compiled to begin at absolute location zero, so make the
571 * address zero but have the data segment selector compensate
572 * for the actual address */
573 hijack_source.idt.Offset = start_phys_address & 0x000F;
574 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
577 idle = fork_idle(cpu);
579 panic("failed fork for CPU%d", cpu);
580 idle->thread.eip = (unsigned long) start_secondary;
581 /* init_tasks (in sched.c) is indexed logically */
582 stack_start.esp = (void *) idle->thread.esp;
586 /* Note: Don't modify initial ss override */
587 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
588 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
589 hijack_source.idt.Offset, stack_start.esp));
590 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
591 * (so that the booting CPU can find start_32 */
592 orig_swapper_pg_dir0 = swapper_pg_dir[0];
594 if(page_table_copies == NULL)
595 panic("No free memory for 486 page tables\n");
596 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
597 page_table_copies[i] = (i * PAGE_SIZE)
598 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
600 ((unsigned long *)swapper_pg_dir)[0] =
601 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
602 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
604 ((unsigned long *)swapper_pg_dir)[0] =
605 (virt_to_phys(pg0) & PAGE_MASK)
606 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
610 printk("CPU %d: non extended Quad boot\n", cpu);
611 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
612 *hijack_vector = hijack_source.val;
614 printk("CPU%d: extended VIC boot\n", cpu);
615 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
616 *hijack_vector = hijack_source.val;
617 /* VIC errata, may also receive interrupt at this address */
618 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
619 *hijack_vector = hijack_source.val;
621 /* All non-boot CPUs start with interrupts fully masked. Need
622 * to lower the mask of the CPI we're about to send. We do
623 * this in the VIC by masquerading as the processor we're
624 * about to boot and lowering its interrupt mask */
625 local_irq_save(flags);
627 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
629 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
630 /* here we're altering registers belonging to `cpu' */
632 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
633 /* now go back to our original identity */
634 outb(boot_cpu_id, VIC_PROCESSOR_ID);
636 /* and boot the CPU */
638 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
641 local_irq_restore(flags);
643 /* now wait for it to become ready (or timeout) */
644 for(timeout = 0; timeout < 50000; timeout++) {
649 /* reset the page table */
650 swapper_pg_dir[0] = orig_swapper_pg_dir0;
653 free_page((unsigned long)page_table_copies);
656 if (cpu_booted_map) {
657 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
658 cpu, smp_processor_id()));
660 printk("CPU%d: ", cpu);
661 print_cpu_info(&cpu_data[cpu]);
663 cpu_set(cpu, cpu_callout_map);
666 printk("CPU%d FAILED TO BOOT: ", cpu);
667 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
670 printk("Not responding.\n");
681 /* CAT BUS initialisation must be done after the memory */
682 /* FIXME: The L4 has a catbus too, it just needs to be
683 * accessed in a totally different way */
684 if(voyager_level == 5) {
687 /* now that the cat has probed the Voyager System Bus, sanity
688 * check the cpu map */
689 if( ((voyager_quad_processors | voyager_extended_vic_processors)
690 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
692 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
694 } else if(voyager_level == 4)
695 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
697 /* this sets up the idle task to run on the current cpu */
698 voyager_extended_cpus = 1;
699 /* Remove the global_irq_holder setting, it triggers a BUG() on
700 * schedule at the moment */
701 //global_irq_holder = boot_cpu_id;
703 /* FIXME: Need to do something about this but currently only works
704 * on CPUs with a tsc which none of mine have.
705 smp_tune_scheduling();
707 smp_store_cpu_info(boot_cpu_id);
708 printk("CPU%d: ", boot_cpu_id);
709 print_cpu_info(&cpu_data[boot_cpu_id]);
712 /* booting on a Quad CPU */
713 printk("VOYAGER SMP: Boot CPU is Quad\n");
718 /* enable our own CPIs */
721 cpu_set(boot_cpu_id, cpu_online_map);
722 cpu_set(boot_cpu_id, cpu_callout_map);
724 /* loop over all the extended VIC CPUs and boot them. The
725 * Quad CPUs must be bootstrapped by their extended VIC cpu */
726 for(i = 0; i < NR_CPUS; i++) {
727 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
730 /* This udelay seems to be needed for the Quad boots
731 * don't remove unless you know what you're doing */
734 /* we could compute the total bogomips here, but why bother?,
735 * Code added from smpboot.c */
737 unsigned long bogosum = 0;
738 for (i = 0; i < NR_CPUS; i++)
739 if (cpu_isset(i, cpu_online_map))
740 bogosum += cpu_data[i].loops_per_jiffy;
741 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
744 (bogosum/(5000/HZ))%100);
746 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
747 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
748 /* that's it, switch to symmetric mode */
749 outb(0, VIC_PRIORITY_REGISTER);
750 outb(0, VIC_CLAIM_REGISTER_0);
751 outb(0, VIC_CLAIM_REGISTER_1);
753 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
756 /* Reload the secondary CPUs task structure (this function does not
759 initialize_secondary(void)
763 set_current(hard_get_current());
767 * We don't actually need to load the full TSS,
768 * basically just the stack pointer and the eip.
775 :"r" (current->thread.esp),"r" (current->thread.eip));
778 /* handle a Voyager SYS_INT -- If we don't, the base board will
781 * System interrupts occur because some problem was detected on the
782 * various busses. To find out what you have to probe all the
783 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
785 smp_vic_sys_interrupt(struct pt_regs *regs)
787 ack_CPI(VIC_SYS_INT);
788 printk("Voyager SYSTEM INTERRUPT\n");
791 /* Handle a voyager CMN_INT; These interrupts occur either because of
792 * a system status change or because a single bit memory error
793 * occurred. FIXME: At the moment, ignore all this. */
795 smp_vic_cmn_interrupt(struct pt_regs *regs)
797 static __u8 in_cmn_int = 0;
798 static DEFINE_SPINLOCK(cmn_int_lock);
800 /* common ints are broadcast, so make sure we only do this once */
801 _raw_spin_lock(&cmn_int_lock);
806 _raw_spin_unlock(&cmn_int_lock);
808 VDEBUG(("Voyager COMMON INTERRUPT\n"));
810 if(voyager_level == 5)
811 voyager_cat_do_common_interrupt();
813 _raw_spin_lock(&cmn_int_lock);
816 _raw_spin_unlock(&cmn_int_lock);
817 ack_CPI(VIC_CMN_INT);
821 * Reschedule call back. Nothing to do, all the work is done
822 * automatically when we return from the interrupt. */
824 smp_reschedule_interrupt(void)
829 static struct mm_struct * flush_mm;
830 static unsigned long flush_va;
831 static DEFINE_SPINLOCK(tlbstate_lock);
832 #define FLUSH_ALL 0xffffffff
835 * We cannot call mmdrop() because we are in interrupt context,
836 * instead update mm->cpu_vm_mask.
838 * We need to reload %cr3 since the page tables may be going
839 * away from under us..
842 leave_mm (unsigned long cpu)
844 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
846 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
847 load_cr3(swapper_pg_dir);
852 * Invalidate call-back
855 smp_invalidate_interrupt(void)
857 __u8 cpu = smp_processor_id();
859 if (!test_bit(cpu, &smp_invalidate_needed))
861 /* This will flood messages. Don't uncomment unless you see
862 * Problems with cross cpu invalidation
863 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
864 smp_processor_id()));
867 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
868 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
869 if (flush_va == FLUSH_ALL)
872 __flush_tlb_one(flush_va);
876 smp_mb__before_clear_bit();
877 clear_bit(cpu, &smp_invalidate_needed);
878 smp_mb__after_clear_bit();
881 /* All the new flush operations for 2.4 */
884 /* This routine is called with a physical cpu mask */
886 flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
893 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
895 if (cpumask & (1 << smp_processor_id()))
900 spin_lock(&tlbstate_lock);
904 atomic_set_mask(cpumask, &smp_invalidate_needed);
906 * We have to send the CPI only to
909 send_CPI(cpumask, VIC_INVALIDATE_CPI);
911 while (smp_invalidate_needed) {
914 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
919 /* Uncomment only to debug invalidation problems
920 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
925 spin_unlock(&tlbstate_lock);
929 flush_tlb_current_task(void)
931 struct mm_struct *mm = current->mm;
932 unsigned long cpu_mask;
936 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
939 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
946 flush_tlb_mm (struct mm_struct * mm)
948 unsigned long cpu_mask;
952 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
954 if (current->active_mm == mm) {
958 leave_mm(smp_processor_id());
961 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
966 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
968 struct mm_struct *mm = vma->vm_mm;
969 unsigned long cpu_mask;
973 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
974 if (current->active_mm == mm) {
978 leave_mm(smp_processor_id());
982 flush_tlb_others(cpu_mask, mm, va);
987 /* enable the requested IRQs */
989 smp_enable_irq_interrupt(void)
992 __u8 cpu = get_cpu();
994 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
995 vic_irq_enable_mask[cpu]));
997 spin_lock(&vic_irq_lock);
998 for(irq = 0; irq < 16; irq++) {
999 if(vic_irq_enable_mask[cpu] & (1<<irq))
1000 enable_local_vic_irq(irq);
1002 vic_irq_enable_mask[cpu] = 0;
1003 spin_unlock(&vic_irq_lock);
1005 put_cpu_no_resched();
1009 * CPU halt call-back
1012 smp_stop_cpu_function(void *dummy)
1014 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1015 cpu_clear(smp_processor_id(), cpu_online_map);
1016 local_irq_disable();
1021 static DEFINE_SPINLOCK(call_lock);
1023 struct call_data_struct {
1024 void (*func) (void *info);
1026 volatile unsigned long started;
1027 volatile unsigned long finished;
1031 static struct call_data_struct * call_data;
1033 /* execute a thread on a new CPU. The function to be called must be
1034 * previously set up. This is used to schedule a function for
1035 * execution on all CPU's - set up the function then broadcast a
1036 * function_interrupt CPI to come here on each CPU */
1038 smp_call_function_interrupt(void)
1040 void (*func) (void *info) = call_data->func;
1041 void *info = call_data->info;
1042 /* must take copy of wait because call_data may be replaced
1043 * unless the function is waiting for us to finish */
1044 int wait = call_data->wait;
1045 __u8 cpu = smp_processor_id();
1048 * Notify initiating CPU that I've grabbed the data and am
1049 * about to execute the function
1052 if(!test_and_clear_bit(cpu, &call_data->started)) {
1053 /* If the bit wasn't set, this could be a replay */
1054 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1058 * At this point the info structure may be out of scope unless wait==1
1065 clear_bit(cpu, &call_data->finished);
1069 /* Call this function on all CPUs using the function_interrupt above
1070 <func> The function to run. This must be fast and non-blocking.
1071 <info> An arbitrary pointer to pass to the function.
1072 <retry> If true, keep retrying until ready.
1073 <wait> If true, wait until function has completed on other CPUs.
1074 [RETURNS] 0 on success, else a negative status code. Does not return until
1075 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1078 smp_call_function (void (*func) (void *info), void *info, int retry,
1081 struct call_data_struct data;
1082 __u32 mask = cpus_addr(cpu_online_map)[0];
1084 mask &= ~(1<<smp_processor_id());
1089 /* Can deadlock when called with interrupts disabled */
1090 WARN_ON(irqs_disabled());
1094 data.started = mask;
1097 data.finished = mask;
1099 spin_lock(&call_lock);
1102 /* Send a message to all other CPUs and wait for them to respond */
1103 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1105 /* Wait for response */
1106 while (data.started)
1110 while (data.finished)
1113 spin_unlock(&call_lock);
1118 /* Sorry about the name. In an APIC based system, the APICs
1119 * themselves are programmed to send a timer interrupt. This is used
1120 * by linux to reschedule the processor. Voyager doesn't have this,
1121 * so we use the system clock to interrupt one processor, which in
1122 * turn, broadcasts a timer CPI to all the others --- we receive that
1123 * CPI here. We don't use this actually for counting so losing
1124 * ticks doesn't matter
1126 * FIXME: For those CPU's which actually have a local APIC, we could
1127 * try to use it to trigger this interrupt instead of having to
1128 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1129 * no local APIC, so I can't do this
1131 * This function is currently a placeholder and is unused in the code */
1133 smp_apic_timer_interrupt(struct pt_regs *regs)
1135 wrapper_smp_local_timer_interrupt(regs);
1138 /* All of the QUAD interrupt GATES */
1140 smp_qic_timer_interrupt(struct pt_regs *regs)
1142 ack_QIC_CPI(QIC_TIMER_CPI);
1143 wrapper_smp_local_timer_interrupt(regs);
1147 smp_qic_invalidate_interrupt(struct pt_regs *regs)
1149 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1150 smp_invalidate_interrupt();
1154 smp_qic_reschedule_interrupt(struct pt_regs *regs)
1156 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1157 smp_reschedule_interrupt();
1161 smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1163 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1164 smp_enable_irq_interrupt();
1168 smp_qic_call_function_interrupt(struct pt_regs *regs)
1170 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1171 smp_call_function_interrupt();
1175 smp_vic_cpi_interrupt(struct pt_regs *regs)
1177 __u8 cpu = smp_processor_id();
1180 ack_QIC_CPI(VIC_CPI_LEVEL0);
1182 ack_VIC_CPI(VIC_CPI_LEVEL0);
1184 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1185 wrapper_smp_local_timer_interrupt(regs);
1186 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1187 smp_invalidate_interrupt();
1188 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1189 smp_reschedule_interrupt();
1190 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1191 smp_enable_irq_interrupt();
1192 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1193 smp_call_function_interrupt();
1197 do_flush_tlb_all(void* info)
1199 unsigned long cpu = smp_processor_id();
1202 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1207 /* flush the TLB of every active CPU in the system */
1211 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1214 /* used to set up the trampoline for other CPUs when the memory manager
1217 smp_alloc_memory(void)
1219 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1220 if(__pa(trampoline_base) >= 0x93000)
1224 /* send a reschedule CPI to one CPU by physical CPU number*/
1226 smp_send_reschedule(int cpu)
1228 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1233 hard_smp_processor_id(void)
1236 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1237 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1238 return cpumask & 0x1F;
1240 for(i = 0; i < 8; i++) {
1241 if(cpumask & (1<<i))
1244 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1248 /* broadcast a halt to all other CPUs */
1252 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1255 /* this function is triggered in time.c when a clock tick fires
1256 * we need to re-broadcast the tick to all CPUs */
1258 smp_vic_timer_interrupt(struct pt_regs *regs)
1260 send_CPI_allbutself(VIC_TIMER_CPI);
1261 smp_local_timer_interrupt(regs);
1265 wrapper_smp_local_timer_interrupt(struct pt_regs *regs)
1268 smp_local_timer_interrupt(regs);
1272 /* local (per CPU) timer interrupt. It does both profiling and
1273 * process statistics/rescheduling.
1275 * We do profiling in every local tick, statistics/rescheduling
1276 * happen only every 'profiling multiplier' ticks. The default
1277 * multiplier is 1 and it can be changed by writing the new multiplier
1278 * value into /proc/profile.
1281 smp_local_timer_interrupt(struct pt_regs * regs)
1283 int cpu = smp_processor_id();
1286 profile_tick(CPU_PROFILING, regs);
1287 if (--per_cpu(prof_counter, cpu) <= 0) {
1289 * The multiplier may have changed since the last time we got
1290 * to this point as a result of the user writing to
1291 * /proc/profile. In this case we need to adjust the APIC
1292 * timer accordingly.
1294 * Interrupts are already masked off at this point.
1296 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1297 if (per_cpu(prof_counter, cpu) !=
1298 per_cpu(prof_old_multiplier, cpu)) {
1299 /* FIXME: need to update the vic timer tick here */
1300 per_cpu(prof_old_multiplier, cpu) =
1301 per_cpu(prof_counter, cpu);
1304 update_process_times(user_mode(regs));
1307 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1308 /* only extended VIC processors participate in
1309 * interrupt distribution */
1313 * We take the 'long' return path, and there every subsystem
1314 * grabs the apropriate locks (kernel lock/ irq lock).
1316 * we might want to decouple profiling from the 'long path',
1317 * and do the profiling totally in assembly.
1319 * Currently this isn't too much of an issue (performance wise),
1320 * we can take more than 100K local irqs per second on a 100 MHz P5.
1323 if((++vic_tick[cpu] & 0x7) != 0)
1325 /* get here every 16 ticks (about every 1/6 of a second) */
1327 /* Change our priority to give someone else a chance at getting
1328 * the IRQ. The algorithm goes like this:
1330 * In the VIC, the dynamically routed interrupt is always
1331 * handled by the lowest priority eligible (i.e. receiving
1332 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1333 * lowest processor number gets it.
1335 * The priority of a CPU is controlled by a special per-CPU
1336 * VIC priority register which is 3 bits wide 0 being lowest
1337 * and 7 highest priority..
1339 * Therefore we subtract the average number of interrupts from
1340 * the number we've fielded. If this number is negative, we
1341 * lower the activity count and if it is positive, we raise
1344 * I'm afraid this still leads to odd looking interrupt counts:
1345 * the totals are all roughly equal, but the individual ones
1346 * look rather skewed.
1348 * FIXME: This algorithm is total crap when mixed with SMP
1349 * affinity code since we now try to even up the interrupt
1350 * counts when an affinity binding is keeping them on a
1352 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1353 - vic_intr_total) >> 4;
1360 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1362 #ifdef VOYAGER_DEBUG
1363 if((vic_tick[cpu] & 0xFFF) == 0) {
1364 /* print this message roughly every 25 secs */
1365 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1366 cpu, vic_tick[cpu], weight);
1371 /* setup the profiling timer */
1373 setup_profiling_timer(unsigned int multiplier)
1381 * Set the new multiplier for each CPU. CPUs don't start using the
1382 * new values until the next timer interrupt in which they do process
1385 for (i = 0; i < NR_CPUS; ++i)
1386 per_cpu(prof_multiplier, i) = multiplier;
1392 /* The CPIs are handled in the per cpu 8259s, so they must be
1393 * enabled to be received: FIX: enabling the CPIs in the early
1394 * boot sequence interferes with bug checking; enable them later
1396 #define VIC_SET_GATE(cpi, vector) \
1397 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1398 #define QIC_SET_GATE(cpi, vector) \
1399 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1406 /* initialize the per cpu irq mask to all disabled */
1407 for(i = 0; i < NR_CPUS; i++)
1408 vic_irq_mask[i] = 0xFFFF;
1410 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1412 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1413 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1415 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1416 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1417 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1418 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1419 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1422 /* now put the VIC descriptor into the first 48 IRQs
1424 * This is for later: first 16 correspond to PC IRQs; next 16
1425 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1426 for(i = 0; i < 48; i++)
1427 irq_desc[i].handler = &vic_irq_type;
1430 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1431 * processor to receive CPI */
1433 send_CPI(__u32 cpuset, __u8 cpi)
1436 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1438 if(cpi < VIC_START_FAKE_CPI) {
1439 /* fake CPI are only used for booting, so send to the
1440 * extended quads as well---Quads must be VIC booted */
1441 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1445 send_QIC_CPI(quad_cpuset, cpi);
1446 cpuset &= ~quad_cpuset;
1447 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1450 for_each_online_cpu(cpu) {
1451 if(cpuset & (1<<cpu))
1452 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1455 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1458 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1459 * set the cache line to shared by reading it.
1461 * DON'T make this inline otherwise the cache line read will be
1465 ack_QIC_CPI(__u8 cpi) {
1466 __u8 cpu = hard_smp_processor_id();
1470 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1471 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1475 ack_special_QIC_CPI(__u8 cpi)
1479 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1482 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1485 /* also clear at the VIC, just in case (nop for non-extended proc) */
1489 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1491 ack_VIC_CPI(__u8 cpi)
1493 #ifdef VOYAGER_DEBUG
1494 unsigned long flags;
1496 __u8 cpu = smp_processor_id();
1498 local_irq_save(flags);
1499 isr = vic_read_isr();
1500 if((isr & (1<<(cpi &7))) == 0) {
1501 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1504 /* send specific EOI; the two system interrupts have
1505 * bit 4 set for a separate vector but behave as the
1506 * corresponding 3 bit intr */
1507 outb_p(0x60|(cpi & 7),0x20);
1509 #ifdef VOYAGER_DEBUG
1510 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1511 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1513 local_irq_restore(flags);
1517 /* cribbed with thanks from irq.c */
1518 #define __byte(x,y) (((unsigned char *)&(y))[x])
1519 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1520 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1523 startup_vic_irq(unsigned int irq)
1525 enable_vic_irq(irq);
1530 /* The enable and disable routines. This is where we run into
1531 * conflicting architectural philosophy. Fundamentally, the voyager
1532 * architecture does not expect to have to disable interrupts globally
1533 * (the IRQ controllers belong to each CPU). The processor masquerade
1534 * which is used to start the system shouldn't be used in a running OS
1535 * since it will cause great confusion if two separate CPUs drive to
1536 * the same IRQ controller (I know, I've tried it).
1538 * The solution is a variant on the NCR lazy SPL design:
1540 * 1) To disable an interrupt, do nothing (other than set the
1541 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1543 * 2) If the interrupt dares to come in, raise the local mask against
1544 * it (this will result in all the CPU masks being raised
1547 * 3) To enable the interrupt, lower the mask on the local CPU and
1548 * broadcast an Interrupt enable CPI which causes all other CPUs to
1549 * adjust their masks accordingly. */
1552 enable_vic_irq(unsigned int irq)
1554 /* linux doesn't to processor-irq affinity, so enable on
1555 * all CPUs we know about */
1556 int cpu = smp_processor_id(), real_cpu;
1557 __u16 mask = (1<<irq);
1558 __u32 processorList = 0;
1559 unsigned long flags;
1561 VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1562 irq, cpu, cpu_irq_affinity[cpu]));
1563 spin_lock_irqsave(&vic_irq_lock, flags);
1564 for_each_online_cpu(real_cpu) {
1565 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1567 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1568 /* irq has no affinity for this CPU, ignore */
1571 if(real_cpu == cpu) {
1572 enable_local_vic_irq(irq);
1574 else if(vic_irq_mask[real_cpu] & mask) {
1575 vic_irq_enable_mask[real_cpu] |= mask;
1576 processorList |= (1<<real_cpu);
1579 spin_unlock_irqrestore(&vic_irq_lock, flags);
1581 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1585 disable_vic_irq(unsigned int irq)
1587 /* lazy disable, do nothing */
1591 enable_local_vic_irq(unsigned int irq)
1593 __u8 cpu = smp_processor_id();
1594 __u16 mask = ~(1 << irq);
1595 __u16 old_mask = vic_irq_mask[cpu];
1597 vic_irq_mask[cpu] &= mask;
1598 if(vic_irq_mask[cpu] == old_mask)
1601 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1605 outb_p(cached_A1(cpu),0xA1);
1609 outb_p(cached_21(cpu),0x21);
1615 disable_local_vic_irq(unsigned int irq)
1617 __u8 cpu = smp_processor_id();
1618 __u16 mask = (1 << irq);
1619 __u16 old_mask = vic_irq_mask[cpu];
1624 vic_irq_mask[cpu] |= mask;
1625 if(old_mask == vic_irq_mask[cpu])
1628 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1632 outb_p(cached_A1(cpu),0xA1);
1636 outb_p(cached_21(cpu),0x21);
1641 /* The VIC is level triggered, so the ack can only be issued after the
1642 * interrupt completes. However, we do Voyager lazy interrupt
1643 * handling here: It is an extremely expensive operation to mask an
1644 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1645 * this interrupt actually comes in, then we mask and ack here to push
1646 * the interrupt off to another CPU */
1648 before_handle_vic_irq(unsigned int irq)
1650 irq_desc_t *desc = irq_desc + irq;
1651 __u8 cpu = smp_processor_id();
1653 _raw_spin_lock(&vic_irq_lock);
1655 vic_intr_count[cpu]++;
1657 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1658 /* The irq is not in our affinity mask, push it off
1659 * onto another CPU */
1660 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1662 disable_local_vic_irq(irq);
1663 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1664 * actually calling the interrupt routine */
1665 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1666 } else if(desc->status & IRQ_DISABLED) {
1667 /* Damn, the interrupt actually arrived, do the lazy
1668 * disable thing. The interrupt routine in irq.c will
1669 * not handle a IRQ_DISABLED interrupt, so nothing more
1670 * need be done here */
1671 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1673 disable_local_vic_irq(irq);
1674 desc->status |= IRQ_REPLAY;
1676 desc->status &= ~IRQ_REPLAY;
1679 _raw_spin_unlock(&vic_irq_lock);
1682 /* Finish the VIC interrupt: basically mask */
1684 after_handle_vic_irq(unsigned int irq)
1686 irq_desc_t *desc = irq_desc + irq;
1688 _raw_spin_lock(&vic_irq_lock);
1690 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1691 #ifdef VOYAGER_DEBUG
1695 desc->status = status;
1696 if ((status & IRQ_DISABLED))
1697 disable_local_vic_irq(irq);
1698 #ifdef VOYAGER_DEBUG
1699 /* DEBUG: before we ack, check what's in progress */
1700 isr = vic_read_isr();
1701 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1703 __u8 cpu = smp_processor_id();
1705 int mask; /* Um... initialize me??? --RR */
1707 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1709 for_each_cpu(real_cpu, mask) {
1711 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1713 isr = vic_read_isr();
1714 if(isr & (1<<irq)) {
1715 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1719 outb(cpu, VIC_PROCESSOR_ID);
1722 #endif /* VOYAGER_DEBUG */
1723 /* as soon as we ack, the interrupt is eligible for
1724 * receipt by another CPU so everything must be in
1727 if(status & IRQ_REPLAY) {
1728 /* replay is set if we disable the interrupt
1729 * in the before_handle_vic_irq() routine, so
1730 * clear the in progress bit here to allow the
1731 * next CPU to handle this correctly */
1732 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1734 #ifdef VOYAGER_DEBUG
1735 isr = vic_read_isr();
1736 if((isr & (1<<irq)) != 0)
1737 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1739 #endif /* VOYAGER_DEBUG */
1741 _raw_spin_unlock(&vic_irq_lock);
1743 /* All code after this point is out of the main path - the IRQ
1744 * may be intercepted by another CPU if reasserted */
1748 /* Linux processor - interrupt affinity manipulations.
1750 * For each processor, we maintain a 32 bit irq affinity mask.
1751 * Initially it is set to all 1's so every processor accepts every
1752 * interrupt. In this call, we change the processor's affinity mask:
1754 * Change from enable to disable:
1756 * If the interrupt ever comes in to the processor, we will disable it
1757 * and ack it to push it off to another CPU, so just accept the mask here.
1759 * Change from disable to enable:
1761 * change the mask and then do an interrupt enable CPI to re-enable on
1762 * the selected processors */
1765 set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1767 /* Only extended processors handle interrupts */
1768 unsigned long real_mask;
1769 unsigned long irq_mask = 1 << irq;
1772 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1774 if(cpus_addr(mask)[0] == 0)
1775 /* can't have no cpu's to accept the interrupt -- extremely
1776 * bad things will happen */
1780 /* can't change the affinity of the timer IRQ. This
1781 * is due to the constraint in the voyager
1782 * architecture that the CPI also comes in on and IRQ
1783 * line and we have chosen IRQ0 for this. If you
1784 * raise the mask on this interrupt, the processor
1785 * will no-longer be able to accept VIC CPIs */
1789 /* You can only have 32 interrupts in a voyager system
1790 * (and 32 only if you have a secondary microchannel
1794 for_each_online_cpu(cpu) {
1795 unsigned long cpu_mask = 1 << cpu;
1797 if(cpu_mask & real_mask) {
1798 /* enable the interrupt for this cpu */
1799 cpu_irq_affinity[cpu] |= irq_mask;
1801 /* disable the interrupt for this cpu */
1802 cpu_irq_affinity[cpu] &= ~irq_mask;
1805 /* this is magic, we now have the correct affinity maps, so
1806 * enable the interrupt. This will send an enable CPI to
1807 * those cpu's who need to enable it in their local masks,
1808 * causing them to correct for the new affinity . If the
1809 * interrupt is currently globally disabled, it will simply be
1810 * disabled again as it comes in (voyager lazy disable). If
1811 * the affinity map is tightened to disable the interrupt on a
1812 * cpu, it will be pushed off when it comes in */
1813 enable_vic_irq(irq);
1817 ack_vic_irq(unsigned int irq)
1820 outb(0x62,0x20); /* Specific EOI to cascade */
1821 outb(0x60|(irq & 7),0xA0);
1823 outb(0x60 | (irq & 7),0x20);
1827 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1828 * but are not vectored by it. This means that the 8259 mask must be
1829 * lowered to receive them */
1831 vic_enable_cpi(void)
1833 __u8 cpu = smp_processor_id();
1835 /* just take a copy of the current mask (nop for boot cpu) */
1836 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1838 enable_local_vic_irq(VIC_CPI_LEVEL0);
1839 enable_local_vic_irq(VIC_CPI_LEVEL1);
1840 /* for sys int and cmn int */
1841 enable_local_vic_irq(7);
1844 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1845 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1846 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1847 cpu, QIC_CPI_ENABLE));
1850 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1851 cpu, vic_irq_mask[cpu]));
1857 int old_cpu = smp_processor_id(), cpu;
1859 /* dump the interrupt masks of each processor */
1860 for_each_online_cpu(cpu) {
1861 __u16 imr, isr, irr;
1862 unsigned long flags;
1864 local_irq_save(flags);
1865 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1866 imr = (inb(0xa1) << 8) | inb(0x21);
1868 irr = inb(0xa0) << 8;
1872 isr = inb(0xa0) << 8;
1875 outb(old_cpu, VIC_PROCESSOR_ID);
1876 local_irq_restore(flags);
1877 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1878 cpu, vic_irq_mask[cpu], imr, irr, isr);
1880 /* These lines are put in to try to unstick an un ack'd irq */
1883 for(irq=0; irq<16; irq++) {
1884 if(isr & (1<<irq)) {
1885 printk("\tCPU%d: ack irq %d\n",
1887 local_irq_save(flags);
1888 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1891 outb(old_cpu, VIC_PROCESSOR_ID);
1892 local_irq_restore(flags);
1901 smp_voyager_power_off(void *dummy)
1903 if(smp_processor_id() == boot_cpu_id)
1904 voyager_power_off();
1906 smp_stop_cpu_function(NULL);
1910 smp_prepare_cpus(unsigned int max_cpus)
1912 /* FIXME: ignore max_cpus for now */
1916 void __devinit smp_prepare_boot_cpu(void)
1918 cpu_set(smp_processor_id(), cpu_online_map);
1919 cpu_set(smp_processor_id(), cpu_callout_map);
1923 __cpu_up(unsigned int cpu)
1925 /* This only works at boot for x86. See "rewrite" above. */
1926 if (cpu_isset(cpu, smp_commenced_mask))
1929 /* In case one didn't come up */
1930 if (!cpu_isset(cpu, cpu_callin_map))
1932 /* Unleash the CPU! */
1933 cpu_set(cpu, smp_commenced_mask);
1934 while (!cpu_isset(cpu, cpu_online_map))
1940 smp_cpus_done(unsigned int max_cpus)