2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
6 #include <linux/init.h>
10 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
13 * i450NX -- Find and scan all secondary buses on all PXB's.
18 printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
20 for(pxb=0; pxb<2; pxb++) {
21 pci_read_config_byte(d, reg++, &busno);
22 pci_read_config_byte(d, reg++, &suba);
23 pci_read_config_byte(d, reg++, &subb);
24 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
26 pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */
28 pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */
30 pcibios_last_bus = -1;
32 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
34 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
37 * i450GX and i450KX -- Find and scan all secondary buses.
38 * (called separately for each PCI bridge found)
41 pci_read_config_byte(d, 0x4a, &busno);
42 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
43 pci_scan_bus(busno, &pci_root_ops, NULL);
44 pcibios_last_bus = -1;
46 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
48 static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
51 * UM8886BF IDE controller sets region type bits incorrectly,
52 * therefore they look like memory despite of them being I/O.
56 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
58 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
60 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
62 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
65 * NCR 53C810 returns class code 0 (at least on some systems).
66 * Fix class to be PCI_CLASS_STORAGE_SCSI
69 printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
70 d->class = PCI_CLASS_STORAGE_SCSI << 8;
73 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
75 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
80 * PCI IDE controllers use non-standard I/O port decoding, respect it.
82 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
84 DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
86 struct resource *r = &d->resource[i];
87 if ((r->start & ~0x80) == 0x374) {
93 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
95 static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
100 * Runs the fixup only for the first IDE controller
101 * (Shai Fultheim - shai@ftcon.com)
103 static int called = 0;
109 * There exist PCI IDE controllers which have utter garbage
110 * in first four base registers. Ignore that.
112 DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
114 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash);
118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash);
119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash);
121 static void __devinit pci_fixup_latency(struct pci_dev *d)
124 * SiS 5597 and 5598 chipsets require latency timer set to
125 * at most 32 to avoid lockups.
127 DBG("PCI: Setting max latency to 32\n");
128 pcibios_max_latency = 32;
130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
133 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
136 * PIIX4 ACPI device: hardwired IRQ9
140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
143 * Addresses issues with problems in the memory write queue timer in
144 * certain VIA Northbridges. This bugfix is per VIA's specifications,
145 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
146 * to trigger a bug in its integrated ProSavage video card, which
147 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
148 * until VIA can provide us with definitive information on why screen
149 * corruption occurs, and what exactly those bits do.
151 * VIA 8363,8622,8361 Northbridges:
152 * - bits 5, 6, 7 at offset 0x55 need to be turned off
153 * VIA 8367 (KT266x) Northbridges:
154 * - bits 5, 6, 7 at offset 0x95 need to be turned off
155 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
156 * - bits 6, 7 at offset 0x55 need to be turned off
159 #define VIA_8363_KL133_REVISION_ID 0x81
160 #define VIA_8363_KM133_REVISION_ID 0x84
162 static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
167 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
169 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
171 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
172 /* fix pci bus latency issues resulted by NB bios error
173 it appears on bug free^Wreduced kt266x's bios forces
174 NB latency to zero */
175 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
177 where = 0x95; /* the memory write queue timer register is
178 different for the KT266x's: 0x95 not 0x55 */
179 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
180 (revision == VIA_8363_KL133_REVISION_ID ||
181 revision == VIA_8363_KM133_REVISION_ID)) {
182 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
183 causes screen corruption on the KL133/KM133 */
186 pci_read_config_byte(d, where, &v);
188 printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
189 d->device, revision, where, v, mask, v & mask);
191 pci_write_config_byte(d, where, v);
194 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
195 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
196 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
200 * For some reasons Intel decided that certain parts of their
201 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
202 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
203 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
204 * to Intel terminology. These devices do forward all addresses from
205 * system to PCI bus no matter what are their window settings, so they are
206 * "transparent" (or subtractive decoding) from programmers point of view.
208 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
210 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
211 (dev->device & 0xff00) == 0x2400)
212 dev->transparent = 1;
214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
217 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
219 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
221 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
222 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
223 * This allows the state-machine and timer to return to a proper state within
224 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
225 * issue another HALT within 80 ns of the initial HALT, the failure condition
228 static void __init pci_fixup_nforce2(struct pci_dev *dev)
233 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
236 * Chip Old value New value
237 * C17 0x1F0FFF01 0x1F01FF01
238 * C18D 0x9F0FFF01 0x9F01FF01
240 * Northbridge chip version may be determined by
241 * reading the PCI revision ID (0xC1 or greater is C18D).
243 fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;
245 pci_read_config_dword(dev, 0x6c, &val);
248 * Apply fixup only if C1 Halt Disconnect is enabled
249 * (bit28) because it is not supported on some boards.
251 if ((val & (1 << 28)) && val != fixed_val) {
252 printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
253 pci_write_config_dword(dev, 0x6c, fixed_val);
256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);