2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
17 #include <asm/io_apic.h>
18 #include <asm/hw_irq.h>
22 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
23 #define PIRQ_VERSION 0x0100
25 int broken_hp_bios_irq9;
27 static struct irq_routing_table *pirq_table;
30 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
31 * Avoid using: 13, 14 and 15 (FP error and IDE).
32 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
34 unsigned int pcibios_irq_mask = 0xfff8;
36 static int pirq_penalty[16] = {
37 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
38 0, 0, 0, 0, 1000, 100000, 100000, 100000
44 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
45 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
48 struct irq_router_handler {
50 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
53 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
56 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
59 static struct irq_routing_table * __init pirq_find_routing_table(void)
62 struct irq_routing_table *rt;
66 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
67 rt = (struct irq_routing_table *) addr;
68 if (rt->signature != PIRQ_SIGNATURE ||
69 rt->version != PIRQ_VERSION ||
71 rt->size < sizeof(struct irq_routing_table))
74 for(i=0; i<rt->size; i++)
77 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
85 * If we have a IRQ routing table, use it to search for peer host
86 * bridges. It's a gross hack, but since there are no other known
87 * ways how to get a list of buses, we have to go this way.
90 static void __init pirq_peer_trick(void)
92 struct irq_routing_table *rt = pirq_table;
97 memset(busmap, 0, sizeof(busmap));
98 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
103 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
105 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
111 for(i = 1; i < 256; i++) {
112 if (!busmap[i] || pci_find_bus(0, i))
114 if (pci_scan_bus(i, &pci_root_ops, NULL))
115 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
117 pcibios_last_bus = -1;
121 * Code for querying and setting of IRQ routes on various interrupt routers.
124 void eisa_set_level_irq(unsigned int irq)
126 unsigned char mask = 1 << (irq & 7);
127 unsigned int port = 0x4d0 + (irq >> 3);
128 unsigned char val = inb(port);
132 outb(val | mask, port);
137 * Common IRQ routing practice: nybbles in config space,
138 * offset by some magic constant.
140 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
143 unsigned reg = offset + (nr >> 1);
145 pci_read_config_byte(router, reg, &x);
146 return (nr & 1) ? (x >> 4) : (x & 0xf);
149 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
152 unsigned reg = offset + (nr >> 1);
154 pci_read_config_byte(router, reg, &x);
155 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
156 pci_write_config_byte(router, reg, x);
160 * ALI pirq entries are damn ugly, and completely undocumented.
161 * This has been figured out from pirq tables, and it's not a pretty
164 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
166 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
168 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
171 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
173 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
174 unsigned int val = irqmap[irq];
177 write_config_nybble(router, 0x48, pirq-1, val);
184 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
185 * just a pointer to the config space.
187 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
191 pci_read_config_byte(router, pirq, &x);
192 return (x < 16) ? x : 0;
195 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
197 pci_write_config_byte(router, pirq, irq);
202 * The VIA pirq rules are nibble-based, like ALI,
203 * but without the ugly irq number munging.
204 * However, PIRQD is in the upper instead of lower 4 bits.
206 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
208 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
211 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
213 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
218 * ITE 8330G pirq rules are nibble-based
219 * FIXME: pirqmap may be { 1, 0, 3, 2 },
220 * 2+3 are both mapped to irq 9 on my system
222 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
224 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
225 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
228 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
230 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
231 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
236 * OPTI: high four bits are nibble pointer..
237 * I wonder what the low bits do?
239 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
241 return read_config_nybble(router, 0xb8, pirq >> 4);
244 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
246 write_config_nybble(router, 0xb8, pirq >> 4, irq);
251 * Cyrix: nibble offset 0x5C
252 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
253 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
255 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
257 return read_config_nybble(router, 0x5C, (pirq-1)^1);
260 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
262 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
267 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
268 * We have to deal with the following issues here:
269 * - vendors have different ideas about the meaning of link values
270 * - some onboard devices (integrated in the chipset) have special
271 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
272 * - different revision of the router have a different layout for
273 * the routing registers, particularly for the onchip devices
275 * For all routing registers the common thing is we have one byte
276 * per routeable link which is defined as:
277 * bit 7 IRQ mapping enabled (0) or disabled (1)
278 * bits [6:4] reserved (sometimes used for onchip devices)
279 * bits [3:0] IRQ to map to
280 * allowed: 3-7, 9-12, 14-15
281 * reserved: 0, 1, 2, 8, 13
283 * The config-space registers located at 0x41/0x42/0x43/0x44 are
284 * always used to route the normal PCI INT A/B/C/D respectively.
285 * Apparently there are systems implementing PCI routing table using
286 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
287 * We try our best to handle both link mappings.
289 * Currently (2003-05-21) it appears most SiS chipsets follow the
290 * definition of routing registers from the SiS-5595 southbridge.
291 * According to the SiS 5595 datasheets the revision id's of the
292 * router (ISA-bridge) should be 0x01 or 0xb0.
294 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
295 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
296 * They seem to work with the current routing code. However there is
297 * some concern because of the two USB-OHCI HCs (original SiS 5595
298 * had only one). YMMV.
300 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
303 * bits [6:5] must be written 01
304 * bit 4 channel-select primary (0), secondary (1)
307 * bit 6 OHCI function disabled (0), enabled (1)
309 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
311 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
313 * We support USBIRQ (in addition to INTA-INTD) and keep the
314 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
316 * Currently the only reported exception is the new SiS 65x chipset
317 * which includes the SiS 69x southbridge. Here we have the 85C503
318 * router revision 0x04 and there are changes in the register layout
319 * mostly related to the different USB HCs with USB 2.0 support.
321 * Onchip routing for router rev-id 0x04 (try-and-error observation)
323 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
324 * bit 6-4 are probably unused, not like 5595
327 #define PIRQ_SIS_IRQ_MASK 0x0f
328 #define PIRQ_SIS_IRQ_DISABLE 0x80
329 #define PIRQ_SIS_USB_ENABLE 0x40
331 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
337 if (reg >= 0x01 && reg <= 0x04)
339 pci_read_config_byte(router, reg, &x);
340 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
343 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
349 if (reg >= 0x01 && reg <= 0x04)
351 pci_read_config_byte(router, reg, &x);
352 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
353 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
354 pci_write_config_byte(router, reg, x);
360 * VLSI: nibble offset 0x74 - educated guess due to routing table and
361 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
362 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
363 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
364 * for the busbridge to the docking station.
367 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
370 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
373 return read_config_nybble(router, 0x74, pirq-1);
376 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
379 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
382 write_config_nybble(router, 0x74, pirq-1, irq);
387 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
388 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
389 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
390 * register is a straight binary coding of desired PIC IRQ (low nibble).
392 * The 'link' value in the PIRQ table is already in the correct format
393 * for the Index register. There are some special index values:
394 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
395 * and 0x03 for SMBus.
397 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
400 return inb(0xc01) & 0xf;
403 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
410 /* Support for AMD756 PCI IRQ Routing
411 * Jhon H. Caicedo <jhcaiced@osso.org.co>
412 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
413 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
414 * The AMD756 pirq rules are nibble-based
415 * offset 0x56 0-3 PIRQA 4-7 PIRQB
416 * offset 0x57 0-3 PIRQC 4-7 PIRQD
418 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
424 irq = read_config_nybble(router, 0x56, pirq - 1);
426 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
427 dev->vendor, dev->device, pirq, irq);
431 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
433 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
434 dev->vendor, dev->device, pirq, irq);
437 write_config_nybble(router, 0x56, pirq - 1, irq);
442 #ifdef CONFIG_PCI_BIOS
444 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
446 struct pci_dev *bridge;
447 int pin = pci_get_interrupt_pin(dev, &bridge);
448 return pcibios_set_irq_routing(bridge, pin, irq);
454 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
456 /* 440GX has a proprietary PIRQ router -- don't use it */
457 if ( pci_find_device(PCI_VENDOR_ID_INTEL,
458 PCI_DEVICE_ID_INTEL_82443GX_0, NULL) ||
459 pci_find_device(PCI_VENDOR_ID_INTEL,
460 PCI_DEVICE_ID_INTEL_82443GX_2, NULL))
465 case PCI_DEVICE_ID_INTEL_82371FB_0:
466 case PCI_DEVICE_ID_INTEL_82371SB_0:
467 case PCI_DEVICE_ID_INTEL_82371AB_0:
468 case PCI_DEVICE_ID_INTEL_82371MX:
469 case PCI_DEVICE_ID_INTEL_82443MX_0:
470 case PCI_DEVICE_ID_INTEL_82801AA_0:
471 case PCI_DEVICE_ID_INTEL_82801AB_0:
472 case PCI_DEVICE_ID_INTEL_82801BA_0:
473 case PCI_DEVICE_ID_INTEL_82801BA_10:
474 case PCI_DEVICE_ID_INTEL_82801CA_0:
475 case PCI_DEVICE_ID_INTEL_82801CA_12:
476 case PCI_DEVICE_ID_INTEL_82801DB_0:
477 case PCI_DEVICE_ID_INTEL_82801E_0:
478 case PCI_DEVICE_ID_INTEL_82801EB_0:
479 case PCI_DEVICE_ID_INTEL_ESB_0:
480 case PCI_DEVICE_ID_INTEL_ICH6_0:
481 r->name = "PIIX/ICH";
482 r->get = pirq_piix_get;
483 r->set = pirq_piix_set;
489 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
491 /* FIXME: We should move some of the quirk fixup stuff here */
494 case PCI_DEVICE_ID_VIA_82C586_0:
495 case PCI_DEVICE_ID_VIA_82C596:
496 case PCI_DEVICE_ID_VIA_82C686:
497 case PCI_DEVICE_ID_VIA_8231:
498 /* FIXME: add new ones for 8233/5 */
500 r->get = pirq_via_get;
501 r->set = pirq_via_set;
507 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
511 case PCI_DEVICE_ID_VLSI_82C534:
512 r->name = "VLSI 82C534";
513 r->get = pirq_vlsi_get;
514 r->set = pirq_vlsi_set;
521 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
525 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
526 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
527 r->name = "ServerWorks";
528 r->get = pirq_serverworks_get;
529 r->set = pirq_serverworks_set;
535 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
537 if (device != PCI_DEVICE_ID_SI_503)
541 r->get = pirq_sis_get;
542 r->set = pirq_sis_set;
543 DBG("PCI: Detecting SiS router at %02x:%02x\n",
544 rt->rtr_bus, rt->rtr_devfn);
548 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
552 case PCI_DEVICE_ID_CYRIX_5520:
554 r->get = pirq_cyrix_get;
555 r->set = pirq_cyrix_set;
561 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
565 case PCI_DEVICE_ID_OPTI_82C700:
567 r->get = pirq_opti_get;
568 r->set = pirq_opti_set;
574 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
578 case PCI_DEVICE_ID_ITE_IT8330G_0:
580 r->get = pirq_ite_get;
581 r->set = pirq_ite_set;
587 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
591 case PCI_DEVICE_ID_AL_M1533:
592 case PCI_DEVICE_ID_AL_M1563:
593 printk("PCI: Using ALI IRQ Router\n");
595 r->get = pirq_ali_get;
596 r->set = pirq_ali_set;
602 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
606 case PCI_DEVICE_ID_AMD_VIPER_740B:
609 case PCI_DEVICE_ID_AMD_VIPER_7413:
612 case PCI_DEVICE_ID_AMD_VIPER_7443:
618 r->get = pirq_amd756_get;
619 r->set = pirq_amd756_set;
623 static __initdata struct irq_router_handler pirq_routers[] = {
624 { PCI_VENDOR_ID_INTEL, intel_router_probe },
625 { PCI_VENDOR_ID_AL, ali_router_probe },
626 { PCI_VENDOR_ID_ITE, ite_router_probe },
627 { PCI_VENDOR_ID_VIA, via_router_probe },
628 { PCI_VENDOR_ID_OPTI, opti_router_probe },
629 { PCI_VENDOR_ID_SI, sis_router_probe },
630 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
631 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
632 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
633 { PCI_VENDOR_ID_AMD, amd_router_probe },
634 /* Someone with docs needs to add the ATI Radeon IGP */
637 static struct irq_router pirq_router;
638 static struct pci_dev *pirq_router_dev;
642 * FIXME: should we have an option to say "generic for
646 static void __init pirq_find_router(struct irq_router *r)
648 struct irq_routing_table *rt = pirq_table;
649 struct irq_router_handler *h;
651 #ifdef CONFIG_PCI_BIOS
652 if (!rt->signature) {
653 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
654 r->set = pirq_bios_set;
660 /* Default unless a driver reloads it */
665 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
666 rt->rtr_vendor, rt->rtr_device);
668 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
669 if (!pirq_router_dev) {
670 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
674 for( h = pirq_routers; h->vendor; h++) {
675 /* First look for a router match */
676 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
678 /* Fall back to a device match */
679 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
682 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
684 pirq_router_dev->vendor,
685 pirq_router_dev->device,
686 pci_name(pirq_router_dev));
689 static struct irq_info *pirq_get_info(struct pci_dev *dev)
691 struct irq_routing_table *rt = pirq_table;
692 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
693 struct irq_info *info;
695 for (info = rt->slots; entries--; info++)
696 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
701 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
704 struct irq_info *info;
708 struct irq_router *r = &pirq_router;
709 struct pci_dev *dev2 = NULL;
713 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
715 DBG(" -> no interrupt pin\n");
720 /* Find IRQ routing entry */
725 DBG("IRQ for %s:%d", pci_name(dev), pin);
726 info = pirq_get_info(dev);
728 DBG(" -> not found in routing table\n");
731 pirq = info->irq[pin].link;
732 mask = info->irq[pin].bitmap;
734 DBG(" -> not routed\n");
737 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
738 mask &= pcibios_irq_mask;
740 /* Work around broken HP Pavilion Notebooks which assign USB to
741 IRQ 9 even though it is actually wired to IRQ 11 */
743 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
745 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
746 r->set(pirq_router_dev, dev, pirq, 11);
750 * Find the best IRQ to assign: use the one
751 * reported by the device if possible.
754 if (!((1 << newirq) & mask)) {
755 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
756 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
758 if (!newirq && assign) {
759 for (i = 0; i < 16; i++) {
760 if (!(mask & (1 << i)))
762 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
766 DBG(" -> newirq=%d", newirq);
768 /* Check if it is hardcoded */
769 if ((pirq & 0xf0) == 0xf0) {
771 DBG(" -> hardcoded IRQ %d\n", irq);
773 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
774 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
775 DBG(" -> got IRQ %d\n", irq);
777 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
778 DBG(" -> assigning IRQ %d", newirq);
779 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
780 eisa_set_level_irq(newirq);
788 DBG(" ... failed\n");
789 if (newirq && mask == (1 << newirq)) {
795 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
797 /* Update IRQ for all devices with the same pirq value */
798 while ((dev2 = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
799 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
803 info = pirq_get_info(dev2);
806 if (info->irq[pin].link == pirq) {
807 /* We refuse to override the dev->irq information. Give a warning! */
808 if ( dev2->irq && dev2->irq != irq && \
809 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
810 ((1 << dev2->irq) & mask)) ) {
811 #ifndef CONFIG_PCI_USE_VECTOR
812 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
813 pci_name(dev2), dev2->irq, irq);
820 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
826 static void __init pcibios_fixup_irqs(void)
828 struct pci_dev *dev = NULL;
831 DBG("PCI: IRQ fixup\n");
832 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
834 * If the BIOS has set an out of range IRQ number, just ignore it.
835 * Also keep track of which IRQ's are already in use.
837 if (dev->irq >= 16) {
838 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
841 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
842 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
843 pirq_penalty[dev->irq] = 0;
844 pirq_penalty[dev->irq]++;
848 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
849 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
850 #ifdef CONFIG_X86_IO_APIC
852 * Recalculate IRQ numbers if we use the I/O APIC.
854 if (io_apic_assign_pci_irqs)
859 pin--; /* interrupt pins are numbered starting from 1 */
860 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
862 * Busses behind bridges are typically not listed in the MP-table.
863 * In this case we have to look up the IRQ based on the parent bus,
864 * parent slot, and pin number. The SMP code detects such bridged
865 * busses itself so we should get into this branch reliably.
867 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
868 struct pci_dev * bridge = dev->bus->self;
870 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
871 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
872 PCI_SLOT(bridge->devfn), pin);
874 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
875 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
878 if (use_pci_vector() &&
879 !platform_legacy_irq(irq))
880 irq = IO_APIC_VECTOR(irq);
882 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
883 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
890 * Still no IRQ? Try to lookup one...
892 if (pin && !dev->irq)
893 pcibios_lookup_irq(dev, 0);
897 static int __init pcibios_irq_init(void)
899 DBG("PCI: IRQ init\n");
901 if (pcibios_enable_irq)
904 pirq_table = pirq_find_routing_table();
906 #ifdef CONFIG_PCI_BIOS
907 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
908 pirq_table = pcibios_get_irq_routing_table();
912 pirq_find_router(&pirq_router);
913 if (pirq_table->exclusive_irqs) {
916 if (!(pirq_table->exclusive_irqs & (1 << i)))
917 pirq_penalty[i] += 100;
919 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
920 if (io_apic_assign_pci_irqs)
924 pcibios_enable_irq = pirq_enable_irq;
926 pcibios_fixup_irqs();
930 subsys_initcall(pcibios_irq_init);
933 void pcibios_penalize_isa_irq(int irq)
936 * If any ISAPnP device reports an IRQ in its list of possible
937 * IRQ's, we try to avoid assigning it to PCI devices.
939 pirq_penalty[irq] += 100;
942 int pirq_enable_irq(struct pci_dev *dev)
945 extern int interrupt_line_quirk;
946 struct pci_dev *temp_dev;
948 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
949 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
952 if (io_apic_assign_pci_irqs) {
956 pin--; /* interrupt pins are numbered starting from 1 */
957 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
959 * Busses behind bridges are typically not listed in the MP-table.
960 * In this case we have to look up the IRQ based on the parent bus,
961 * parent slot, and pin number. The SMP code detects such bridged
962 * busses itself so we should get into this branch reliably.
965 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
966 struct pci_dev * bridge = dev->bus->self;
968 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
969 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
970 PCI_SLOT(bridge->devfn), pin);
972 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
973 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
978 #ifdef CONFIG_PCI_USE_VECTOR
979 if (!platform_legacy_irq(irq))
980 irq = IO_APIC_VECTOR(irq);
982 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
983 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
987 msg = " Probably buggy MP table.";
989 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
992 msg = " Please try using pci=biosirq.";
994 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
995 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
998 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
999 'A' + pin - 1, pci_name(dev), msg);
1001 /* VIA bridges use interrupt line for apic/pci steering across
1003 else if (interrupt_line_quirk)
1004 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1008 int pci_vector_resources(int last, int nr_released)
1010 int count = nr_released;
1013 int offset = (last % 8);
1015 while (next < FIRST_SYSTEM_VECTOR) {
1017 #ifdef CONFIG_X86_64
1018 if (next == IA32_SYSCALL_VECTOR)
1021 if (next == SYSCALL_VECTOR)
1025 if (next >= FIRST_SYSTEM_VECTOR) {
1027 next = FIRST_DEVICE_VECTOR + offset;