2 ** IA64 System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2002-2004 Alex Williamson
5 ** (c) Copyright 2002-2003 Grant Grundler
6 ** (c) Copyright 2002-2004 Hewlett-Packard Company
8 ** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code)
9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
11 ** This program is free software; you can redistribute it and/or modify
12 ** it under the terms of the GNU General Public License as published by
13 ** the Free Software Foundation; either version 2 of the License, or
14 ** (at your option) any later version.
17 ** This module initializes the IOC (I/O Controller) found on HP
18 ** McKinley machines and their successors.
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
30 #include <linux/string.h>
31 #include <linux/pci.h>
32 #include <linux/proc_fs.h>
33 #include <linux/seq_file.h>
34 #include <linux/acpi.h>
35 #include <linux/efi.h>
36 #include <linux/nodemask.h>
37 #include <linux/bitops.h> /* hweight64() */
39 #include <asm/delay.h> /* ia64_get_itc() */
41 #include <asm/page.h> /* PAGE_OFFSET */
43 #include <asm/system.h> /* wmb() */
45 #include <asm/acpi-ext.h>
50 ** Enabling timing search of the pdir resource map. Output in /proc.
51 ** Disabled by default to optimize performance.
53 #undef PDIR_SEARCH_TIMING
56 ** This option allows cards capable of 64bit DMA to bypass the IOMMU. If
57 ** not defined, all DMA will be 32bit and go through the TLB.
58 ** There's potentially a conflict in the bio merge code with us
59 ** advertising an iommu, but then bypassing it. Since I/O MMU bypassing
60 ** appears to give more performance than bio-level virtual merging, we'll
61 ** do the former for now. NOTE: BYPASS_SG also needs to be undef'd to
62 ** completely restrict DMA to the IOMMU.
64 #define ALLOW_IOV_BYPASS
67 ** This option specifically allows/disallows bypassing scatterlists with
68 ** multiple entries. Coalescing these entries can allow better DMA streaming
69 ** and in some cases shows better performance than entirely bypassing the
70 ** IOMMU. Performance increase on the order of 1-2% sequential output/input
71 ** using bonnie++ on a RAID0 MD device (sym2 & mpt).
73 #undef ALLOW_IOV_BYPASS_SG
76 ** If a device prefetches beyond the end of a valid pdir entry, it will cause
77 ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
78 ** disconnect on 4k boundaries and prevent such issues. If the device is
79 ** particularly agressive, this option will keep the entire pdir valid such
80 ** that prefetching will hit a valid address. This could severely impact
81 ** error containment, and is therefore off by default. The page that is
82 ** used for spill-over is poisoned, so that should help debugging somewhat.
84 #undef FULL_VALID_PDIR
86 #define ENABLE_MARK_CLEAN
89 ** The number of debug flags is a clue - this code is fragile. NOTE: since
90 ** tightening the use of res_lock the resource bitmap and actual pdir are no
91 ** longer guaranteed to stay in sync. The sanity checking code isn't going to
96 #undef DEBUG_SBA_RUN_SG
97 #undef DEBUG_SBA_RESOURCE
98 #undef ASSERT_PDIR_SANITY
99 #undef DEBUG_LARGE_SG_ENTRIES
102 #if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY)
103 #error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive
106 #define SBA_INLINE __inline__
107 /* #define SBA_INLINE */
109 #ifdef DEBUG_SBA_INIT
110 #define DBG_INIT(x...) printk(x)
112 #define DBG_INIT(x...)
116 #define DBG_RUN(x...) printk(x)
118 #define DBG_RUN(x...)
121 #ifdef DEBUG_SBA_RUN_SG
122 #define DBG_RUN_SG(x...) printk(x)
124 #define DBG_RUN_SG(x...)
128 #ifdef DEBUG_SBA_RESOURCE
129 #define DBG_RES(x...) printk(x)
131 #define DBG_RES(x...)
135 #define DBG_BYPASS(x...) printk(x)
137 #define DBG_BYPASS(x...)
140 #ifdef ASSERT_PDIR_SANITY
141 #define ASSERT(expr) \
143 printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
151 ** The number of pdir entries to "free" before issuing
152 ** a read to PCOM register to flush out PCOM writes.
153 ** Interacts with allocation granularity (ie 4 or 8 entries
154 ** allocated and free'd/purged at a time might make this
155 ** less interesting).
157 #define DELAYED_RESOURCE_CNT 64
159 #define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
160 #define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
161 #define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
163 #define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
165 #define IOC_FUNC_ID 0x000
166 #define IOC_FCLASS 0x008 /* function class, bist, header, rev... */
167 #define IOC_IBASE 0x300 /* IO TLB */
168 #define IOC_IMASK 0x308
169 #define IOC_PCOM 0x310
170 #define IOC_TCNFG 0x318
171 #define IOC_PDIR_BASE 0x320
173 #define IOC_ROPE0_CFG 0x500
174 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
177 /* AGP GART driver looks for this */
178 #define ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
181 ** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register)
183 ** Some IOCs (sx1000) can run at the above pages sizes, but are
184 ** really only supported using the IOC at a 4k page size.
186 ** iovp_size could only be greater than PAGE_SIZE if we are
187 ** confident the drivers really only touch the next physical
188 ** page iff that driver instance owns it.
190 static unsigned long iovp_size;
191 static unsigned long iovp_shift;
192 static unsigned long iovp_mask;
195 void __iomem *ioc_hpa; /* I/O MMU base address */
196 char *res_map; /* resource map, bit == pdir entry */
197 u64 *pdir_base; /* physical base address */
198 unsigned long ibase; /* pdir IOV Space base */
199 unsigned long imask; /* pdir IOV Space mask */
201 unsigned long *res_hint; /* next avail IOVP - circular search */
202 unsigned long dma_mask;
203 spinlock_t res_lock; /* protects the resource bitmap, but must be held when */
204 /* clearing pdir to prevent races with allocations. */
205 unsigned int res_bitshift; /* from the RIGHT! */
206 unsigned int res_size; /* size of resource map in bytes */
208 unsigned int node; /* node where this IOC lives */
210 #if DELAYED_RESOURCE_CNT > 0
211 spinlock_t saved_lock; /* may want to try to get this on a separate cacheline */
212 /* than res_lock for bigger systems. */
214 struct sba_dma_pair {
217 } saved[DELAYED_RESOURCE_CNT];
220 #ifdef PDIR_SEARCH_TIMING
221 #define SBA_SEARCH_SAMPLE 0x100
222 unsigned long avg_search[SBA_SEARCH_SAMPLE];
223 unsigned long avg_idx; /* current index into avg_search */
226 /* Stuff we don't need in performance path */
227 struct ioc *next; /* list of IOC's in system */
228 acpi_handle handle; /* for multiple IOC's */
230 unsigned int func_id;
231 unsigned int rev; /* HW revision of chip */
233 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
234 struct pci_dev *sac_only_dev;
237 static struct ioc *ioc_list;
238 static int reserve_sba_gart = 1;
240 static SBA_INLINE void sba_mark_invalid(struct ioc *, dma_addr_t, size_t);
241 static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t);
243 #define sba_sg_address(sg) (page_address((sg)->page) + (sg)->offset)
245 #ifdef FULL_VALID_PDIR
246 static u64 prefetch_spill_page;
250 # define GET_IOC(dev) (((dev)->bus == &pci_bus_type) \
251 ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
253 # define GET_IOC(dev) NULL
257 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
258 ** (or rather not merge) DMA's into managable chunks.
259 ** On parisc, this is more of the software/tuning constraint
260 ** rather than the HW. I/O MMU allocation alogorithms can be
261 ** faster with smaller size is (to some degree).
263 #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
265 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
267 /************************************
268 ** SBA register read and write support
270 ** BE WARNED: register writes are posted.
271 ** (ie follow writes which must reach HW with a read)
274 #define READ_REG(addr) __raw_readq(addr)
275 #define WRITE_REG(val, addr) __raw_writeq(val, addr)
277 #ifdef DEBUG_SBA_INIT
280 * sba_dump_tlb - debugging only - print IOMMU operating parameters
281 * @hpa: base address of the IOMMU
283 * Print the size/location of the IO MMU PDIR.
286 sba_dump_tlb(char *hpa)
288 DBG_INIT("IO TLB at 0x%p\n", (void *)hpa);
289 DBG_INIT("IOC_IBASE : %016lx\n", READ_REG(hpa+IOC_IBASE));
290 DBG_INIT("IOC_IMASK : %016lx\n", READ_REG(hpa+IOC_IMASK));
291 DBG_INIT("IOC_TCNFG : %016lx\n", READ_REG(hpa+IOC_TCNFG));
292 DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE));
298 #ifdef ASSERT_PDIR_SANITY
301 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
302 * @ioc: IO MMU structure which owns the pdir we are interested in.
303 * @msg: text to print ont the output line.
306 * Print one entry of the IO MMU PDIR in human readable form.
309 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
311 /* start printing from lowest pde in rval */
312 u64 *ptr = &ioc->pdir_base[pide & ~(BITS_PER_LONG - 1)];
313 unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)];
316 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
317 msg, rptr, pide & (BITS_PER_LONG - 1), *rptr);
320 while (rcnt < BITS_PER_LONG) {
321 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
322 (rcnt == (pide & (BITS_PER_LONG - 1)))
324 rcnt, ptr, (unsigned long long) *ptr );
328 printk(KERN_DEBUG "%s", msg);
333 * sba_check_pdir - debugging only - consistency checker
334 * @ioc: IO MMU structure which owns the pdir we are interested in.
335 * @msg: text to print ont the output line.
337 * Verify the resource map and pdir state is consistent
340 sba_check_pdir(struct ioc *ioc, char *msg)
342 u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]);
343 u64 *rptr = (u64 *) ioc->res_map; /* resource map ptr */
344 u64 *pptr = ioc->pdir_base; /* pdir ptr */
347 while (rptr < rptr_end) {
349 int rcnt; /* number of bits we might check */
355 /* Get last byte and highest bit from that */
356 u32 pde = ((u32)((*pptr >> (63)) & 0x1));
357 if ((rval & 0x1) ^ pde)
360 ** BUMMER! -- res_map != pdir --
361 ** Dump rval and matching pdir entries
363 sba_dump_pdir_entry(ioc, msg, pide);
367 rval >>= 1; /* try the next bit */
371 rptr++; /* look at next word of res_map */
373 /* It'd be nice if we always got here :^) */
379 * sba_dump_sg - debugging only - print Scatter-Gather list
380 * @ioc: IO MMU structure which owns the pdir we are interested in.
381 * @startsg: head of the SG list
382 * @nents: number of entries in SG list
384 * print the SG list so we can verify it's correct by hand.
387 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
389 while (nents-- > 0) {
390 printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents,
391 startsg->dma_address, startsg->dma_length,
392 sba_sg_address(startsg));
398 sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
400 struct scatterlist *the_sg = startsg;
401 int the_nents = nents;
403 while (the_nents-- > 0) {
404 if (sba_sg_address(the_sg) == 0x0UL)
405 sba_dump_sg(NULL, startsg, nents);
410 #endif /* ASSERT_PDIR_SANITY */
415 /**************************************************************
417 * I/O Pdir Resource Management
419 * Bits set in the resource map are in use.
420 * Each bit can represent a number of pages.
421 * LSbs represent lower addresses (IOVA's).
423 ***************************************************************/
424 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
426 /* Convert from IOVP to IOVA and vice versa. */
427 #define SBA_IOVA(ioc,iovp,offset) ((ioc->ibase) | (iovp) | (offset))
428 #define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase))
430 #define PDIR_ENTRY_SIZE sizeof(u64)
432 #define PDIR_INDEX(iovp) ((iovp)>>iovp_shift)
434 #define RESMAP_MASK(n) ~(~0UL << (n))
435 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
439 * For most cases the normal get_order is sufficient, however it limits us
440 * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity.
441 * It only incurs about 1 clock cycle to use this one with the static variable
442 * and makes the code more intuitive.
444 static SBA_INLINE int
445 get_iovp_order (unsigned long size)
447 long double d = size - 1;
450 order = ia64_getf_exp(d);
451 order = order - iovp_shift - 0xffff + 1;
458 * sba_search_bitmap - find free space in IO PDIR resource bitmap
459 * @ioc: IO MMU structure which owns the pdir we are interested in.
460 * @bits_wanted: number of entries we need.
462 * Find consecutive free bits in resource bitmap.
463 * Each bit represents one entry in the IO Pdir.
464 * Cool perf optimization: search for log2(size) bits at a time.
466 static SBA_INLINE unsigned long
467 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
469 unsigned long *res_ptr = ioc->res_hint;
470 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
471 unsigned long pide = ~0UL;
473 ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
474 ASSERT(res_ptr < res_end);
477 * N.B. REO/Grande defect AR2305 can cause TLB fetch timeouts
478 * if a TLB entry is purged while in use. sba_mark_invalid()
479 * purges IOTLB entries in power-of-two sizes, so we also
480 * allocate IOVA space in power-of-two sizes.
482 bits_wanted = 1UL << get_iovp_order(bits_wanted << iovp_shift);
484 if (likely(bits_wanted == 1)) {
485 unsigned int bitshiftcnt;
486 for(; res_ptr < res_end ; res_ptr++) {
487 if (likely(*res_ptr != ~0UL)) {
488 bitshiftcnt = ffz(*res_ptr);
489 *res_ptr |= (1UL << bitshiftcnt);
490 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
491 pide <<= 3; /* convert to bit address */
493 ioc->res_bitshift = bitshiftcnt + bits_wanted;
501 if (likely(bits_wanted <= BITS_PER_LONG/2)) {
503 ** Search the resource bit map on well-aligned values.
504 ** "o" is the alignment.
505 ** We need the alignment to invalidate I/O TLB using
506 ** SBA HW features in the unmap path.
508 unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift);
509 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
510 unsigned long mask, base_mask;
512 base_mask = RESMAP_MASK(bits_wanted);
513 mask = base_mask << bitshiftcnt;
515 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
516 for(; res_ptr < res_end ; res_ptr++)
518 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
520 for (; mask ; mask <<= o, bitshiftcnt += o) {
521 if(0 == ((*res_ptr) & mask)) {
522 *res_ptr |= mask; /* mark resources busy! */
523 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
524 pide <<= 3; /* convert to bit address */
526 ioc->res_bitshift = bitshiftcnt + bits_wanted;
540 qwords = bits_wanted >> 6; /* /64 */
541 bits = bits_wanted - (qwords * BITS_PER_LONG);
543 end = res_end - qwords;
545 for (; res_ptr < end; res_ptr++) {
546 for (i = 0 ; i < qwords ; i++) {
550 if (bits && res_ptr[i] && (__ffs(res_ptr[i]) < bits))
553 /* Found it, mark it */
554 for (i = 0 ; i < qwords ; i++)
556 res_ptr[i] |= RESMAP_MASK(bits);
558 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
559 pide <<= 3; /* convert to bit address */
561 ioc->res_bitshift = bits;
569 prefetch(ioc->res_map);
570 ioc->res_hint = (unsigned long *) ioc->res_map;
571 ioc->res_bitshift = 0;
575 ioc->res_hint = res_ptr;
581 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
582 * @ioc: IO MMU structure which owns the pdir we are interested in.
583 * @size: number of bytes to create a mapping for
585 * Given a size, find consecutive unmarked and then mark those bits in the
589 sba_alloc_range(struct ioc *ioc, size_t size)
591 unsigned int pages_needed = size >> iovp_shift;
592 #ifdef PDIR_SEARCH_TIMING
593 unsigned long itc_start;
598 ASSERT(pages_needed);
599 ASSERT(0 == (size & ~iovp_mask));
601 spin_lock_irqsave(&ioc->res_lock, flags);
603 #ifdef PDIR_SEARCH_TIMING
604 itc_start = ia64_get_itc();
607 ** "seek and ye shall find"...praying never hurts either...
609 pide = sba_search_bitmap(ioc, pages_needed);
610 if (unlikely(pide >= (ioc->res_size << 3))) {
611 pide = sba_search_bitmap(ioc, pages_needed);
612 if (unlikely(pide >= (ioc->res_size << 3))) {
613 #if DELAYED_RESOURCE_CNT > 0
615 ** With delayed resource freeing, we can give this one more shot. We're
616 ** getting close to being in trouble here, so do what we can to make this
619 spin_lock(&ioc->saved_lock);
620 if (ioc->saved_cnt > 0) {
621 struct sba_dma_pair *d;
622 int cnt = ioc->saved_cnt;
624 d = &(ioc->saved[ioc->saved_cnt]);
627 sba_mark_invalid(ioc, d->iova, d->size);
628 sba_free_range(ioc, d->iova, d->size);
632 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
634 spin_unlock(&ioc->saved_lock);
636 pide = sba_search_bitmap(ioc, pages_needed);
637 if (unlikely(pide >= (ioc->res_size << 3)))
638 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
641 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
647 #ifdef PDIR_SEARCH_TIMING
648 ioc->avg_search[ioc->avg_idx++] = (ia64_get_itc() - itc_start) / pages_needed;
649 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
652 prefetchw(&(ioc->pdir_base[pide]));
654 #ifdef ASSERT_PDIR_SANITY
655 /* verify the first enable bit is clear */
656 if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) {
657 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
661 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
662 __FUNCTION__, size, pages_needed, pide,
663 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
666 spin_unlock_irqrestore(&ioc->res_lock, flags);
673 * sba_free_range - unmark bits in IO PDIR resource bitmap
674 * @ioc: IO MMU structure which owns the pdir we are interested in.
675 * @iova: IO virtual address which was previously allocated.
676 * @size: number of bytes to create a mapping for
678 * clear bits in the ioc's resource map
680 static SBA_INLINE void
681 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
683 unsigned long iovp = SBA_IOVP(ioc, iova);
684 unsigned int pide = PDIR_INDEX(iovp);
685 unsigned int ridx = pide >> 3; /* convert bit to byte address */
686 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
687 int bits_not_wanted = size >> iovp_shift;
690 /* Round up to power-of-two size: see AR2305 note above */
691 bits_not_wanted = 1UL << get_iovp_order(bits_not_wanted << iovp_shift);
692 for (; bits_not_wanted > 0 ; res_ptr++) {
694 if (unlikely(bits_not_wanted > BITS_PER_LONG)) {
696 /* these mappings start 64bit aligned */
698 bits_not_wanted -= BITS_PER_LONG;
699 pide += BITS_PER_LONG;
703 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
704 m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1));
707 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", __FUNCTION__, (uint) iova, size,
708 bits_not_wanted, m, pide, res_ptr, *res_ptr);
711 ASSERT(bits_not_wanted);
712 ASSERT((*res_ptr & m) == m); /* verify same bits are set */
719 /**************************************************************
721 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
723 ***************************************************************/
726 * sba_io_pdir_entry - fill in one IO PDIR entry
727 * @pdir_ptr: pointer to IO PDIR entry
728 * @vba: Virtual CPU address of buffer to map
730 * SBA Mapping Routine
732 * Given a virtual address (vba, arg1) sba_io_pdir_entry()
733 * loads the I/O PDIR entry pointed to by pdir_ptr (arg0).
734 * Each IO Pdir entry consists of 8 bytes as shown below
738 * +-+---------------------+----------------------------------+----+--------+
739 * |V| U | PPN[39:12] | U | FF |
740 * +-+---------------------+----------------------------------+----+--------+
744 * PPN == Physical Page Number
746 * The physical address fields are filled with the results of virt_to_phys()
751 #define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL) \
752 | 0x8000000000000000ULL)
755 sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba)
757 *pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL);
761 #ifdef ENABLE_MARK_CLEAN
763 * Since DMA is i-cache coherent, any (complete) pages that were written via
764 * DMA can be marked as "clean" so that update_mmu_cache() doesn't have to
765 * flush them when they get mapped into an executable vm-area.
768 mark_clean (void *addr, size_t size)
770 unsigned long pg_addr, end;
772 pg_addr = PAGE_ALIGN((unsigned long) addr);
773 end = (unsigned long) addr + size;
774 while (pg_addr + PAGE_SIZE <= end) {
775 struct page *page = virt_to_page((void *)pg_addr);
776 set_bit(PG_arch_1, &page->flags);
777 pg_addr += PAGE_SIZE;
783 * sba_mark_invalid - invalidate one or more IO PDIR entries
784 * @ioc: IO MMU structure which owns the pdir we are interested in.
785 * @iova: IO Virtual Address mapped earlier
786 * @byte_cnt: number of bytes this mapping covers.
788 * Marking the IO PDIR entry(ies) as Invalid and invalidate
789 * corresponding IO TLB entry. The PCOM (Purge Command Register)
790 * is to purge stale entries in the IO TLB when unmapping entries.
792 * The PCOM register supports purging of multiple pages, with a minium
793 * of 1 page and a maximum of 2GB. Hardware requires the address be
794 * aligned to the size of the range being purged. The size of the range
795 * must be a power of 2. The "Cool perf optimization" in the
796 * allocation routine helps keep that true.
798 static SBA_INLINE void
799 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
801 u32 iovp = (u32) SBA_IOVP(ioc,iova);
803 int off = PDIR_INDEX(iovp);
805 /* Must be non-zero and rounded up */
806 ASSERT(byte_cnt > 0);
807 ASSERT(0 == (byte_cnt & ~iovp_mask));
809 #ifdef ASSERT_PDIR_SANITY
810 /* Assert first pdir entry is set */
811 if (!(ioc->pdir_base[off] >> 60)) {
812 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
816 if (byte_cnt <= iovp_size)
818 ASSERT(off < ioc->pdir_size);
820 iovp |= iovp_shift; /* set "size" field for PCOM */
822 #ifndef FULL_VALID_PDIR
824 ** clear I/O PDIR entry "valid" bit
825 ** Do NOT clear the rest - save it for debugging.
826 ** We should only clear bits that have previously
829 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
832 ** If we want to maintain the PDIR as valid, put in
833 ** the spill page so devices prefetching won't
834 ** cause a hard fail.
836 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
839 u32 t = get_iovp_order(byte_cnt) + iovp_shift;
842 ASSERT(t <= 31); /* 2GB! Max value of "size" field */
845 /* verify this pdir entry is enabled */
846 ASSERT(ioc->pdir_base[off] >> 63);
847 #ifndef FULL_VALID_PDIR
848 /* clear I/O Pdir entry "valid" bit first */
849 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
851 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
854 byte_cnt -= iovp_size;
855 } while (byte_cnt > 0);
858 WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM);
862 * sba_map_single - map one buffer and return IOVA for DMA
863 * @dev: instance of PCI owned by the driver that's asking.
864 * @addr: driver buffer to map.
865 * @size: number of bytes to map in driver buffer.
868 * See Documentation/DMA-mapping.txt
871 sba_map_single(struct device *dev, void *addr, size_t size, int dir)
878 #ifdef ASSERT_PDIR_SANITY
881 #ifdef ALLOW_IOV_BYPASS
882 unsigned long pci_addr = virt_to_phys(addr);
885 #ifdef ALLOW_IOV_BYPASS
886 ASSERT(to_pci_dev(dev)->dma_mask);
888 ** Check if the PCI device can DMA to ptr... if so, just return ptr
890 if (likely((pci_addr & ~to_pci_dev(dev)->dma_mask) == 0)) {
892 ** Device is bit capable of DMA'ing to the buffer...
893 ** just return the PCI address of ptr
895 DBG_BYPASS("sba_map_single() bypass mask/addr: 0x%lx/0x%lx\n",
896 to_pci_dev(dev)->dma_mask, pci_addr);
903 prefetch(ioc->res_hint);
906 ASSERT(size <= DMA_CHUNK_SIZE);
908 /* save offset bits */
909 offset = ((dma_addr_t) (long) addr) & ~iovp_mask;
911 /* round up to nearest iovp_size */
912 size = (size + offset + ~iovp_mask) & iovp_mask;
914 #ifdef ASSERT_PDIR_SANITY
915 spin_lock_irqsave(&ioc->res_lock, flags);
916 if (sba_check_pdir(ioc,"Check before sba_map_single()"))
917 panic("Sanity check failed");
918 spin_unlock_irqrestore(&ioc->res_lock, flags);
921 pide = sba_alloc_range(ioc, size);
923 iovp = (dma_addr_t) pide << iovp_shift;
925 DBG_RUN("%s() 0x%p -> 0x%lx\n",
926 __FUNCTION__, addr, (long) iovp | offset);
928 pdir_start = &(ioc->pdir_base[pide]);
931 ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
932 sba_io_pdir_entry(pdir_start, (unsigned long) addr);
934 DBG_RUN(" pdir 0x%p %lx\n", pdir_start, *pdir_start);
940 /* force pdir update */
943 /* form complete address */
944 #ifdef ASSERT_PDIR_SANITY
945 spin_lock_irqsave(&ioc->res_lock, flags);
946 sba_check_pdir(ioc,"Check after sba_map_single()");
947 spin_unlock_irqrestore(&ioc->res_lock, flags);
949 return SBA_IOVA(ioc, iovp, offset);
953 * sba_unmap_single - unmap one IOVA and free resources
954 * @dev: instance of PCI owned by the driver that's asking.
955 * @iova: IOVA of driver buffer previously mapped.
956 * @size: number of bytes mapped in driver buffer.
959 * See Documentation/DMA-mapping.txt
961 void sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, int dir)
964 #if DELAYED_RESOURCE_CNT > 0
965 struct sba_dma_pair *d;
973 #ifdef ALLOW_IOV_BYPASS
974 if (likely((iova & ioc->imask) != ioc->ibase)) {
976 ** Address does not fall w/in IOVA, must be bypassing
978 DBG_BYPASS("sba_unmap_single() bypass addr: 0x%lx\n", iova);
980 #ifdef ENABLE_MARK_CLEAN
981 if (dir == DMA_FROM_DEVICE) {
982 mark_clean(phys_to_virt(iova), size);
988 offset = iova & ~iovp_mask;
990 DBG_RUN("%s() iovp 0x%lx/%x\n",
991 __FUNCTION__, (long) iova, size);
993 iova ^= offset; /* clear offset bits */
995 size = ROUNDUP(size, iovp_size);
998 #if DELAYED_RESOURCE_CNT > 0
999 spin_lock_irqsave(&ioc->saved_lock, flags);
1000 d = &(ioc->saved[ioc->saved_cnt]);
1003 if (unlikely(++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT)) {
1004 int cnt = ioc->saved_cnt;
1005 spin_lock(&ioc->res_lock);
1007 sba_mark_invalid(ioc, d->iova, d->size);
1008 sba_free_range(ioc, d->iova, d->size);
1012 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1013 spin_unlock(&ioc->res_lock);
1015 spin_unlock_irqrestore(&ioc->saved_lock, flags);
1016 #else /* DELAYED_RESOURCE_CNT == 0 */
1017 spin_lock_irqsave(&ioc->res_lock, flags);
1018 sba_mark_invalid(ioc, iova, size);
1019 sba_free_range(ioc, iova, size);
1020 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1021 spin_unlock_irqrestore(&ioc->res_lock, flags);
1022 #endif /* DELAYED_RESOURCE_CNT == 0 */
1023 #ifdef ENABLE_MARK_CLEAN
1024 if (dir == DMA_FROM_DEVICE) {
1025 u32 iovp = (u32) SBA_IOVP(ioc,iova);
1026 int off = PDIR_INDEX(iovp);
1029 if (size <= iovp_size) {
1030 addr = phys_to_virt(ioc->pdir_base[off] &
1031 ~0xE000000000000FFFULL);
1032 mark_clean(addr, size);
1034 size_t byte_cnt = size;
1037 addr = phys_to_virt(ioc->pdir_base[off] &
1038 ~0xE000000000000FFFULL);
1039 mark_clean(addr, min(byte_cnt, iovp_size));
1041 byte_cnt -= iovp_size;
1043 } while (byte_cnt > 0);
1051 * sba_alloc_coherent - allocate/map shared mem for DMA
1052 * @dev: instance of PCI owned by the driver that's asking.
1053 * @size: number of bytes mapped in driver buffer.
1054 * @dma_handle: IOVA of new buffer.
1056 * See Documentation/DMA-mapping.txt
1059 sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, int flags)
1070 page = alloc_pages_node(ioc->node == MAX_NUMNODES ?
1071 numa_node_id() : ioc->node, flags,
1074 if (unlikely(!page))
1077 addr = page_address(page);
1080 addr = (void *) __get_free_pages(flags, get_order(size));
1082 if (unlikely(!addr))
1085 memset(addr, 0, size);
1086 *dma_handle = virt_to_phys(addr);
1088 #ifdef ALLOW_IOV_BYPASS
1089 ASSERT(dev->coherent_dma_mask);
1091 ** Check if the PCI device can DMA to ptr... if so, just return ptr
1093 if (likely((*dma_handle & ~dev->coherent_dma_mask) == 0)) {
1094 DBG_BYPASS("sba_alloc_coherent() bypass mask/addr: 0x%lx/0x%lx\n",
1095 dev->coherent_dma_mask, *dma_handle);
1102 * If device can't bypass or bypass is disabled, pass the 32bit fake
1103 * device to map single to get an iova mapping.
1105 *dma_handle = sba_map_single(&ioc->sac_only_dev->dev, addr, size, 0);
1112 * sba_free_coherent - free/unmap shared mem for DMA
1113 * @dev: instance of PCI owned by the driver that's asking.
1114 * @size: number of bytes mapped in driver buffer.
1115 * @vaddr: virtual address IOVA of "consistent" buffer.
1116 * @dma_handler: IO virtual address of "consistent" buffer.
1118 * See Documentation/DMA-mapping.txt
1120 void sba_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
1122 sba_unmap_single(dev, dma_handle, size, 0);
1123 free_pages((unsigned long) vaddr, get_order(size));
1128 ** Since 0 is a valid pdir_base index value, can't use that
1129 ** to determine if a value is valid or not. Use a flag to indicate
1130 ** the SG list entry contains a valid pdir index.
1132 #define PIDE_FLAG 0x1UL
1134 #ifdef DEBUG_LARGE_SG_ENTRIES
1135 int dump_run_sg = 0;
1140 * sba_fill_pdir - write allocated SG entries into IO PDIR
1141 * @ioc: IO MMU structure which owns the pdir we are interested in.
1142 * @startsg: list of IOVA/size pairs
1143 * @nents: number of entries in startsg list
1145 * Take preprocessed SG list and write corresponding entries
1149 static SBA_INLINE int
1152 struct scatterlist *startsg,
1155 struct scatterlist *dma_sg = startsg; /* pointer to current DMA */
1158 unsigned long dma_offset = 0;
1161 while (nents-- > 0) {
1162 int cnt = startsg->dma_length;
1163 startsg->dma_length = 0;
1165 #ifdef DEBUG_LARGE_SG_ENTRIES
1167 printk(" %2d : %08lx/%05x %p\n",
1168 nents, startsg->dma_address, cnt,
1169 sba_sg_address(startsg));
1171 DBG_RUN_SG(" %d : %08lx/%05x %p\n",
1172 nents, startsg->dma_address, cnt,
1173 sba_sg_address(startsg));
1176 ** Look for the start of a new DMA stream
1178 if (startsg->dma_address & PIDE_FLAG) {
1179 u32 pide = startsg->dma_address & ~PIDE_FLAG;
1180 dma_offset = (unsigned long) pide & ~iovp_mask;
1181 startsg->dma_address = 0;
1183 dma_sg->dma_address = pide | ioc->ibase;
1184 pdirp = &(ioc->pdir_base[pide >> iovp_shift]);
1189 ** Look for a VCONTIG chunk
1192 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1195 /* Since multiple Vcontig blocks could make up
1196 ** one DMA stream, *add* cnt to dma_len.
1198 dma_sg->dma_length += cnt;
1200 dma_offset=0; /* only want offset on first chunk */
1201 cnt = ROUNDUP(cnt, iovp_size);
1203 sba_io_pdir_entry(pdirp, vaddr);
1211 /* force pdir update */
1214 #ifdef DEBUG_LARGE_SG_ENTRIES
1222 ** Two address ranges are DMA contiguous *iff* "end of prev" and
1223 ** "start of next" are both on an IOV page boundary.
1225 ** (shift left is a quick trick to mask off upper bits)
1227 #define DMA_CONTIG(__X, __Y) \
1228 (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL)
1232 * sba_coalesce_chunks - preprocess the SG list
1233 * @ioc: IO MMU structure which owns the pdir we are interested in.
1234 * @startsg: list of IOVA/size pairs
1235 * @nents: number of entries in startsg list
1237 * First pass is to walk the SG list and determine where the breaks are
1238 * in the DMA stream. Allocates PDIR entries but does not fill them.
1239 * Returns the number of DMA chunks.
1241 * Doing the fill separate from the coalescing/allocation keeps the
1242 * code simpler. Future enhancement could make one pass through
1243 * the sglist do both.
1245 static SBA_INLINE int
1246 sba_coalesce_chunks( struct ioc *ioc,
1247 struct scatterlist *startsg,
1250 struct scatterlist *vcontig_sg; /* VCONTIG chunk head */
1251 unsigned long vcontig_len; /* len of VCONTIG chunk */
1252 unsigned long vcontig_end;
1253 struct scatterlist *dma_sg; /* next DMA stream head */
1254 unsigned long dma_offset, dma_len; /* start/len of DMA stream */
1258 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1261 ** Prepare for first/next DMA stream
1263 dma_sg = vcontig_sg = startsg;
1264 dma_len = vcontig_len = vcontig_end = startsg->length;
1265 vcontig_end += vaddr;
1266 dma_offset = vaddr & ~iovp_mask;
1268 /* PARANOID: clear entries */
1269 startsg->dma_address = startsg->dma_length = 0;
1272 ** This loop terminates one iteration "early" since
1273 ** it's always looking one "ahead".
1275 while (--nents > 0) {
1276 unsigned long vaddr; /* tmp */
1281 startsg->dma_address = startsg->dma_length = 0;
1283 /* catch brokenness in SCSI layer */
1284 ASSERT(startsg->length <= DMA_CHUNK_SIZE);
1287 ** First make sure current dma stream won't
1288 ** exceed DMA_CHUNK_SIZE if we coalesce the
1291 if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask)
1296 ** Then look for virtually contiguous blocks.
1298 ** append the next transaction?
1300 vaddr = (unsigned long) sba_sg_address(startsg);
1301 if (vcontig_end == vaddr)
1303 vcontig_len += startsg->length;
1304 vcontig_end += startsg->length;
1305 dma_len += startsg->length;
1309 #ifdef DEBUG_LARGE_SG_ENTRIES
1310 dump_run_sg = (vcontig_len > iovp_size);
1314 ** Not virtually contigous.
1315 ** Terminate prev chunk.
1316 ** Start a new chunk.
1318 ** Once we start a new VCONTIG chunk, dma_offset
1319 ** can't change. And we need the offset from the first
1320 ** chunk - not the last one. Ergo Successive chunks
1321 ** must start on page boundaries and dove tail
1322 ** with it's predecessor.
1324 vcontig_sg->dma_length = vcontig_len;
1326 vcontig_sg = startsg;
1327 vcontig_len = startsg->length;
1330 ** 3) do the entries end/start on page boundaries?
1331 ** Don't update vcontig_end until we've checked.
1333 if (DMA_CONTIG(vcontig_end, vaddr))
1335 vcontig_end = vcontig_len + vaddr;
1336 dma_len += vcontig_len;
1344 ** End of DMA Stream
1345 ** Terminate last VCONTIG block.
1346 ** Allocate space for DMA stream.
1348 vcontig_sg->dma_length = vcontig_len;
1349 dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask;
1350 ASSERT(dma_len <= DMA_CHUNK_SIZE);
1351 dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG
1352 | (sba_alloc_range(ioc, dma_len) << iovp_shift)
1362 * sba_map_sg - map Scatter/Gather list
1363 * @dev: instance of PCI owned by the driver that's asking.
1364 * @sglist: array of buffer/length pairs
1365 * @nents: number of entries in list
1366 * @dir: R/W or both.
1368 * See Documentation/DMA-mapping.txt
1370 int sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, int dir)
1373 int coalesced, filled = 0;
1374 #ifdef ASSERT_PDIR_SANITY
1375 unsigned long flags;
1377 #ifdef ALLOW_IOV_BYPASS_SG
1378 struct scatterlist *sg;
1381 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1385 #ifdef ALLOW_IOV_BYPASS_SG
1386 ASSERT(to_pci_dev(dev)->dma_mask);
1387 if (likely((ioc->dma_mask & ~to_pci_dev(dev)->dma_mask) == 0)) {
1388 for (sg = sglist ; filled < nents ; filled++, sg++){
1389 sg->dma_length = sg->length;
1390 sg->dma_address = virt_to_phys(sba_sg_address(sg));
1395 /* Fast path single entry scatterlists. */
1397 sglist->dma_length = sglist->length;
1398 sglist->dma_address = sba_map_single(dev, sba_sg_address(sglist), sglist->length, dir);
1402 #ifdef ASSERT_PDIR_SANITY
1403 spin_lock_irqsave(&ioc->res_lock, flags);
1404 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1406 sba_dump_sg(ioc, sglist, nents);
1407 panic("Check before sba_map_sg()");
1409 spin_unlock_irqrestore(&ioc->res_lock, flags);
1412 prefetch(ioc->res_hint);
1415 ** First coalesce the chunks and allocate I/O pdir space
1417 ** If this is one DMA stream, we can properly map using the
1418 ** correct virtual address associated with each DMA page.
1419 ** w/o this association, we wouldn't have coherent DMA!
1420 ** Access to the virtual address is what forces a two pass algorithm.
1422 coalesced = sba_coalesce_chunks(ioc, sglist, nents);
1425 ** Program the I/O Pdir
1427 ** map the virtual addresses to the I/O Pdir
1428 ** o dma_address will contain the pdir index
1429 ** o dma_len will contain the number of bytes to map
1430 ** o address contains the virtual address.
1432 filled = sba_fill_pdir(ioc, sglist, nents);
1434 #ifdef ASSERT_PDIR_SANITY
1435 spin_lock_irqsave(&ioc->res_lock, flags);
1436 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1438 sba_dump_sg(ioc, sglist, nents);
1439 panic("Check after sba_map_sg()\n");
1441 spin_unlock_irqrestore(&ioc->res_lock, flags);
1444 ASSERT(coalesced == filled);
1445 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1452 * sba_unmap_sg - unmap Scatter/Gather list
1453 * @dev: instance of PCI owned by the driver that's asking.
1454 * @sglist: array of buffer/length pairs
1455 * @nents: number of entries in list
1456 * @dir: R/W or both.
1458 * See Documentation/DMA-mapping.txt
1460 void sba_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
1462 #ifdef ASSERT_PDIR_SANITY
1464 unsigned long flags;
1467 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1468 __FUNCTION__, nents, sba_sg_address(sglist), sglist->length);
1470 #ifdef ASSERT_PDIR_SANITY
1474 spin_lock_irqsave(&ioc->res_lock, flags);
1475 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1476 spin_unlock_irqrestore(&ioc->res_lock, flags);
1479 while (nents && sglist->dma_length) {
1481 sba_unmap_single(dev, sglist->dma_address, sglist->dma_length, dir);
1486 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1488 #ifdef ASSERT_PDIR_SANITY
1489 spin_lock_irqsave(&ioc->res_lock, flags);
1490 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1491 spin_unlock_irqrestore(&ioc->res_lock, flags);
1496 /**************************************************************
1498 * Initialization and claim
1500 ***************************************************************/
1503 ioc_iova_init(struct ioc *ioc)
1507 struct pci_dev *device = NULL;
1508 #ifdef FULL_VALID_PDIR
1509 unsigned long index;
1513 ** Firmware programs the base and size of a "safe IOVA space"
1514 ** (one that doesn't overlap memory or LMMIO space) in the
1515 ** IBASE and IMASK registers.
1517 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL;
1518 ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL;
1520 ioc->iov_size = ~ioc->imask + 1;
1522 DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n",
1523 __FUNCTION__, ioc->ioc_hpa, ioc->ibase, ioc->imask,
1524 ioc->iov_size >> 20);
1526 switch (iovp_size) {
1527 case 4*1024: tcnfg = 0; break;
1528 case 8*1024: tcnfg = 1; break;
1529 case 16*1024: tcnfg = 2; break;
1530 case 64*1024: tcnfg = 3; break;
1532 panic(PFX "Unsupported IOTLB page size %ldK",
1536 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1538 ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE;
1539 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1540 get_order(ioc->pdir_size));
1541 if (!ioc->pdir_base)
1542 panic(PFX "Couldn't allocate I/O Page Table\n");
1544 memset(ioc->pdir_base, 0, ioc->pdir_size);
1546 DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __FUNCTION__,
1547 iovp_size >> 10, ioc->pdir_base, ioc->pdir_size);
1549 ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base);
1550 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1553 ** If an AGP device is present, only use half of the IOV space
1554 ** for PCI DMA. Unfortunately we can't know ahead of time
1555 ** whether GART support will actually be used, for now we
1556 ** can just key on an AGP device found in the system.
1557 ** We program the next pdir index after we stop w/ a key for
1558 ** the GART code to handshake on.
1560 for_each_pci_dev(device)
1561 agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP);
1563 if (agp_found && reserve_sba_gart) {
1564 printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n",
1565 ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2);
1566 ioc->pdir_size /= 2;
1567 ((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE;
1569 #ifdef FULL_VALID_PDIR
1571 ** Check to see if the spill page has been allocated, we don't need more than
1572 ** one across multiple SBAs.
1574 if (!prefetch_spill_page) {
1575 char *spill_poison = "SBAIOMMU POISON";
1576 int poison_size = 16;
1577 void *poison_addr, *addr;
1579 addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size));
1581 panic(PFX "Couldn't allocate PDIR spill page\n");
1584 for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size)
1585 memcpy(poison_addr, spill_poison, poison_size);
1587 prefetch_spill_page = virt_to_phys(addr);
1589 DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __FUNCTION__, prefetch_spill_page);
1592 ** Set all the PDIR entries valid w/ the spill page as the target
1594 for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++)
1595 ((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page);
1598 /* Clear I/O TLB of any possible entries */
1599 WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM);
1600 READ_REG(ioc->ioc_hpa + IOC_PCOM);
1602 /* Enable IOVA translation */
1603 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1604 READ_REG(ioc->ioc_hpa + IOC_IBASE);
1608 ioc_resource_init(struct ioc *ioc)
1610 spin_lock_init(&ioc->res_lock);
1611 #if DELAYED_RESOURCE_CNT > 0
1612 spin_lock_init(&ioc->saved_lock);
1615 /* resource map size dictated by pdir_size */
1616 ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */
1617 ioc->res_size >>= 3; /* convert bit count to byte count */
1618 DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size);
1620 ioc->res_map = (char *) __get_free_pages(GFP_KERNEL,
1621 get_order(ioc->res_size));
1623 panic(PFX "Couldn't allocate resource map\n");
1625 memset(ioc->res_map, 0, ioc->res_size);
1626 /* next available IOVP - circular search */
1627 ioc->res_hint = (unsigned long *) ioc->res_map;
1629 #ifdef ASSERT_PDIR_SANITY
1630 /* Mark first bit busy - ie no IOVA 0 */
1631 ioc->res_map[0] = 0x1;
1632 ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE;
1634 #ifdef FULL_VALID_PDIR
1635 /* Mark the last resource used so we don't prefetch beyond IOVA space */
1636 ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */
1637 ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF
1638 | prefetch_spill_page);
1641 DBG_INIT("%s() res_map %x %p\n", __FUNCTION__,
1642 ioc->res_size, (void *) ioc->res_map);
1646 ioc_sac_init(struct ioc *ioc)
1648 struct pci_dev *sac = NULL;
1649 struct pci_controller *controller = NULL;
1652 * pci_alloc_coherent() must return a DMA address which is
1653 * SAC (single address cycle) addressable, so allocate a
1654 * pseudo-device to enforce that.
1656 sac = kmalloc(sizeof(*sac), GFP_KERNEL);
1658 panic(PFX "Couldn't allocate struct pci_dev");
1659 memset(sac, 0, sizeof(*sac));
1661 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
1663 panic(PFX "Couldn't allocate struct pci_controller");
1664 memset(controller, 0, sizeof(*controller));
1666 controller->iommu = ioc;
1667 sac->sysdata = controller;
1668 sac->dma_mask = 0xFFFFFFFFUL;
1670 sac->dev.bus = &pci_bus_type;
1672 ioc->sac_only_dev = sac;
1676 ioc_zx1_init(struct ioc *ioc)
1678 unsigned long rope_config;
1681 if (ioc->rev < 0x20)
1682 panic(PFX "IOC 2.0 or later required for IOMMU support\n");
1684 /* 38 bit memory controller + extra bit for range displaced by MMIO */
1685 ioc->dma_mask = (0x1UL << 39) - 1;
1688 ** Clear ROPE(N)_CONFIG AO bit.
1689 ** Disables "NT Ordering" (~= !"Relaxed Ordering")
1690 ** Overrides bit 1 in DMA Hint Sets.
1691 ** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701.
1693 for (i=0; i<(8*8); i+=8) {
1694 rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i);
1695 rope_config &= ~IOC_ROPE_AO;
1696 WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i);
1700 typedef void (initfunc)(struct ioc *);
1708 static struct ioc_iommu ioc_iommu_info[] __initdata = {
1709 { ZX1_IOC_ID, "zx1", ioc_zx1_init },
1710 { SX1000_IOC_ID, "sx1000", NULL },
1713 static struct ioc * __init
1714 ioc_init(u64 hpa, void *handle)
1717 struct ioc_iommu *info;
1719 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
1723 memset(ioc, 0, sizeof(*ioc));
1725 ioc->next = ioc_list;
1728 ioc->handle = handle;
1729 ioc->ioc_hpa = ioremap(hpa, 0x1000);
1731 ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID);
1732 ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL;
1733 ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL; /* conservative */
1735 for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) {
1736 if (ioc->func_id == info->func_id) {
1737 ioc->name = info->name;
1743 iovp_size = (1 << iovp_shift);
1744 iovp_mask = ~(iovp_size - 1);
1746 DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __FUNCTION__,
1747 PAGE_SIZE >> 10, iovp_size >> 10);
1750 ioc->name = kmalloc(24, GFP_KERNEL);
1752 sprintf((char *) ioc->name, "Unknown (%04x:%04x)",
1753 ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF);
1755 ioc->name = "Unknown";
1759 ioc_resource_init(ioc);
1762 if ((long) ~iovp_mask > (long) ia64_max_iommu_merge_mask)
1763 ia64_max_iommu_merge_mask = ~iovp_mask;
1765 printk(KERN_INFO PFX
1766 "%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n",
1767 ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF,
1768 hpa, ioc->iov_size >> 20, ioc->ibase);
1775 /**************************************************************************
1777 ** SBA initialization code (HW and SW)
1779 ** o identify SBA chip itself
1780 ** o FIXME: initialize DMA hints for reasonable defaults
1782 **************************************************************************/
1784 #ifdef CONFIG_PROC_FS
1786 ioc_start(struct seq_file *s, loff_t *pos)
1791 for (ioc = ioc_list; ioc; ioc = ioc->next)
1799 ioc_next(struct seq_file *s, void *v, loff_t *pos)
1801 struct ioc *ioc = v;
1808 ioc_stop(struct seq_file *s, void *v)
1813 ioc_show(struct seq_file *s, void *v)
1815 struct ioc *ioc = v;
1816 unsigned long *res_ptr = (unsigned long *)ioc->res_map;
1819 seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n",
1820 ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF));
1822 if (ioc->node != MAX_NUMNODES)
1823 seq_printf(s, "NUMA node : %d\n", ioc->node);
1825 seq_printf(s, "IOVA size : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024));
1826 seq_printf(s, "IOVA page size : %ld kb\n", iovp_size/1024);
1828 for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr)
1829 used += hweight64(*res_ptr);
1831 seq_printf(s, "PDIR size : %d entries\n", ioc->pdir_size >> 3);
1832 seq_printf(s, "PDIR used : %d entries\n", used);
1834 #ifdef PDIR_SEARCH_TIMING
1836 unsigned long i = 0, avg = 0, min, max;
1837 min = max = ioc->avg_search[0];
1838 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1839 avg += ioc->avg_search[i];
1840 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1841 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1843 avg /= SBA_SEARCH_SAMPLE;
1844 seq_printf(s, "Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles/IOVA page)\n",
1848 #ifndef ALLOW_IOV_BYPASS
1849 seq_printf(s, "IOVA bypass disabled\n");
1854 static struct seq_operations ioc_seq_ops = {
1862 ioc_open(struct inode *inode, struct file *file)
1864 return seq_open(file, &ioc_seq_ops);
1867 static struct file_operations ioc_fops = {
1870 .llseek = seq_lseek,
1871 .release = seq_release
1877 struct proc_dir_entry *dir, *entry;
1879 dir = proc_mkdir("bus/mckinley", NULL);
1883 entry = create_proc_entry(ioc_list->name, 0, dir);
1885 entry->proc_fops = &ioc_fops;
1890 sba_connect_bus(struct pci_bus *bus)
1892 acpi_handle handle, parent;
1896 if (!PCI_CONTROLLER(bus))
1897 panic(PFX "no sysdata on bus %d!\n", bus->number);
1899 if (PCI_CONTROLLER(bus)->iommu)
1902 handle = PCI_CONTROLLER(bus)->acpi_handle;
1907 * The IOC scope encloses PCI root bridges in the ACPI
1908 * namespace, so work our way out until we find an IOC we
1909 * claimed previously.
1912 for (ioc = ioc_list; ioc; ioc = ioc->next)
1913 if (ioc->handle == handle) {
1914 PCI_CONTROLLER(bus)->iommu = ioc;
1918 status = acpi_get_parent(handle, &parent);
1920 } while (ACPI_SUCCESS(status));
1922 printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number);
1927 sba_map_ioc_to_node(struct ioc *ioc, acpi_handle handle)
1929 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
1930 union acpi_object *obj;
1931 acpi_handle phandle;
1934 ioc->node = MAX_NUMNODES;
1937 * Check for a _PXM on this node first. We don't typically see
1938 * one here, so we'll end up getting it from the parent.
1940 if (ACPI_FAILURE(acpi_evaluate_object(handle, "_PXM", NULL, &buffer))) {
1941 if (ACPI_FAILURE(acpi_get_parent(handle, &phandle)))
1944 /* Reset the acpi buffer */
1945 buffer.length = ACPI_ALLOCATE_BUFFER;
1946 buffer.pointer = NULL;
1948 if (ACPI_FAILURE(acpi_evaluate_object(phandle, "_PXM", NULL,
1953 if (!buffer.length || !buffer.pointer)
1956 obj = buffer.pointer;
1958 if (obj->type != ACPI_TYPE_INTEGER ||
1959 obj->integer.value >= MAX_PXM_DOMAINS) {
1960 acpi_os_free(buffer.pointer);
1964 node = pxm_to_nid_map[obj->integer.value];
1965 acpi_os_free(buffer.pointer);
1967 if (node >= MAX_NUMNODES || !node_online(node))
1974 #define sba_map_ioc_to_node(ioc, handle)
1978 acpi_sba_ioc_add(struct acpi_device *device)
1983 struct acpi_buffer buffer;
1984 struct acpi_device_info *dev_info;
1986 status = hp_acpi_csr_space(device->handle, &hpa, &length);
1987 if (ACPI_FAILURE(status))
1990 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
1991 status = acpi_get_object_info(device->handle, &buffer);
1992 if (ACPI_FAILURE(status))
1994 dev_info = buffer.pointer;
1997 * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI
1998 * root bridges, and its CSR space includes the IOC function.
2000 if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0) {
2001 hpa += ZX1_IOC_OFFSET;
2002 /* zx1 based systems default to kernel page size iommu pages */
2004 iovp_shift = min(PAGE_SHIFT, 16);
2006 ACPI_MEM_FREE(dev_info);
2009 * default anything not caught above or specified on cmdline to 4k
2015 ioc = ioc_init(hpa, device->handle);
2019 /* setup NUMA node association */
2020 sba_map_ioc_to_node(ioc, device->handle);
2024 static struct acpi_driver acpi_sba_ioc_driver = {
2025 .name = "IOC IOMMU Driver",
2026 .ids = "HWP0001,HWP0004",
2028 .add = acpi_sba_ioc_add,
2035 acpi_bus_register_driver(&acpi_sba_ioc_driver);
2041 struct pci_bus *b = NULL;
2042 while ((b = pci_find_next_bus(b)) != NULL)
2047 #ifdef CONFIG_PROC_FS
2053 subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */
2055 extern void dig_setup(char**);
2057 * MAX_DMA_ADDRESS needs to be setup prior to paging_init to do any good,
2058 * so we use the platform_setup hook to fix it up.
2061 sba_setup(char **cmdline_p)
2063 MAX_DMA_ADDRESS = ~0UL;
2064 dig_setup(cmdline_p);
2068 nosbagart(char *str)
2070 reserve_sba_gart = 0;
2075 sba_dma_supported (struct device *dev, u64 mask)
2077 /* make sure it's at least 32bit capable */
2078 return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
2082 sba_dma_mapping_error (dma_addr_t dma_addr)
2087 __setup("nosbagart", nosbagart);
2090 sba_page_override(char *str)
2092 unsigned long page_size;
2094 page_size = memparse(str, &str);
2095 switch (page_size) {
2100 iovp_shift = ffs(page_size) - 1;
2103 printk("%s: unknown/unsupported iommu page size %ld\n",
2104 __FUNCTION__, page_size);
2110 __setup("sbapagesize=",sba_page_override);
2112 EXPORT_SYMBOL(sba_dma_mapping_error);
2113 EXPORT_SYMBOL(sba_map_single);
2114 EXPORT_SYMBOL(sba_unmap_single);
2115 EXPORT_SYMBOL(sba_map_sg);
2116 EXPORT_SYMBOL(sba_unmap_sg);
2117 EXPORT_SYMBOL(sba_dma_supported);
2118 EXPORT_SYMBOL(sba_alloc_coherent);
2119 EXPORT_SYMBOL(sba_free_coherent);