2 ** IA64 System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2002-2004 Alex Williamson
5 ** (c) Copyright 2002-2003 Grant Grundler
6 ** (c) Copyright 2002-2004 Hewlett-Packard Company
8 ** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code)
9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
11 ** This program is free software; you can redistribute it and/or modify
12 ** it under the terms of the GNU General Public License as published by
13 ** the Free Software Foundation; either version 2 of the License, or
14 ** (at your option) any later version.
17 ** This module initializes the IOC (I/O Controller) found on HP
18 ** McKinley machines and their successors.
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
30 #include <linux/string.h>
31 #include <linux/pci.h>
32 #include <linux/proc_fs.h>
33 #include <linux/seq_file.h>
34 #include <linux/acpi.h>
35 #include <linux/efi.h>
37 #include <asm/delay.h> /* ia64_get_itc() */
39 #include <asm/page.h> /* PAGE_OFFSET */
41 #include <asm/system.h> /* wmb() */
42 #include <asm/bitops.h> /* hweight64() */
44 #include <asm/acpi-ext.h>
49 ** Enabling timing search of the pdir resource map. Output in /proc.
50 ** Disabled by default to optimize performance.
52 #undef PDIR_SEARCH_TIMING
55 ** This option allows cards capable of 64bit DMA to bypass the IOMMU. If
56 ** not defined, all DMA will be 32bit and go through the TLB.
57 ** There's potentially a conflict in the bio merge code with us
58 ** advertising an iommu, but then bypassing it. Since I/O MMU bypassing
59 ** appears to give more performance than bio-level virtual merging, we'll
60 ** do the former for now. NOTE: BYPASS_SG also needs to be undef'd to
61 ** completely restrict DMA to the IOMMU.
63 #define ALLOW_IOV_BYPASS
66 ** This option specifically allows/disallows bypassing scatterlists with
67 ** multiple entries. Coalescing these entries can allow better DMA streaming
68 ** and in some cases shows better performance than entirely bypassing the
69 ** IOMMU. Performance increase on the order of 1-2% sequential output/input
70 ** using bonnie++ on a RAID0 MD device (sym2 & mpt).
72 #undef ALLOW_IOV_BYPASS_SG
75 ** If a device prefetches beyond the end of a valid pdir entry, it will cause
76 ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
77 ** disconnect on 4k boundaries and prevent such issues. If the device is
78 ** particularly agressive, this option will keep the entire pdir valid such
79 ** that prefetching will hit a valid address. This could severely impact
80 ** error containment, and is therefore off by default. The page that is
81 ** used for spill-over is poisoned, so that should help debugging somewhat.
83 #undef FULL_VALID_PDIR
85 #define ENABLE_MARK_CLEAN
88 ** The number of debug flags is a clue - this code is fragile. NOTE: since
89 ** tightening the use of res_lock the resource bitmap and actual pdir are no
90 ** longer guaranteed to stay in sync. The sanity checking code isn't going to
95 #undef DEBUG_SBA_RUN_SG
96 #undef DEBUG_SBA_RESOURCE
97 #undef ASSERT_PDIR_SANITY
98 #undef DEBUG_LARGE_SG_ENTRIES
101 #if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY)
102 #error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive
105 #define SBA_INLINE __inline__
106 /* #define SBA_INLINE */
108 #ifdef DEBUG_SBA_INIT
109 #define DBG_INIT(x...) printk(x)
111 #define DBG_INIT(x...)
115 #define DBG_RUN(x...) printk(x)
117 #define DBG_RUN(x...)
120 #ifdef DEBUG_SBA_RUN_SG
121 #define DBG_RUN_SG(x...) printk(x)
123 #define DBG_RUN_SG(x...)
127 #ifdef DEBUG_SBA_RESOURCE
128 #define DBG_RES(x...) printk(x)
130 #define DBG_RES(x...)
134 #define DBG_BYPASS(x...) printk(x)
136 #define DBG_BYPASS(x...)
139 #ifdef ASSERT_PDIR_SANITY
140 #define ASSERT(expr) \
142 printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
150 ** The number of pdir entries to "free" before issuing
151 ** a read to PCOM register to flush out PCOM writes.
152 ** Interacts with allocation granularity (ie 4 or 8 entries
153 ** allocated and free'd/purged at a time might make this
154 ** less interesting).
156 #define DELAYED_RESOURCE_CNT 64
158 #define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
159 #define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
160 #define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
162 #define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
164 #define IOC_FUNC_ID 0x000
165 #define IOC_FCLASS 0x008 /* function class, bist, header, rev... */
166 #define IOC_IBASE 0x300 /* IO TLB */
167 #define IOC_IMASK 0x308
168 #define IOC_PCOM 0x310
169 #define IOC_TCNFG 0x318
170 #define IOC_PDIR_BASE 0x320
172 #define IOC_ROPE0_CFG 0x500
173 #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
176 /* AGP GART driver looks for this */
177 #define ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
180 ** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register)
182 ** Some IOCs (sx1000) can run at the above pages sizes, but are
183 ** really only supported using the IOC at a 4k page size.
185 ** iovp_size could only be greater than PAGE_SIZE if we are
186 ** confident the drivers really only touch the next physical
187 ** page iff that driver instance owns it.
189 static unsigned long iovp_size;
190 static unsigned long iovp_shift;
191 static unsigned long iovp_mask;
194 void *ioc_hpa; /* I/O MMU base address */
195 char *res_map; /* resource map, bit == pdir entry */
196 u64 *pdir_base; /* physical base address */
197 unsigned long ibase; /* pdir IOV Space base */
198 unsigned long imask; /* pdir IOV Space mask */
200 unsigned long *res_hint; /* next avail IOVP - circular search */
201 unsigned long dma_mask;
202 spinlock_t res_lock; /* protects the resource bitmap, but must be held when */
203 /* clearing pdir to prevent races with allocations. */
204 unsigned int res_bitshift; /* from the RIGHT! */
205 unsigned int res_size; /* size of resource map in bytes */
206 #if DELAYED_RESOURCE_CNT > 0
207 spinlock_t saved_lock; /* may want to try to get this on a separate cacheline */
208 /* than res_lock for bigger systems. */
210 struct sba_dma_pair {
213 } saved[DELAYED_RESOURCE_CNT];
216 #ifdef PDIR_SEARCH_TIMING
217 #define SBA_SEARCH_SAMPLE 0x100
218 unsigned long avg_search[SBA_SEARCH_SAMPLE];
219 unsigned long avg_idx; /* current index into avg_search */
222 /* Stuff we don't need in performance path */
223 struct ioc *next; /* list of IOC's in system */
224 acpi_handle handle; /* for multiple IOC's */
226 unsigned int func_id;
227 unsigned int rev; /* HW revision of chip */
229 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
230 struct pci_dev *sac_only_dev;
233 static struct ioc *ioc_list;
234 static int reserve_sba_gart = 1;
236 static SBA_INLINE void sba_mark_invalid(struct ioc *, dma_addr_t, size_t);
237 static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t);
239 #define sba_sg_address(sg) (page_address((sg)->page) + (sg)->offset)
241 #ifdef FULL_VALID_PDIR
242 static u64 prefetch_spill_page;
246 # define GET_IOC(dev) (((dev)->bus == &pci_bus_type) \
247 ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
249 # define GET_IOC(dev) NULL
253 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
254 ** (or rather not merge) DMA's into managable chunks.
255 ** On parisc, this is more of the software/tuning constraint
256 ** rather than the HW. I/O MMU allocation alogorithms can be
257 ** faster with smaller size is (to some degree).
259 #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
261 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
263 /************************************
264 ** SBA register read and write support
266 ** BE WARNED: register writes are posted.
267 ** (ie follow writes which must reach HW with a read)
270 #define READ_REG(addr) __raw_readq(addr)
271 #define WRITE_REG(val, addr) __raw_writeq(val, addr)
273 #ifdef DEBUG_SBA_INIT
276 * sba_dump_tlb - debugging only - print IOMMU operating parameters
277 * @hpa: base address of the IOMMU
279 * Print the size/location of the IO MMU PDIR.
282 sba_dump_tlb(char *hpa)
284 DBG_INIT("IO TLB at 0x%p\n", (void *)hpa);
285 DBG_INIT("IOC_IBASE : %016lx\n", READ_REG(hpa+IOC_IBASE));
286 DBG_INIT("IOC_IMASK : %016lx\n", READ_REG(hpa+IOC_IMASK));
287 DBG_INIT("IOC_TCNFG : %016lx\n", READ_REG(hpa+IOC_TCNFG));
288 DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE));
294 #ifdef ASSERT_PDIR_SANITY
297 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
298 * @ioc: IO MMU structure which owns the pdir we are interested in.
299 * @msg: text to print ont the output line.
302 * Print one entry of the IO MMU PDIR in human readable form.
305 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
307 /* start printing from lowest pde in rval */
308 u64 *ptr = &ioc->pdir_base[pide & ~(BITS_PER_LONG - 1)];
309 unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)];
312 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
313 msg, rptr, pide & (BITS_PER_LONG - 1), *rptr);
316 while (rcnt < BITS_PER_LONG) {
317 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
318 (rcnt == (pide & (BITS_PER_LONG - 1)))
320 rcnt, ptr, (unsigned long long) *ptr );
324 printk(KERN_DEBUG "%s", msg);
329 * sba_check_pdir - debugging only - consistency checker
330 * @ioc: IO MMU structure which owns the pdir we are interested in.
331 * @msg: text to print ont the output line.
333 * Verify the resource map and pdir state is consistent
336 sba_check_pdir(struct ioc *ioc, char *msg)
338 u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]);
339 u64 *rptr = (u64 *) ioc->res_map; /* resource map ptr */
340 u64 *pptr = ioc->pdir_base; /* pdir ptr */
343 while (rptr < rptr_end) {
345 int rcnt; /* number of bits we might check */
351 /* Get last byte and highest bit from that */
352 u32 pde = ((u32)((*pptr >> (63)) & 0x1));
353 if ((rval & 0x1) ^ pde)
356 ** BUMMER! -- res_map != pdir --
357 ** Dump rval and matching pdir entries
359 sba_dump_pdir_entry(ioc, msg, pide);
363 rval >>= 1; /* try the next bit */
367 rptr++; /* look at next word of res_map */
369 /* It'd be nice if we always got here :^) */
375 * sba_dump_sg - debugging only - print Scatter-Gather list
376 * @ioc: IO MMU structure which owns the pdir we are interested in.
377 * @startsg: head of the SG list
378 * @nents: number of entries in SG list
380 * print the SG list so we can verify it's correct by hand.
383 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
385 while (nents-- > 0) {
386 printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents,
387 startsg->dma_address, startsg->dma_length,
388 sba_sg_address(startsg));
394 sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
396 struct scatterlist *the_sg = startsg;
397 int the_nents = nents;
399 while (the_nents-- > 0) {
400 if (sba_sg_address(the_sg) == 0x0UL)
401 sba_dump_sg(NULL, startsg, nents);
406 #endif /* ASSERT_PDIR_SANITY */
411 /**************************************************************
413 * I/O Pdir Resource Management
415 * Bits set in the resource map are in use.
416 * Each bit can represent a number of pages.
417 * LSbs represent lower addresses (IOVA's).
419 ***************************************************************/
420 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
422 /* Convert from IOVP to IOVA and vice versa. */
423 #define SBA_IOVA(ioc,iovp,offset) ((ioc->ibase) | (iovp) | (offset))
424 #define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase))
426 #define PDIR_ENTRY_SIZE sizeof(u64)
428 #define PDIR_INDEX(iovp) ((iovp)>>iovp_shift)
430 #define RESMAP_MASK(n) ~(~0UL << (n))
431 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
435 * For most cases the normal get_order is sufficient, however it limits us
436 * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity.
437 * It only incurs about 1 clock cycle to use this one with the static variable
438 * and makes the code more intuitive.
440 static SBA_INLINE int
441 get_iovp_order (unsigned long size)
443 long double d = size - 1;
446 order = ia64_getf_exp(d);
447 order = order - iovp_shift - 0xffff + 1;
454 * sba_search_bitmap - find free space in IO PDIR resource bitmap
455 * @ioc: IO MMU structure which owns the pdir we are interested in.
456 * @bits_wanted: number of entries we need.
458 * Find consecutive free bits in resource bitmap.
459 * Each bit represents one entry in the IO Pdir.
460 * Cool perf optimization: search for log2(size) bits at a time.
462 static SBA_INLINE unsigned long
463 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
465 unsigned long *res_ptr = ioc->res_hint;
466 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
467 unsigned long pide = ~0UL;
469 ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
470 ASSERT(res_ptr < res_end);
472 if (likely(bits_wanted == 1)) {
473 unsigned int bitshiftcnt;
474 for(; res_ptr < res_end ; res_ptr++) {
475 if (likely(*res_ptr != ~0UL)) {
476 bitshiftcnt = ffz(*res_ptr);
477 *res_ptr |= (1UL << bitshiftcnt);
478 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
479 pide <<= 3; /* convert to bit address */
481 ioc->res_bitshift = bitshiftcnt + bits_wanted;
489 if (likely(bits_wanted <= BITS_PER_LONG/2)) {
491 ** Search the resource bit map on well-aligned values.
492 ** "o" is the alignment.
493 ** We need the alignment to invalidate I/O TLB using
494 ** SBA HW features in the unmap path.
496 unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift);
497 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
498 unsigned long mask, base_mask;
500 base_mask = RESMAP_MASK(bits_wanted);
501 mask = base_mask << bitshiftcnt;
503 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
504 for(; res_ptr < res_end ; res_ptr++)
506 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
508 for (; mask ; mask <<= o, bitshiftcnt += o) {
509 if(0 == ((*res_ptr) & mask)) {
510 *res_ptr |= mask; /* mark resources busy! */
511 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
512 pide <<= 3; /* convert to bit address */
514 ioc->res_bitshift = bitshiftcnt + bits_wanted;
528 qwords = bits_wanted >> 6; /* /64 */
529 bits = bits_wanted - (qwords * BITS_PER_LONG);
531 end = res_end - qwords;
533 for (; res_ptr < end; res_ptr++) {
534 for (i = 0 ; i < qwords ; i++) {
538 if (bits && res_ptr[i] && (__ffs(res_ptr[i]) < bits))
541 /* Found it, mark it */
542 for (i = 0 ; i < qwords ; i++)
544 res_ptr[i] |= RESMAP_MASK(bits);
546 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
547 pide <<= 3; /* convert to bit address */
549 ioc->res_bitshift = bits;
557 prefetch(ioc->res_map);
558 ioc->res_hint = (unsigned long *) ioc->res_map;
559 ioc->res_bitshift = 0;
563 ioc->res_hint = res_ptr;
569 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
570 * @ioc: IO MMU structure which owns the pdir we are interested in.
571 * @size: number of bytes to create a mapping for
573 * Given a size, find consecutive unmarked and then mark those bits in the
577 sba_alloc_range(struct ioc *ioc, size_t size)
579 unsigned int pages_needed = size >> iovp_shift;
580 #ifdef PDIR_SEARCH_TIMING
581 unsigned long itc_start;
586 ASSERT(pages_needed);
587 ASSERT(0 == (size & ~iovp_mask));
589 spin_lock_irqsave(&ioc->res_lock, flags);
591 #ifdef PDIR_SEARCH_TIMING
592 itc_start = ia64_get_itc();
595 ** "seek and ye shall find"...praying never hurts either...
597 pide = sba_search_bitmap(ioc, pages_needed);
598 if (unlikely(pide >= (ioc->res_size << 3))) {
599 pide = sba_search_bitmap(ioc, pages_needed);
600 if (unlikely(pide >= (ioc->res_size << 3))) {
601 #if DELAYED_RESOURCE_CNT > 0
603 ** With delayed resource freeing, we can give this one more shot. We're
604 ** getting close to being in trouble here, so do what we can to make this
607 spin_lock(&ioc->saved_lock);
608 if (ioc->saved_cnt > 0) {
609 struct sba_dma_pair *d;
610 int cnt = ioc->saved_cnt;
612 d = &(ioc->saved[ioc->saved_cnt]);
615 sba_mark_invalid(ioc, d->iova, d->size);
616 sba_free_range(ioc, d->iova, d->size);
620 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
622 spin_unlock(&ioc->saved_lock);
624 pide = sba_search_bitmap(ioc, pages_needed);
625 if (unlikely(pide >= (ioc->res_size << 3)))
626 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
629 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
635 #ifdef PDIR_SEARCH_TIMING
636 ioc->avg_search[ioc->avg_idx++] = (ia64_get_itc() - itc_start) / pages_needed;
637 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
640 prefetchw(&(ioc->pdir_base[pide]));
642 #ifdef ASSERT_PDIR_SANITY
643 /* verify the first enable bit is clear */
644 if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) {
645 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
649 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
650 __FUNCTION__, size, pages_needed, pide,
651 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
654 spin_unlock_irqrestore(&ioc->res_lock, flags);
661 * sba_free_range - unmark bits in IO PDIR resource bitmap
662 * @ioc: IO MMU structure which owns the pdir we are interested in.
663 * @iova: IO virtual address which was previously allocated.
664 * @size: number of bytes to create a mapping for
666 * clear bits in the ioc's resource map
668 static SBA_INLINE void
669 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
671 unsigned long iovp = SBA_IOVP(ioc, iova);
672 unsigned int pide = PDIR_INDEX(iovp);
673 unsigned int ridx = pide >> 3; /* convert bit to byte address */
674 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
675 int bits_not_wanted = size >> iovp_shift;
678 for (; bits_not_wanted > 0 ; res_ptr++) {
680 if (unlikely(bits_not_wanted > BITS_PER_LONG)) {
682 /* these mappings start 64bit aligned */
684 bits_not_wanted -= BITS_PER_LONG;
685 pide += BITS_PER_LONG;
689 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
690 m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1));
693 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", __FUNCTION__, (uint) iova, size,
694 bits_not_wanted, m, pide, res_ptr, *res_ptr);
697 ASSERT(bits_not_wanted);
698 ASSERT((*res_ptr & m) == m); /* verify same bits are set */
705 /**************************************************************
707 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
709 ***************************************************************/
712 * sba_io_pdir_entry - fill in one IO PDIR entry
713 * @pdir_ptr: pointer to IO PDIR entry
714 * @vba: Virtual CPU address of buffer to map
716 * SBA Mapping Routine
718 * Given a virtual address (vba, arg1) sba_io_pdir_entry()
719 * loads the I/O PDIR entry pointed to by pdir_ptr (arg0).
720 * Each IO Pdir entry consists of 8 bytes as shown below
724 * +-+---------------------+----------------------------------+----+--------+
725 * |V| U | PPN[39:12] | U | FF |
726 * +-+---------------------+----------------------------------+----+--------+
730 * PPN == Physical Page Number
732 * The physical address fields are filled with the results of virt_to_phys()
737 #define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL) \
738 | 0x8000000000000000ULL)
741 sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba)
743 *pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL);
747 #ifdef ENABLE_MARK_CLEAN
749 * Since DMA is i-cache coherent, any (complete) pages that were written via
750 * DMA can be marked as "clean" so that update_mmu_cache() doesn't have to
751 * flush them when they get mapped into an executable vm-area.
754 mark_clean (void *addr, size_t size)
756 unsigned long pg_addr, end;
758 pg_addr = PAGE_ALIGN((unsigned long) addr);
759 end = (unsigned long) addr + size;
760 while (pg_addr + PAGE_SIZE <= end) {
761 struct page *page = virt_to_page((void *)pg_addr);
762 set_bit(PG_arch_1, &page->flags);
763 pg_addr += PAGE_SIZE;
769 * sba_mark_invalid - invalidate one or more IO PDIR entries
770 * @ioc: IO MMU structure which owns the pdir we are interested in.
771 * @iova: IO Virtual Address mapped earlier
772 * @byte_cnt: number of bytes this mapping covers.
774 * Marking the IO PDIR entry(ies) as Invalid and invalidate
775 * corresponding IO TLB entry. The PCOM (Purge Command Register)
776 * is to purge stale entries in the IO TLB when unmapping entries.
778 * The PCOM register supports purging of multiple pages, with a minium
779 * of 1 page and a maximum of 2GB. Hardware requires the address be
780 * aligned to the size of the range being purged. The size of the range
781 * must be a power of 2. The "Cool perf optimization" in the
782 * allocation routine helps keep that true.
784 static SBA_INLINE void
785 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
787 u32 iovp = (u32) SBA_IOVP(ioc,iova);
789 int off = PDIR_INDEX(iovp);
791 /* Must be non-zero and rounded up */
792 ASSERT(byte_cnt > 0);
793 ASSERT(0 == (byte_cnt & ~iovp_mask));
795 #ifdef ASSERT_PDIR_SANITY
796 /* Assert first pdir entry is set */
797 if (!(ioc->pdir_base[off] >> 60)) {
798 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
802 if (byte_cnt <= iovp_size)
804 ASSERT(off < ioc->pdir_size);
806 iovp |= iovp_shift; /* set "size" field for PCOM */
808 #ifndef FULL_VALID_PDIR
810 ** clear I/O PDIR entry "valid" bit
811 ** Do NOT clear the rest - save it for debugging.
812 ** We should only clear bits that have previously
815 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
818 ** If we want to maintain the PDIR as valid, put in
819 ** the spill page so devices prefetching won't
820 ** cause a hard fail.
822 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
825 u32 t = get_iovp_order(byte_cnt) + iovp_shift;
828 ASSERT(t <= 31); /* 2GB! Max value of "size" field */
831 /* verify this pdir entry is enabled */
832 ASSERT(ioc->pdir_base[off] >> 63);
833 #ifndef FULL_VALID_PDIR
834 /* clear I/O Pdir entry "valid" bit first */
835 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
837 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
840 byte_cnt -= iovp_size;
841 } while (byte_cnt > 0);
844 WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM);
848 * sba_map_single - map one buffer and return IOVA for DMA
849 * @dev: instance of PCI owned by the driver that's asking.
850 * @addr: driver buffer to map.
851 * @size: number of bytes to map in driver buffer.
854 * See Documentation/DMA-mapping.txt
857 sba_map_single(struct device *dev, void *addr, size_t size, int dir)
864 #ifdef ASSERT_PDIR_SANITY
867 #ifdef ALLOW_IOV_BYPASS
868 unsigned long pci_addr = virt_to_phys(addr);
871 #ifdef ALLOW_IOV_BYPASS
872 ASSERT(to_pci_dev(dev)->dma_mask);
874 ** Check if the PCI device can DMA to ptr... if so, just return ptr
876 if (likely((pci_addr & ~to_pci_dev(dev)->dma_mask) == 0)) {
878 ** Device is bit capable of DMA'ing to the buffer...
879 ** just return the PCI address of ptr
881 DBG_BYPASS("sba_map_single() bypass mask/addr: 0x%lx/0x%lx\n",
882 to_pci_dev(dev)->dma_mask, pci_addr);
889 prefetch(ioc->res_hint);
892 ASSERT(size <= DMA_CHUNK_SIZE);
894 /* save offset bits */
895 offset = ((dma_addr_t) (long) addr) & ~iovp_mask;
897 /* round up to nearest iovp_size */
898 size = (size + offset + ~iovp_mask) & iovp_mask;
900 #ifdef ASSERT_PDIR_SANITY
901 spin_lock_irqsave(&ioc->res_lock, flags);
902 if (sba_check_pdir(ioc,"Check before sba_map_single()"))
903 panic("Sanity check failed");
904 spin_unlock_irqrestore(&ioc->res_lock, flags);
907 pide = sba_alloc_range(ioc, size);
909 iovp = (dma_addr_t) pide << iovp_shift;
911 DBG_RUN("%s() 0x%p -> 0x%lx\n",
912 __FUNCTION__, addr, (long) iovp | offset);
914 pdir_start = &(ioc->pdir_base[pide]);
917 ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
918 sba_io_pdir_entry(pdir_start, (unsigned long) addr);
920 DBG_RUN(" pdir 0x%p %lx\n", pdir_start, *pdir_start);
926 /* force pdir update */
929 /* form complete address */
930 #ifdef ASSERT_PDIR_SANITY
931 spin_lock_irqsave(&ioc->res_lock, flags);
932 sba_check_pdir(ioc,"Check after sba_map_single()");
933 spin_unlock_irqrestore(&ioc->res_lock, flags);
935 return SBA_IOVA(ioc, iovp, offset);
939 * sba_unmap_single - unmap one IOVA and free resources
940 * @dev: instance of PCI owned by the driver that's asking.
941 * @iova: IOVA of driver buffer previously mapped.
942 * @size: number of bytes mapped in driver buffer.
945 * See Documentation/DMA-mapping.txt
947 void sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, int dir)
950 #if DELAYED_RESOURCE_CNT > 0
951 struct sba_dma_pair *d;
959 #ifdef ALLOW_IOV_BYPASS
960 if (likely((iova & ioc->imask) != ioc->ibase)) {
962 ** Address does not fall w/in IOVA, must be bypassing
964 DBG_BYPASS("sba_unmap_single() bypass addr: 0x%lx\n", iova);
966 #ifdef ENABLE_MARK_CLEAN
967 if (dir == DMA_FROM_DEVICE) {
968 mark_clean(phys_to_virt(iova), size);
974 offset = iova & ~iovp_mask;
976 DBG_RUN("%s() iovp 0x%lx/%x\n",
977 __FUNCTION__, (long) iova, size);
979 iova ^= offset; /* clear offset bits */
981 size = ROUNDUP(size, iovp_size);
984 #if DELAYED_RESOURCE_CNT > 0
985 spin_lock_irqsave(&ioc->saved_lock, flags);
986 d = &(ioc->saved[ioc->saved_cnt]);
989 if (unlikely(++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT)) {
990 int cnt = ioc->saved_cnt;
991 spin_lock(&ioc->res_lock);
993 sba_mark_invalid(ioc, d->iova, d->size);
994 sba_free_range(ioc, d->iova, d->size);
998 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
999 spin_unlock(&ioc->res_lock);
1001 spin_unlock_irqrestore(&ioc->saved_lock, flags);
1002 #else /* DELAYED_RESOURCE_CNT == 0 */
1003 spin_lock_irqsave(&ioc->res_lock, flags);
1004 sba_mark_invalid(ioc, iova, size);
1005 sba_free_range(ioc, iova, size);
1006 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1007 spin_unlock_irqrestore(&ioc->res_lock, flags);
1008 #endif /* DELAYED_RESOURCE_CNT == 0 */
1009 #ifdef ENABLE_MARK_CLEAN
1010 if (dir == DMA_FROM_DEVICE) {
1011 u32 iovp = (u32) SBA_IOVP(ioc,iova);
1012 int off = PDIR_INDEX(iovp);
1015 if (size <= iovp_size) {
1016 addr = phys_to_virt(ioc->pdir_base[off] &
1017 ~0xE000000000000FFFULL);
1018 mark_clean(addr, size);
1020 size_t byte_cnt = size;
1023 addr = phys_to_virt(ioc->pdir_base[off] &
1024 ~0xE000000000000FFFULL);
1025 mark_clean(addr, min(byte_cnt, iovp_size));
1027 byte_cnt -= iovp_size;
1029 } while (byte_cnt > 0);
1037 * sba_alloc_coherent - allocate/map shared mem for DMA
1038 * @dev: instance of PCI owned by the driver that's asking.
1039 * @size: number of bytes mapped in driver buffer.
1040 * @dma_handle: IOVA of new buffer.
1042 * See Documentation/DMA-mapping.txt
1045 sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, int flags)
1050 addr = (void *) __get_free_pages(flags, get_order(size));
1051 if (unlikely(!addr))
1054 memset(addr, 0, size);
1055 *dma_handle = virt_to_phys(addr);
1057 #ifdef ALLOW_IOV_BYPASS
1058 ASSERT(dev->coherent_dma_mask);
1060 ** Check if the PCI device can DMA to ptr... if so, just return ptr
1062 if (likely((*dma_handle & ~dev->coherent_dma_mask) == 0)) {
1063 DBG_BYPASS("sba_alloc_coherent() bypass mask/addr: 0x%lx/0x%lx\n",
1064 dev->coherent_dma_mask, *dma_handle);
1071 * If device can't bypass or bypass is disabled, pass the 32bit fake
1072 * device to map single to get an iova mapping.
1076 *dma_handle = sba_map_single(&ioc->sac_only_dev->dev, addr, size, 0);
1083 * sba_free_coherent - free/unmap shared mem for DMA
1084 * @dev: instance of PCI owned by the driver that's asking.
1085 * @size: number of bytes mapped in driver buffer.
1086 * @vaddr: virtual address IOVA of "consistent" buffer.
1087 * @dma_handler: IO virtual address of "consistent" buffer.
1089 * See Documentation/DMA-mapping.txt
1091 void sba_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
1093 sba_unmap_single(dev, dma_handle, size, 0);
1094 free_pages((unsigned long) vaddr, get_order(size));
1099 ** Since 0 is a valid pdir_base index value, can't use that
1100 ** to determine if a value is valid or not. Use a flag to indicate
1101 ** the SG list entry contains a valid pdir index.
1103 #define PIDE_FLAG 0x1UL
1105 #ifdef DEBUG_LARGE_SG_ENTRIES
1106 int dump_run_sg = 0;
1111 * sba_fill_pdir - write allocated SG entries into IO PDIR
1112 * @ioc: IO MMU structure which owns the pdir we are interested in.
1113 * @startsg: list of IOVA/size pairs
1114 * @nents: number of entries in startsg list
1116 * Take preprocessed SG list and write corresponding entries
1120 static SBA_INLINE int
1123 struct scatterlist *startsg,
1126 struct scatterlist *dma_sg = startsg; /* pointer to current DMA */
1129 unsigned long dma_offset = 0;
1132 while (nents-- > 0) {
1133 int cnt = startsg->dma_length;
1134 startsg->dma_length = 0;
1136 #ifdef DEBUG_LARGE_SG_ENTRIES
1138 printk(" %2d : %08lx/%05x %p\n",
1139 nents, startsg->dma_address, cnt,
1140 sba_sg_address(startsg));
1142 DBG_RUN_SG(" %d : %08lx/%05x %p\n",
1143 nents, startsg->dma_address, cnt,
1144 sba_sg_address(startsg));
1147 ** Look for the start of a new DMA stream
1149 if (startsg->dma_address & PIDE_FLAG) {
1150 u32 pide = startsg->dma_address & ~PIDE_FLAG;
1151 dma_offset = (unsigned long) pide & ~iovp_mask;
1152 startsg->dma_address = 0;
1154 dma_sg->dma_address = pide | ioc->ibase;
1155 pdirp = &(ioc->pdir_base[pide >> iovp_shift]);
1160 ** Look for a VCONTIG chunk
1163 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1166 /* Since multiple Vcontig blocks could make up
1167 ** one DMA stream, *add* cnt to dma_len.
1169 dma_sg->dma_length += cnt;
1171 dma_offset=0; /* only want offset on first chunk */
1172 cnt = ROUNDUP(cnt, iovp_size);
1174 sba_io_pdir_entry(pdirp, vaddr);
1182 /* force pdir update */
1185 #ifdef DEBUG_LARGE_SG_ENTRIES
1193 ** Two address ranges are DMA contiguous *iff* "end of prev" and
1194 ** "start of next" are both on an IOV page boundary.
1196 ** (shift left is a quick trick to mask off upper bits)
1198 #define DMA_CONTIG(__X, __Y) \
1199 (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL)
1203 * sba_coalesce_chunks - preprocess the SG list
1204 * @ioc: IO MMU structure which owns the pdir we are interested in.
1205 * @startsg: list of IOVA/size pairs
1206 * @nents: number of entries in startsg list
1208 * First pass is to walk the SG list and determine where the breaks are
1209 * in the DMA stream. Allocates PDIR entries but does not fill them.
1210 * Returns the number of DMA chunks.
1212 * Doing the fill separate from the coalescing/allocation keeps the
1213 * code simpler. Future enhancement could make one pass through
1214 * the sglist do both.
1216 static SBA_INLINE int
1217 sba_coalesce_chunks( struct ioc *ioc,
1218 struct scatterlist *startsg,
1221 struct scatterlist *vcontig_sg; /* VCONTIG chunk head */
1222 unsigned long vcontig_len; /* len of VCONTIG chunk */
1223 unsigned long vcontig_end;
1224 struct scatterlist *dma_sg; /* next DMA stream head */
1225 unsigned long dma_offset, dma_len; /* start/len of DMA stream */
1229 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1232 ** Prepare for first/next DMA stream
1234 dma_sg = vcontig_sg = startsg;
1235 dma_len = vcontig_len = vcontig_end = startsg->length;
1236 vcontig_end += vaddr;
1237 dma_offset = vaddr & ~iovp_mask;
1239 /* PARANOID: clear entries */
1240 startsg->dma_address = startsg->dma_length = 0;
1243 ** This loop terminates one iteration "early" since
1244 ** it's always looking one "ahead".
1246 while (--nents > 0) {
1247 unsigned long vaddr; /* tmp */
1252 startsg->dma_address = startsg->dma_length = 0;
1254 /* catch brokenness in SCSI layer */
1255 ASSERT(startsg->length <= DMA_CHUNK_SIZE);
1258 ** First make sure current dma stream won't
1259 ** exceed DMA_CHUNK_SIZE if we coalesce the
1262 if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask)
1267 ** Then look for virtually contiguous blocks.
1269 ** append the next transaction?
1271 vaddr = (unsigned long) sba_sg_address(startsg);
1272 if (vcontig_end == vaddr)
1274 vcontig_len += startsg->length;
1275 vcontig_end += startsg->length;
1276 dma_len += startsg->length;
1280 #ifdef DEBUG_LARGE_SG_ENTRIES
1281 dump_run_sg = (vcontig_len > iovp_size);
1285 ** Not virtually contigous.
1286 ** Terminate prev chunk.
1287 ** Start a new chunk.
1289 ** Once we start a new VCONTIG chunk, dma_offset
1290 ** can't change. And we need the offset from the first
1291 ** chunk - not the last one. Ergo Successive chunks
1292 ** must start on page boundaries and dove tail
1293 ** with it's predecessor.
1295 vcontig_sg->dma_length = vcontig_len;
1297 vcontig_sg = startsg;
1298 vcontig_len = startsg->length;
1301 ** 3) do the entries end/start on page boundaries?
1302 ** Don't update vcontig_end until we've checked.
1304 if (DMA_CONTIG(vcontig_end, vaddr))
1306 vcontig_end = vcontig_len + vaddr;
1307 dma_len += vcontig_len;
1315 ** End of DMA Stream
1316 ** Terminate last VCONTIG block.
1317 ** Allocate space for DMA stream.
1319 vcontig_sg->dma_length = vcontig_len;
1320 dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask;
1321 ASSERT(dma_len <= DMA_CHUNK_SIZE);
1322 dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG
1323 | (sba_alloc_range(ioc, dma_len) << iovp_shift)
1333 * sba_map_sg - map Scatter/Gather list
1334 * @dev: instance of PCI owned by the driver that's asking.
1335 * @sglist: array of buffer/length pairs
1336 * @nents: number of entries in list
1337 * @dir: R/W or both.
1339 * See Documentation/DMA-mapping.txt
1341 int sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, int dir)
1344 int coalesced, filled = 0;
1345 #ifdef ASSERT_PDIR_SANITY
1346 unsigned long flags;
1348 #ifdef ALLOW_IOV_BYPASS_SG
1349 struct scatterlist *sg;
1352 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1356 #ifdef ALLOW_IOV_BYPASS_SG
1357 ASSERT(to_pci_dev(dev)->dma_mask);
1358 if (likely((ioc->dma_mask & ~to_pci_dev(dev)->dma_mask) == 0)) {
1359 for (sg = sglist ; filled < nents ; filled++, sg++){
1360 sg->dma_length = sg->length;
1361 sg->dma_address = virt_to_phys(sba_sg_address(sg));
1366 /* Fast path single entry scatterlists. */
1368 sglist->dma_length = sglist->length;
1369 sglist->dma_address = sba_map_single(dev, sba_sg_address(sglist), sglist->length, dir);
1373 #ifdef ASSERT_PDIR_SANITY
1374 spin_lock_irqsave(&ioc->res_lock, flags);
1375 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1377 sba_dump_sg(ioc, sglist, nents);
1378 panic("Check before sba_map_sg()");
1380 spin_unlock_irqrestore(&ioc->res_lock, flags);
1383 prefetch(ioc->res_hint);
1386 ** First coalesce the chunks and allocate I/O pdir space
1388 ** If this is one DMA stream, we can properly map using the
1389 ** correct virtual address associated with each DMA page.
1390 ** w/o this association, we wouldn't have coherent DMA!
1391 ** Access to the virtual address is what forces a two pass algorithm.
1393 coalesced = sba_coalesce_chunks(ioc, sglist, nents);
1396 ** Program the I/O Pdir
1398 ** map the virtual addresses to the I/O Pdir
1399 ** o dma_address will contain the pdir index
1400 ** o dma_len will contain the number of bytes to map
1401 ** o address contains the virtual address.
1403 filled = sba_fill_pdir(ioc, sglist, nents);
1405 #ifdef ASSERT_PDIR_SANITY
1406 spin_lock_irqsave(&ioc->res_lock, flags);
1407 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1409 sba_dump_sg(ioc, sglist, nents);
1410 panic("Check after sba_map_sg()\n");
1412 spin_unlock_irqrestore(&ioc->res_lock, flags);
1415 ASSERT(coalesced == filled);
1416 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1423 * sba_unmap_sg - unmap Scatter/Gather list
1424 * @dev: instance of PCI owned by the driver that's asking.
1425 * @sglist: array of buffer/length pairs
1426 * @nents: number of entries in list
1427 * @dir: R/W or both.
1429 * See Documentation/DMA-mapping.txt
1431 void sba_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
1433 #ifdef ASSERT_PDIR_SANITY
1435 unsigned long flags;
1438 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1439 __FUNCTION__, nents, sba_sg_address(sglist), sglist->length);
1441 #ifdef ASSERT_PDIR_SANITY
1445 spin_lock_irqsave(&ioc->res_lock, flags);
1446 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1447 spin_unlock_irqrestore(&ioc->res_lock, flags);
1450 while (nents && sglist->dma_length) {
1452 sba_unmap_single(dev, sglist->dma_address, sglist->dma_length, dir);
1457 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1459 #ifdef ASSERT_PDIR_SANITY
1460 spin_lock_irqsave(&ioc->res_lock, flags);
1461 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1462 spin_unlock_irqrestore(&ioc->res_lock, flags);
1467 /**************************************************************
1469 * Initialization and claim
1471 ***************************************************************/
1474 ioc_iova_init(struct ioc *ioc)
1478 struct pci_dev *device = NULL;
1479 #ifdef FULL_VALID_PDIR
1480 unsigned long index;
1484 ** Firmware programs the base and size of a "safe IOVA space"
1485 ** (one that doesn't overlap memory or LMMIO space) in the
1486 ** IBASE and IMASK registers.
1488 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL;
1489 ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL;
1491 ioc->iov_size = ~ioc->imask + 1;
1493 DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n",
1494 __FUNCTION__, ioc->ioc_hpa, ioc->ibase, ioc->imask,
1495 ioc->iov_size >> 20);
1497 switch (iovp_size) {
1498 case 4*1024: tcnfg = 0; break;
1499 case 8*1024: tcnfg = 1; break;
1500 case 16*1024: tcnfg = 2; break;
1501 case 64*1024: tcnfg = 3; break;
1503 panic(PFX "Unsupported IOTLB page size %ldK",
1507 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1509 ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE;
1510 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1511 get_order(ioc->pdir_size));
1512 if (!ioc->pdir_base)
1513 panic(PFX "Couldn't allocate I/O Page Table\n");
1515 memset(ioc->pdir_base, 0, ioc->pdir_size);
1517 DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __FUNCTION__,
1518 iovp_size >> 10, ioc->pdir_base, ioc->pdir_size);
1520 ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base);
1521 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1524 ** If an AGP device is present, only use half of the IOV space
1525 ** for PCI DMA. Unfortunately we can't know ahead of time
1526 ** whether GART support will actually be used, for now we
1527 ** can just key on an AGP device found in the system.
1528 ** We program the next pdir index after we stop w/ a key for
1529 ** the GART code to handshake on.
1531 while ((device = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, device)) != NULL)
1532 agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP);
1534 if (agp_found && reserve_sba_gart) {
1535 printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n",
1536 ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2);
1537 ioc->pdir_size /= 2;
1538 ((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE;
1540 #ifdef FULL_VALID_PDIR
1542 ** Check to see if the spill page has been allocated, we don't need more than
1543 ** one across multiple SBAs.
1545 if (!prefetch_spill_page) {
1546 char *spill_poison = "SBAIOMMU POISON";
1547 int poison_size = 16;
1548 void *poison_addr, *addr;
1550 addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size));
1552 panic(PFX "Couldn't allocate PDIR spill page\n");
1555 for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size)
1556 memcpy(poison_addr, spill_poison, poison_size);
1558 prefetch_spill_page = virt_to_phys(addr);
1560 DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __FUNCTION__, prefetch_spill_page);
1563 ** Set all the PDIR entries valid w/ the spill page as the target
1565 for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++)
1566 ((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page);
1569 /* Clear I/O TLB of any possible entries */
1570 WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM);
1571 READ_REG(ioc->ioc_hpa + IOC_PCOM);
1573 /* Enable IOVA translation */
1574 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1575 READ_REG(ioc->ioc_hpa + IOC_IBASE);
1579 ioc_resource_init(struct ioc *ioc)
1581 spin_lock_init(&ioc->res_lock);
1582 #if DELAYED_RESOURCE_CNT > 0
1583 spin_lock_init(&ioc->saved_lock);
1586 /* resource map size dictated by pdir_size */
1587 ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */
1588 ioc->res_size >>= 3; /* convert bit count to byte count */
1589 DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size);
1591 ioc->res_map = (char *) __get_free_pages(GFP_KERNEL,
1592 get_order(ioc->res_size));
1594 panic(PFX "Couldn't allocate resource map\n");
1596 memset(ioc->res_map, 0, ioc->res_size);
1597 /* next available IOVP - circular search */
1598 ioc->res_hint = (unsigned long *) ioc->res_map;
1600 #ifdef ASSERT_PDIR_SANITY
1601 /* Mark first bit busy - ie no IOVA 0 */
1602 ioc->res_map[0] = 0x1;
1603 ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE;
1605 #ifdef FULL_VALID_PDIR
1606 /* Mark the last resource used so we don't prefetch beyond IOVA space */
1607 ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */
1608 ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF
1609 | prefetch_spill_page);
1612 DBG_INIT("%s() res_map %x %p\n", __FUNCTION__,
1613 ioc->res_size, (void *) ioc->res_map);
1617 ioc_sac_init(struct ioc *ioc)
1619 struct pci_dev *sac = NULL;
1620 struct pci_controller *controller = NULL;
1623 * pci_alloc_coherent() must return a DMA address which is
1624 * SAC (single address cycle) addressable, so allocate a
1625 * pseudo-device to enforce that.
1627 sac = kmalloc(sizeof(*sac), GFP_KERNEL);
1629 panic(PFX "Couldn't allocate struct pci_dev");
1630 memset(sac, 0, sizeof(*sac));
1632 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
1634 panic(PFX "Couldn't allocate struct pci_controller");
1635 memset(controller, 0, sizeof(*controller));
1637 controller->iommu = ioc;
1638 sac->sysdata = controller;
1639 sac->dma_mask = 0xFFFFFFFFUL;
1641 sac->dev.bus = &pci_bus_type;
1643 ioc->sac_only_dev = sac;
1647 ioc_zx1_init(struct ioc *ioc)
1649 unsigned long rope_config;
1652 if (ioc->rev < 0x20)
1653 panic(PFX "IOC 2.0 or later required for IOMMU support\n");
1655 /* 38 bit memory controller + extra bit for range displaced by MMIO */
1656 ioc->dma_mask = (0x1UL << 39) - 1;
1659 ** Clear ROPE(N)_CONFIG AO bit.
1660 ** Disables "NT Ordering" (~= !"Relaxed Ordering")
1661 ** Overrides bit 1 in DMA Hint Sets.
1662 ** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701.
1664 for (i=0; i<(8*8); i+=8) {
1665 rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i);
1666 rope_config &= ~IOC_ROPE_AO;
1667 WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i);
1671 typedef void (initfunc)(struct ioc *);
1679 static struct ioc_iommu ioc_iommu_info[] __initdata = {
1680 { ZX1_IOC_ID, "zx1", ioc_zx1_init },
1681 { SX1000_IOC_ID, "sx1000", NULL },
1684 static struct ioc * __init
1685 ioc_init(u64 hpa, void *handle)
1688 struct ioc_iommu *info;
1690 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
1694 memset(ioc, 0, sizeof(*ioc));
1696 ioc->next = ioc_list;
1699 ioc->handle = handle;
1700 ioc->ioc_hpa = ioremap(hpa, 0x1000);
1702 ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID);
1703 ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL;
1704 ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL; /* conservative */
1706 for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) {
1707 if (ioc->func_id == info->func_id) {
1708 ioc->name = info->name;
1714 iovp_size = (1 << iovp_shift);
1715 iovp_mask = ~(iovp_size - 1);
1717 DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __FUNCTION__,
1718 PAGE_SIZE >> 10, iovp_size >> 10);
1721 ioc->name = kmalloc(24, GFP_KERNEL);
1723 sprintf((char *) ioc->name, "Unknown (%04x:%04x)",
1724 ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF);
1726 ioc->name = "Unknown";
1730 ioc_resource_init(ioc);
1733 if ((long) ~iovp_mask > (long) ia64_max_iommu_merge_mask)
1734 ia64_max_iommu_merge_mask = ~iovp_mask;
1736 printk(KERN_INFO PFX
1737 "%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n",
1738 ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF,
1739 hpa, ioc->iov_size >> 20, ioc->ibase);
1746 /**************************************************************************
1748 ** SBA initialization code (HW and SW)
1750 ** o identify SBA chip itself
1751 ** o FIXME: initialize DMA hints for reasonable defaults
1753 **************************************************************************/
1755 #ifdef CONFIG_PROC_FS
1757 ioc_start(struct seq_file *s, loff_t *pos)
1762 for (ioc = ioc_list; ioc; ioc = ioc->next)
1770 ioc_next(struct seq_file *s, void *v, loff_t *pos)
1772 struct ioc *ioc = v;
1779 ioc_stop(struct seq_file *s, void *v)
1784 ioc_show(struct seq_file *s, void *v)
1786 struct ioc *ioc = v;
1787 unsigned long *res_ptr = (unsigned long *)ioc->res_map;
1790 seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n",
1791 ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF));
1792 seq_printf(s, "IOVA size : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024));
1793 seq_printf(s, "IOVA page size : %ld kb\n", iovp_size/1024);
1795 for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr)
1796 used += hweight64(*res_ptr);
1798 seq_printf(s, "PDIR size : %d entries\n", ioc->pdir_size >> 3);
1799 seq_printf(s, "PDIR used : %d entries\n", used);
1801 #ifdef PDIR_SEARCH_TIMING
1803 unsigned long i = 0, avg = 0, min, max;
1804 min = max = ioc->avg_search[0];
1805 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1806 avg += ioc->avg_search[i];
1807 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1808 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1810 avg /= SBA_SEARCH_SAMPLE;
1811 seq_printf(s, "Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles/IOVA page)\n",
1815 #ifndef ALLOW_IOV_BYPASS
1816 seq_printf(s, "IOVA bypass disabled\n");
1821 static struct seq_operations ioc_seq_ops = {
1829 ioc_open(struct inode *inode, struct file *file)
1831 return seq_open(file, &ioc_seq_ops);
1834 static struct file_operations ioc_fops = {
1837 .llseek = seq_lseek,
1838 .release = seq_release
1844 struct proc_dir_entry *dir, *entry;
1846 dir = proc_mkdir("bus/mckinley", 0);
1850 entry = create_proc_entry(ioc_list->name, 0, dir);
1852 entry->proc_fops = &ioc_fops;
1857 sba_connect_bus(struct pci_bus *bus)
1859 acpi_handle handle, parent;
1863 if (!PCI_CONTROLLER(bus))
1864 panic(PFX "no sysdata on bus %d!\n", bus->number);
1866 if (PCI_CONTROLLER(bus)->iommu)
1869 handle = PCI_CONTROLLER(bus)->acpi_handle;
1874 * The IOC scope encloses PCI root bridges in the ACPI
1875 * namespace, so work our way out until we find an IOC we
1876 * claimed previously.
1879 for (ioc = ioc_list; ioc; ioc = ioc->next)
1880 if (ioc->handle == handle) {
1881 PCI_CONTROLLER(bus)->iommu = ioc;
1885 status = acpi_get_parent(handle, &parent);
1887 } while (ACPI_SUCCESS(status));
1889 printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number);
1893 acpi_sba_ioc_add(struct acpi_device *device)
1898 struct acpi_buffer buffer;
1899 struct acpi_device_info *dev_info;
1901 status = hp_acpi_csr_space(device->handle, &hpa, &length);
1902 if (ACPI_FAILURE(status))
1905 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
1906 status = acpi_get_object_info(device->handle, &buffer);
1907 if (ACPI_FAILURE(status))
1909 dev_info = buffer.pointer;
1912 * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI
1913 * root bridges, and its CSR space includes the IOC function.
1915 if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0) {
1916 hpa += ZX1_IOC_OFFSET;
1917 /* zx1 based systems default to kernel page size iommu pages */
1919 iovp_shift = min(PAGE_SHIFT, 16);
1921 ACPI_MEM_FREE(dev_info);
1924 * default anything not caught above or specified on cmdline to 4k
1930 ioc = ioc_init(hpa, device->handle);
1937 static struct acpi_driver acpi_sba_ioc_driver = {
1938 .name = "IOC IOMMU Driver",
1939 .ids = "HWP0001,HWP0004",
1941 .add = acpi_sba_ioc_add,
1948 acpi_bus_register_driver(&acpi_sba_ioc_driver);
1954 struct pci_bus *b = NULL;
1955 while ((b = pci_find_next_bus(b)) != NULL)
1960 #ifdef CONFIG_PROC_FS
1966 subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */
1968 extern void dig_setup(char**);
1970 * MAX_DMA_ADDRESS needs to be setup prior to paging_init to do any good,
1971 * so we use the platform_setup hook to fix it up.
1974 sba_setup(char **cmdline_p)
1976 MAX_DMA_ADDRESS = ~0UL;
1977 dig_setup(cmdline_p);
1981 nosbagart(char *str)
1983 reserve_sba_gart = 0;
1988 sba_dma_supported (struct device *dev, u64 mask)
1990 /* make sure it's at least 32bit capable */
1991 return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
1995 sba_dma_mapping_error (dma_addr_t dma_addr)
2000 __setup("nosbagart", nosbagart);
2003 sba_page_override(char *str)
2005 unsigned long page_size;
2007 page_size = memparse(str, &str);
2008 switch (page_size) {
2013 iovp_shift = ffs(page_size) - 1;
2016 printk("%s: unknown/unsupported iommu page size %ld\n",
2017 __FUNCTION__, page_size);
2023 __setup("sbapagesize=",sba_page_override);
2025 EXPORT_SYMBOL(sba_dma_mapping_error);
2026 EXPORT_SYMBOL(sba_map_single);
2027 EXPORT_SYMBOL(sba_unmap_single);
2028 EXPORT_SYMBOL(sba_map_sg);
2029 EXPORT_SYMBOL(sba_unmap_sg);
2030 EXPORT_SYMBOL(sba_dma_supported);
2031 EXPORT_SYMBOL(sba_alloc_coherent);
2032 EXPORT_SYMBOL(sba_free_coherent);