2 #include <linux/time.h>
3 #include <linux/errno.h>
5 /* IBM Summit (EXA) Cyclone counter code*/
6 #define CYCLONE_CBAR_ADDR 0xFEB00CD0
7 #define CYCLONE_PMCC_OFFSET 0x51A0
8 #define CYCLONE_MPMC_OFFSET 0x51D0
9 #define CYCLONE_MPCS_OFFSET 0x51A8
10 #define CYCLONE_TIMER_FREQ 100000000
13 int __init cyclone_setup(char *str)
19 static u32* volatile cyclone_timer; /* Cyclone MPMC0 register */
20 static u32 last_update_cyclone;
22 static unsigned long offset_base;
24 static unsigned long get_offset_cyclone(void)
29 /* Read the cyclone timer */
30 now = readl(cyclone_timer);
31 /* .. relative to previous update*/
32 offset = now - last_update_cyclone;
34 /* convert cyclone ticks to nanoseconds */
35 offset = (offset*NSEC_PER_SEC)/CYCLONE_TIMER_FREQ;
37 /* our adjusted time in nanoseconds */
38 return offset_base + offset;
41 static void update_cyclone(long delta_nsec)
46 /* Read the cyclone timer */
47 now = readl(cyclone_timer);
48 /* .. relative to previous update*/
49 offset = now - last_update_cyclone;
51 /* convert cyclone ticks to nanoseconds */
52 offset = (offset*NSEC_PER_SEC)/CYCLONE_TIMER_FREQ;
54 offset += offset_base;
56 /* Be careful about signed/unsigned comparisons here: */
57 if (delta_nsec < 0 || (unsigned long) delta_nsec < offset)
58 offset_base = offset - delta_nsec;
62 last_update_cyclone = now;
65 static void reset_cyclone(void)
68 last_update_cyclone = readl(cyclone_timer);
71 struct time_interpolator cyclone_interpolator = {
72 .get_offset = get_offset_cyclone,
73 .update = update_cyclone,
74 .reset = reset_cyclone,
75 .frequency = CYCLONE_TIMER_FREQ,
79 int __init init_cyclone_clock(void)
82 u64 base; /* saved cyclone base address */
83 u64 offset; /* offset from pageaddr to cyclone_timer register */
89 printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
91 /* find base address */
92 offset = (CYCLONE_CBAR_ADDR);
93 reg = (u64*)ioremap_nocache(offset, sizeof(u64));
95 printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
101 printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
108 offset = (base + CYCLONE_PMCC_OFFSET);
109 reg = (u64*)ioremap_nocache(offset, sizeof(u64));
111 printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
115 writel(0x00000001,reg);
119 offset = (base + CYCLONE_MPCS_OFFSET);
120 reg = (u64*)ioremap_nocache(offset, sizeof(u64));
122 printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
126 writel(0x00000001,reg);
129 /* map in cyclone_timer */
130 offset = (base + CYCLONE_MPMC_OFFSET);
131 cyclone_timer = (u32*)ioremap_nocache(offset, sizeof(u32));
133 printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
138 /*quick test to make sure its ticking*/
140 u32 old = readl(cyclone_timer);
142 while(stall--) barrier();
143 if(readl(cyclone_timer) == old){
144 printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
145 iounmap(cyclone_timer);
151 /* initialize last tick */
152 last_update_cyclone = readl(cyclone_timer);
153 register_time_interpolator(&cyclone_interpolator);
158 __initcall(init_cyclone_clock);