2 #include <linux/time.h>
3 #include <linux/errno.h>
5 /* IBM Summit (EXA) Cyclone counter code*/
6 #define CYCLONE_CBAR_ADDR 0xFEB00CD0
7 #define CYCLONE_PMCC_OFFSET 0x51A0
8 #define CYCLONE_MPMC_OFFSET 0x51D0
9 #define CYCLONE_MPCS_OFFSET 0x51A8
10 #define CYCLONE_TIMER_FREQ 100000000
13 void __init cyclone_setup(void)
18 static u32* volatile cyclone_timer; /* Cyclone MPMC0 register */
19 static u32 last_update_cyclone;
21 static unsigned long offset_base;
23 static unsigned long get_offset_cyclone(void)
28 /* Read the cyclone timer */
29 now = readl(cyclone_timer);
30 /* .. relative to previous update*/
31 offset = now - last_update_cyclone;
33 /* convert cyclone ticks to nanoseconds */
34 offset = (offset*NSEC_PER_SEC)/CYCLONE_TIMER_FREQ;
36 /* our adjusted time in nanoseconds */
37 return offset_base + offset;
40 static void update_cyclone(long delta_nsec)
45 /* Read the cyclone timer */
46 now = readl(cyclone_timer);
47 /* .. relative to previous update*/
48 offset = now - last_update_cyclone;
50 /* convert cyclone ticks to nanoseconds */
51 offset = (offset*NSEC_PER_SEC)/CYCLONE_TIMER_FREQ;
53 offset += offset_base;
55 /* Be careful about signed/unsigned comparisons here: */
56 if (delta_nsec < 0 || (unsigned long) delta_nsec < offset)
57 offset_base = offset - delta_nsec;
61 last_update_cyclone = now;
64 static void reset_cyclone(void)
67 last_update_cyclone = readl(cyclone_timer);
70 struct time_interpolator cyclone_interpolator = {
71 .get_offset = get_offset_cyclone,
72 .update = update_cyclone,
73 .reset = reset_cyclone,
74 .frequency = CYCLONE_TIMER_FREQ,
78 int __init init_cyclone_clock(void)
81 u64 base; /* saved cyclone base address */
82 u64 offset; /* offset from pageaddr to cyclone_timer register */
88 printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
90 /* find base address */
91 offset = (CYCLONE_CBAR_ADDR);
92 reg = (u64*)ioremap_nocache(offset, sizeof(u64));
94 printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
100 printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
107 offset = (base + CYCLONE_PMCC_OFFSET);
108 reg = (u64*)ioremap_nocache(offset, sizeof(u64));
110 printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
114 writel(0x00000001,reg);
118 offset = (base + CYCLONE_MPCS_OFFSET);
119 reg = (u64*)ioremap_nocache(offset, sizeof(u64));
121 printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
125 writel(0x00000001,reg);
128 /* map in cyclone_timer */
129 offset = (base + CYCLONE_MPMC_OFFSET);
130 cyclone_timer = (u32*)ioremap_nocache(offset, sizeof(u32));
132 printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
137 /*quick test to make sure its ticking*/
139 u32 old = readl(cyclone_timer);
141 while(stall--) barrier();
142 if(readl(cyclone_timer) == old){
143 printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
144 iounmap(cyclone_timer);
150 /* initialize last tick */
151 last_update_cyclone = readl(cyclone_timer);
152 register_time_interpolator(&cyclone_interpolator);
157 __initcall(init_cyclone_clock);