2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
8 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
20 #include <linux/config.h>
22 #include <asm/asmmacro.h>
24 #include <asm/kregs.h>
25 #include <asm/mmu_context.h>
26 #include <asm/offsets.h>
28 #include <asm/pgtable.h>
29 #include <asm/processor.h>
30 #include <asm/ptrace.h>
31 #include <asm/system.h>
33 .section __special_page_section,"ax"
35 .global empty_zero_page
39 .global swapper_pg_dir
45 stringz "Halting kernel\n"
52 * Start the kernel. When the bootloader passes control to _start(), r28
53 * points to the address of the boot parameter area. Execution reaches
54 * here in physical mode.
59 .save rp, r4 // terminate unwind chain with a NULL rp
68 * Initialize kernel region registers:
69 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
70 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
71 * rr[5]: VHPT disabled, page size = IA64_GRANULE_SHIFT
73 mov r16=((ia64_rid(IA64_REGION_ID_KERNEL, (5<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
75 mov r18=((ia64_rid(IA64_REGION_ID_KERNEL, (6<<61)) << 8) | (IA64_GRANULE_SHIFT << 2))
77 mov r20=((ia64_rid(IA64_REGION_ID_KERNEL, (7<<61)) << 8) | (IA64_GRANULE_SHIFT << 2))
85 * Now pin mappings into the TLB for kernel text and data
87 mov r18=KERNEL_TR_PAGE_SHIFT<<2
92 mov r16=IA64_TR_KERNEL
96 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
109 * Switch into virtual mode:
111 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
122 1: // now we are in virtual mode
124 // set IVT entry point---can't access I/O ports without it
136 #define isAP p2 // are we an Application Processor?
137 #define isBP p3 // are we the Bootstrap Processor?
141 * Find the init_task for the currently booting CPU. At poweron, and in
142 * UP mode, task_for_booting_cpu is NULL.
144 movl r3=task_for_booting_cpu
149 cmp.eq isBP,isAP=r3,r0
154 cmp.eq isBP,isAP=r0,r0
157 tpa r3=r2 // r3 == phys addr of task struct
158 // load mapping for stack (virtaddr in r2, physaddr in r3)
166 dep r2=-1,r3,61,3 // IMVA of task
169 shr.u r16=r3,IA64_GRANULE_SHIFT
176 mov r19=IA64_TR_CURRENT_STACK
184 // load the "current" pointer (r13) and ar.k6 with the current task
185 mov IA64_KR(CURRENT)=r2 // virtual address
186 mov IA64_KR(CURRENT_STACK)=r16
189 * Reserve space at the top of the stack for "struct pt_regs". Kernel threads
190 * don't store interesting values in that structure, but the space still needs
191 * to be there because time-critical stuff such as the context switching can
192 * be implemented more efficiently (for example, __switch_to()
193 * always sets the psr.dfh bit of the task it is switching to).
195 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
196 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
197 mov ar.rsc=0 // place RSE in enforced lazy mode
199 loadrs // clear the dirty partition
201 mov ar.bspstore=r2 // establish the new RSE stack
203 mov ar.rsc=0x3 // place RSE in eager mode
205 (isBP) dep r28=-1,r28,61,3 // make address virtual
206 (isBP) movl r2=ia64_boot_param
208 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
210 #ifdef CONFIG_IA64_EARLY_PRINTK
213 stringz "I'm alive and well\n"
217 alloc r2=ar.pfs,0,0,2,0
219 movl out1=alive_msg_end-alive_msg-1
221 br.call.sptk.many rp=early_printk
222 1: // force new bundle
223 #endif /* CONFIG_IA64_EARLY_PRINTK */
226 (isAP) br.call.sptk.many rp=start_secondary
228 (isAP) br.cond.sptk self
231 // This is executed by the bootstrap processor (bsp) only:
233 #ifdef CONFIG_IA64_FW_EMU
234 // initialize PAL & SAL emulator:
235 br.call.sptk.many rp=sys_fw_init
238 br.call.sptk.many rp=start_kernel
239 .ret2: addl r3=@ltoff(halt_msg),gp
241 alloc r2=ar.pfs,8,0,2,0
244 br.call.sptk.many b0=console_print
245 self: br.sptk.many self // endless loop
248 GLOBAL_ENTRY(ia64_save_debug_regs)
249 alloc r16=ar.pfs,1,0,0,0
250 mov r20=ar.lc // preserve ar.lc
251 mov ar.lc=IA64_NUM_DBG_REGS-1
253 add r19=IA64_NUM_DBG_REGS*8,in0
256 #ifdef CONFIG_ITANIUM
265 br.cloop.sptk.many 1b
267 mov ar.lc=r20 // restore ar.lc
269 END(ia64_save_debug_regs)
271 GLOBAL_ENTRY(ia64_load_debug_regs)
272 alloc r16=ar.pfs,1,0,0,0
274 mov r20=ar.lc // preserve ar.lc
275 add r19=IA64_NUM_DBG_REGS*8,in0
276 mov ar.lc=IA64_NUM_DBG_REGS-1
279 1: ld8.nta r16=[in0],8
284 #ifdef CONFIG_ITANIUM
286 srlz.d // Errata 132 (NoFix status)
289 br.cloop.sptk.many 1b
291 mov ar.lc=r20 // restore ar.lc
293 END(ia64_load_debug_regs)
295 GLOBAL_ENTRY(__ia64_save_fpu)
296 alloc r2=ar.pfs,1,4,0,0
297 adds loc0=96*16-16,in0
298 adds loc1=96*16-16-128,in0
300 stf.spill.nta [loc0]=f127,-256
301 stf.spill.nta [loc1]=f119,-256
303 stf.spill.nta [loc0]=f111,-256
304 stf.spill.nta [loc1]=f103,-256
306 stf.spill.nta [loc0]=f95,-256
307 stf.spill.nta [loc1]=f87,-256
309 stf.spill.nta [loc0]=f79,-256
310 stf.spill.nta [loc1]=f71,-256
312 stf.spill.nta [loc0]=f63,-256
313 stf.spill.nta [loc1]=f55,-256
314 adds loc2=96*16-32,in0
316 stf.spill.nta [loc0]=f47,-256
317 stf.spill.nta [loc1]=f39,-256
318 adds loc3=96*16-32-128,in0
320 stf.spill.nta [loc2]=f126,-256
321 stf.spill.nta [loc3]=f118,-256
323 stf.spill.nta [loc2]=f110,-256
324 stf.spill.nta [loc3]=f102,-256
326 stf.spill.nta [loc2]=f94,-256
327 stf.spill.nta [loc3]=f86,-256
329 stf.spill.nta [loc2]=f78,-256
330 stf.spill.nta [loc3]=f70,-256
332 stf.spill.nta [loc2]=f62,-256
333 stf.spill.nta [loc3]=f54,-256
334 adds loc0=96*16-48,in0
336 stf.spill.nta [loc2]=f46,-256
337 stf.spill.nta [loc3]=f38,-256
338 adds loc1=96*16-48-128,in0
340 stf.spill.nta [loc0]=f125,-256
341 stf.spill.nta [loc1]=f117,-256
343 stf.spill.nta [loc0]=f109,-256
344 stf.spill.nta [loc1]=f101,-256
346 stf.spill.nta [loc0]=f93,-256
347 stf.spill.nta [loc1]=f85,-256
349 stf.spill.nta [loc0]=f77,-256
350 stf.spill.nta [loc1]=f69,-256
352 stf.spill.nta [loc0]=f61,-256
353 stf.spill.nta [loc1]=f53,-256
354 adds loc2=96*16-64,in0
356 stf.spill.nta [loc0]=f45,-256
357 stf.spill.nta [loc1]=f37,-256
358 adds loc3=96*16-64-128,in0
360 stf.spill.nta [loc2]=f124,-256
361 stf.spill.nta [loc3]=f116,-256
363 stf.spill.nta [loc2]=f108,-256
364 stf.spill.nta [loc3]=f100,-256
366 stf.spill.nta [loc2]=f92,-256
367 stf.spill.nta [loc3]=f84,-256
369 stf.spill.nta [loc2]=f76,-256
370 stf.spill.nta [loc3]=f68,-256
372 stf.spill.nta [loc2]=f60,-256
373 stf.spill.nta [loc3]=f52,-256
374 adds loc0=96*16-80,in0
376 stf.spill.nta [loc2]=f44,-256
377 stf.spill.nta [loc3]=f36,-256
378 adds loc1=96*16-80-128,in0
380 stf.spill.nta [loc0]=f123,-256
381 stf.spill.nta [loc1]=f115,-256
383 stf.spill.nta [loc0]=f107,-256
384 stf.spill.nta [loc1]=f99,-256
386 stf.spill.nta [loc0]=f91,-256
387 stf.spill.nta [loc1]=f83,-256
389 stf.spill.nta [loc0]=f75,-256
390 stf.spill.nta [loc1]=f67,-256
392 stf.spill.nta [loc0]=f59,-256
393 stf.spill.nta [loc1]=f51,-256
394 adds loc2=96*16-96,in0
396 stf.spill.nta [loc0]=f43,-256
397 stf.spill.nta [loc1]=f35,-256
398 adds loc3=96*16-96-128,in0
400 stf.spill.nta [loc2]=f122,-256
401 stf.spill.nta [loc3]=f114,-256
403 stf.spill.nta [loc2]=f106,-256
404 stf.spill.nta [loc3]=f98,-256
406 stf.spill.nta [loc2]=f90,-256
407 stf.spill.nta [loc3]=f82,-256
409 stf.spill.nta [loc2]=f74,-256
410 stf.spill.nta [loc3]=f66,-256
412 stf.spill.nta [loc2]=f58,-256
413 stf.spill.nta [loc3]=f50,-256
414 adds loc0=96*16-112,in0
416 stf.spill.nta [loc2]=f42,-256
417 stf.spill.nta [loc3]=f34,-256
418 adds loc1=96*16-112-128,in0
420 stf.spill.nta [loc0]=f121,-256
421 stf.spill.nta [loc1]=f113,-256
423 stf.spill.nta [loc0]=f105,-256
424 stf.spill.nta [loc1]=f97,-256
426 stf.spill.nta [loc0]=f89,-256
427 stf.spill.nta [loc1]=f81,-256
429 stf.spill.nta [loc0]=f73,-256
430 stf.spill.nta [loc1]=f65,-256
432 stf.spill.nta [loc0]=f57,-256
433 stf.spill.nta [loc1]=f49,-256
434 adds loc2=96*16-128,in0
436 stf.spill.nta [loc0]=f41,-256
437 stf.spill.nta [loc1]=f33,-256
438 adds loc3=96*16-128-128,in0
440 stf.spill.nta [loc2]=f120,-256
441 stf.spill.nta [loc3]=f112,-256
443 stf.spill.nta [loc2]=f104,-256
444 stf.spill.nta [loc3]=f96,-256
446 stf.spill.nta [loc2]=f88,-256
447 stf.spill.nta [loc3]=f80,-256
449 stf.spill.nta [loc2]=f72,-256
450 stf.spill.nta [loc3]=f64,-256
452 stf.spill.nta [loc2]=f56,-256
453 stf.spill.nta [loc3]=f48,-256
455 stf.spill.nta [loc2]=f40
456 stf.spill.nta [loc3]=f32
460 GLOBAL_ENTRY(__ia64_load_fpu)
461 alloc r2=ar.pfs,1,2,0,0
468 ldf.fill.nta f32=[in0],loc0
469 ldf.fill.nta f40=[ r3],loc0
470 ldf.fill.nta f48=[r14],loc0
471 ldf.fill.nta f56=[r15],loc0
473 ldf.fill.nta f64=[in0],loc0
474 ldf.fill.nta f72=[ r3],loc0
475 ldf.fill.nta f80=[r14],loc0
476 ldf.fill.nta f88=[r15],loc0
478 ldf.fill.nta f96=[in0],loc1
479 ldf.fill.nta f104=[ r3],loc1
480 ldf.fill.nta f112=[r14],loc1
481 ldf.fill.nta f120=[r15],loc1
483 ldf.fill.nta f33=[in0],loc0
484 ldf.fill.nta f41=[ r3],loc0
485 ldf.fill.nta f49=[r14],loc0
486 ldf.fill.nta f57=[r15],loc0
488 ldf.fill.nta f65=[in0],loc0
489 ldf.fill.nta f73=[ r3],loc0
490 ldf.fill.nta f81=[r14],loc0
491 ldf.fill.nta f89=[r15],loc0
493 ldf.fill.nta f97=[in0],loc1
494 ldf.fill.nta f105=[ r3],loc1
495 ldf.fill.nta f113=[r14],loc1
496 ldf.fill.nta f121=[r15],loc1
498 ldf.fill.nta f34=[in0],loc0
499 ldf.fill.nta f42=[ r3],loc0
500 ldf.fill.nta f50=[r14],loc0
501 ldf.fill.nta f58=[r15],loc0
503 ldf.fill.nta f66=[in0],loc0
504 ldf.fill.nta f74=[ r3],loc0
505 ldf.fill.nta f82=[r14],loc0
506 ldf.fill.nta f90=[r15],loc0
508 ldf.fill.nta f98=[in0],loc1
509 ldf.fill.nta f106=[ r3],loc1
510 ldf.fill.nta f114=[r14],loc1
511 ldf.fill.nta f122=[r15],loc1
513 ldf.fill.nta f35=[in0],loc0
514 ldf.fill.nta f43=[ r3],loc0
515 ldf.fill.nta f51=[r14],loc0
516 ldf.fill.nta f59=[r15],loc0
518 ldf.fill.nta f67=[in0],loc0
519 ldf.fill.nta f75=[ r3],loc0
520 ldf.fill.nta f83=[r14],loc0
521 ldf.fill.nta f91=[r15],loc0
523 ldf.fill.nta f99=[in0],loc1
524 ldf.fill.nta f107=[ r3],loc1
525 ldf.fill.nta f115=[r14],loc1
526 ldf.fill.nta f123=[r15],loc1
528 ldf.fill.nta f36=[in0],loc0
529 ldf.fill.nta f44=[ r3],loc0
530 ldf.fill.nta f52=[r14],loc0
531 ldf.fill.nta f60=[r15],loc0
533 ldf.fill.nta f68=[in0],loc0
534 ldf.fill.nta f76=[ r3],loc0
535 ldf.fill.nta f84=[r14],loc0
536 ldf.fill.nta f92=[r15],loc0
538 ldf.fill.nta f100=[in0],loc1
539 ldf.fill.nta f108=[ r3],loc1
540 ldf.fill.nta f116=[r14],loc1
541 ldf.fill.nta f124=[r15],loc1
543 ldf.fill.nta f37=[in0],loc0
544 ldf.fill.nta f45=[ r3],loc0
545 ldf.fill.nta f53=[r14],loc0
546 ldf.fill.nta f61=[r15],loc0
548 ldf.fill.nta f69=[in0],loc0
549 ldf.fill.nta f77=[ r3],loc0
550 ldf.fill.nta f85=[r14],loc0
551 ldf.fill.nta f93=[r15],loc0
553 ldf.fill.nta f101=[in0],loc1
554 ldf.fill.nta f109=[ r3],loc1
555 ldf.fill.nta f117=[r14],loc1
556 ldf.fill.nta f125=[r15],loc1
558 ldf.fill.nta f38 =[in0],loc0
559 ldf.fill.nta f46 =[ r3],loc0
560 ldf.fill.nta f54 =[r14],loc0
561 ldf.fill.nta f62 =[r15],loc0
563 ldf.fill.nta f70 =[in0],loc0
564 ldf.fill.nta f78 =[ r3],loc0
565 ldf.fill.nta f86 =[r14],loc0
566 ldf.fill.nta f94 =[r15],loc0
568 ldf.fill.nta f102=[in0],loc1
569 ldf.fill.nta f110=[ r3],loc1
570 ldf.fill.nta f118=[r14],loc1
571 ldf.fill.nta f126=[r15],loc1
573 ldf.fill.nta f39 =[in0],loc0
574 ldf.fill.nta f47 =[ r3],loc0
575 ldf.fill.nta f55 =[r14],loc0
576 ldf.fill.nta f63 =[r15],loc0
578 ldf.fill.nta f71 =[in0],loc0
579 ldf.fill.nta f79 =[ r3],loc0
580 ldf.fill.nta f87 =[r14],loc0
581 ldf.fill.nta f95 =[r15],loc0
583 ldf.fill.nta f103=[in0]
584 ldf.fill.nta f111=[ r3]
585 ldf.fill.nta f119=[r14]
586 ldf.fill.nta f127=[r15]
590 GLOBAL_ENTRY(__ia64_init_fpu)
591 stf.spill [sp]=f0 // M3
595 ldfps f33,f34=[sp] // M0
596 ldfps f35,f36=[sp] // M1
604 ldfps f41,f42=[sp] // M0
605 ldfps f43,f44=[sp] // M1
612 ldfps f49,f50=[sp] // M0
613 ldfps f51,f52=[sp] // M1
620 ldfps f57,f58=[sp] // M0
621 ldfps f59,f60=[sp] // M1
628 ldfps f65,f66=[sp] // M0
629 ldfps f67,f68=[sp] // M1
636 ldfps f73,f74=[sp] // M0
637 ldfps f75,f76=[sp] // M1
644 ldfps f81,f82=[sp] // M0
645 ldfps f83,f84=[sp] // M1
653 * When the instructions are cached, it would be faster to initialize
654 * the remaining registers with simply mov instructions (F-unit).
655 * This gets the time down to ~29 cycles. However, this would use up
656 * 33 bundles, whereas continuing with the above pattern yields
657 * 10 bundles and ~30 cycles.
660 ldfps f89,f90=[sp] // M0
661 ldfps f91,f92=[sp] // M1
668 ldfps f97,f98=[sp] // M0
669 ldfps f99,f100=[sp] // M1
676 ldfps f105,f106=[sp] // M0
677 ldfps f107,f108=[sp] // M1
684 ldfps f113,f114=[sp] // M0
685 ldfps f115,f116=[sp] // M1
692 ldfps f121,f122=[sp] // M0
693 ldfps f123,f124=[sp] // M1
698 br.ret.sptk.many rp // F
702 * Switch execution mode from virtual to physical
705 * r16 = new psr to establish
707 * Note: RSE must already be in enforced lazy mode
709 GLOBAL_ENTRY(ia64_switch_mode_phys)
711 alloc r2=ar.pfs,0,0,0,0
712 rsm psr.i | psr.ic // disable interrupts and interrupt collection
717 flushrs // must be first insn in group
721 mov cr.ipsr=r16 // set new PSR
722 add r3=1f-ia64_switch_mode_phys,r15
725 mov r14=rp // get return address into a general register
728 // going to physical mode, use tpa to translate virt->phys
735 mov r18=ar.rnat // save ar.rnat
736 mov ar.bspstore=r17 // this steps on ar.rnat
740 mov ar.rnat=r18 // restore ar.rnat
741 rfi // must be last insn in group
745 END(ia64_switch_mode_phys)
748 * Switch execution mode from physical to virtual
751 * r16 = new psr to establish
753 * Note: RSE must already be in enforced lazy mode
755 GLOBAL_ENTRY(ia64_switch_mode_virt)
757 alloc r2=ar.pfs,0,0,0,0
758 rsm psr.i | psr.ic // disable interrupts and interrupt collection
763 flushrs // must be first insn in group
767 mov cr.ipsr=r16 // set new PSR
768 add r3=1f-ia64_switch_mode_virt,r15
771 mov r14=rp // get return address into a general register
775 // - for code addresses, set upper bits of addr to KERNEL_START
776 // - for stack addresses, set upper 3 bits to 0xe.... Dont change any of the
777 // lower bits since we want it to stay identity mapped
778 movl r18=KERNEL_START
779 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
780 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
788 mov r18=ar.rnat // save ar.rnat
789 mov ar.bspstore=r17 // this steps on ar.rnat
793 mov ar.rnat=r18 // restore ar.rnat
794 rfi // must be last insn in group
798 END(ia64_switch_mode_virt)
800 GLOBAL_ENTRY(ia64_delay_loop)
802 { nop 0 // work around GAS unwind info generation bug...
810 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
811 // inside function body without corrupting unwind info).
813 1: br.cloop.sptk.few 1b
819 GLOBAL_ENTRY(start_kernel_thread)
821 .save rp, r0 // this is the end of the call-chain
823 alloc r2 = ar.pfs, 0, 0, 2, 0
826 br.call.sptk.many rp = kernel_thread_helper;;
828 br.call.sptk.many rp = sys_exit;;
829 1: br.sptk.few 1b // not reached
830 END(start_kernel_thread)
832 #ifdef CONFIG_IA64_BRL_EMU
835 * Assembly routines used by brl_emu.c to set preserved register state.
838 #define SET_REG(reg) \
839 GLOBAL_ENTRY(ia64_set_##reg); \
840 alloc r16=ar.pfs,1,0,0,0; \
843 br.ret.sptk.many rp; \
852 #endif /* CONFIG_IA64_BRL_EMU */
856 * This routine handles spinlock contention. It uses a non-standard calling
857 * convention to avoid converting leaf routines into interior routines. Because
858 * of this special convention, there are several restrictions:
860 * - do not use gp relative variables, this code is called from the kernel
861 * and from modules, r1 is undefined.
862 * - do not use stacked registers, the caller owns them.
863 * - do not use the scratch stack space, the caller owns it.
864 * - do not use any registers other than the ones listed below
867 * ar.pfs - saved CFM of caller
868 * ar.ccv - 0 (and available for use)
869 * r28 - available for use.
870 * r29 - available for use.
871 * r30 - available for use.
872 * r31 - address of lock, available for use.
873 * b6 - return address
874 * p14 - available for use.
876 * If you patch this code to use more registers, do not forget to update
877 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
880 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
882 GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
884 .save ar.pfs, r0 // this code effectively has a zero frame size
889 .restore sp // pop existing prologue after next insn
896 // exponential backoff, kdb, lockmeter etc. go in here
898 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
901 cmp4.eq p14,p0=r30,r0
902 (p14) br.cond.sptk.few b6 // lock is now free, try to acquire
903 br.cond.sptk.few .wait
904 END(ia64_spinlock_contention_pre3_4)
908 GLOBAL_ENTRY(ia64_spinlock_contention)
913 // exponential backoff, kdb, lockmeter etc. go in here
915 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
917 cmp4.ne p14,p0=r30,r0
919 (p14) br.cond.sptk.few .wait
921 cmpxchg4.acq r30=[r31], r30, ar.ccv
923 cmp4.ne p14,p0=r0,r30
924 (p14) br.cond.sptk.few .wait
926 br.ret.sptk.many b6 // lock is now taken
927 END(ia64_spinlock_contention)
931 #endif /* CONFIG_SMP */