arch/ia64/kernel/iosapic.c

   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/smp.h>
  90 #include <linux/smp_lock.h>
  91 #include <linux/string.h>
  92 #include <linux/bootmem.h>
  93
  94 #include <asm/delay.h>
  95 #include <asm/hw_irq.h>
  96 #include <asm/io.h>
  97 #include <asm/iosapic.h>
  98 #include <asm/machvec.h>
  99 #include <asm/processor.h>
 100 #include <asm/ptrace.h>
 101 #include <asm/system.h>
 102
 103 #undef DEBUG_INTERRUPT_ROUTING
 104
 105 #ifdef DEBUG_INTERRUPT_ROUTING
 106 #define DBG(fmt...)     printk(fmt)
 107 #else
 108 #define DBG(fmt...)
 109 #endif
 110
 111 #define NR_PREALLOCATE_RTE_ENTRIES \
 112         (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 113 #define RTE_PREALLOCATED        (1)
 114
 115 static DEFINE_SPINLOCK(iosapic_lock);
 116
 117 /*
 118  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 119  * vector.
 120  */
 121
 122 struct iosapic_rte_info {
 123         struct list_head rte_list;      /* node in list of RTEs sharing the
 124                                          * same vector */
 125         char __iomem    *addr;          /* base address of IOSAPIC */
 126         unsigned int    gsi_base;       /* first GSI assigned to this
 127                                          * IOSAPIC */
 128         char            rte_index;      /* IOSAPIC RTE index */
 129         int             refcnt;         /* reference counter */
 130         unsigned int    flags;          /* flags */
 131 } ____cacheline_aligned;
 132
 133 static struct iosapic_intr_info {
 134         struct list_head rtes;          /* RTEs using this vector (empty =>
 135                                          * not an IOSAPIC interrupt) */
 136         int             count;          /* # of RTEs that shares this vector */
 137         u32             low32;          /* current value of low word of
 138                                          * Redirection table entry */
 139         unsigned int    dest;           /* destination CPU physical ID */
 140         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 141         unsigned char   polarity: 1;    /* interrupt polarity
 142                                          * (see iosapic.h) */
 143         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 144 } iosapic_intr_info[IA64_NUM_VECTORS];
 145
 146 static struct iosapic {
 147         char __iomem    *addr;          /* base address of IOSAPIC */
 148         unsigned int    gsi_base;       /* first GSI assigned to this
 149                                          * IOSAPIC */
 150         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 151         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 152 #ifdef CONFIG_NUMA
 153         unsigned short  node;           /* numa node association via pxm */
 154 #endif
 155 } iosapic_lists[NR_IOSAPICS];
 156
 157 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 158
 159 static int iosapic_kmalloc_ok;
 160 static LIST_HEAD(free_rte_list);
 161
 162 #ifdef CONFIG_XEN
 163 #include <xen/interface/xen.h>
 164 #include <xen/interface/physdev.h>
 165 #include <asm/hypervisor.h>
 166 static inline unsigned int xen_iosapic_read(char __iomem *iosapic, unsigned int reg)
 167 {
 168         struct physdev_apic apic_op;
 169         int ret;
 170
 171         apic_op.apic_physbase = (unsigned long)iosapic -
 172                                         __IA64_UNCACHED_OFFSET;
 173         apic_op.reg = reg;
 174         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
 175         if (ret)
 176                 return ret;
 177         return apic_op.value;
 178 }
 179
 180 static inline void xen_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
 181 {
 182         struct physdev_apic apic_op;
 183
 184         apic_op.apic_physbase = (unsigned long)iosapic -
 185                                         __IA64_UNCACHED_OFFSET;
 186         apic_op.reg = reg;
 187         apic_op.value = val;
 188         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
 189 }
 190
 191 static inline unsigned int iosapic_read(char __iomem *iosapic, unsigned int reg)
 192 {
 193         if (!is_running_on_xen()) {
 194                 writel(reg, iosapic + IOSAPIC_REG_SELECT);
 195                 return readl(iosapic + IOSAPIC_WINDOW);
 196         } else
 197                 return xen_iosapic_read(iosapic, reg);
 198 }
 199
 200 static inline void iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
 201 {
 202         if (!is_running_on_xen()) {
 203                 writel(reg, iosapic + IOSAPIC_REG_SELECT);
 204                 writel(val, iosapic + IOSAPIC_WINDOW);
 205         } else
 206                 xen_iosapic_write(iosapic, reg, val);
 207 }
 208
 209 int xen_assign_irq_vector(int irq)
 210 {
 211         struct physdev_irq irq_op;
 212
 213         irq_op.irq = irq;
 214         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
 215                 return -ENOSPC;
 216
 217         return irq_op.vector;
 218 }
 219 #endif /* XEN */
 220
 221 /*
 222  * Find an IOSAPIC associated with a GSI
 223  */
 224 static inline int
 225 find_iosapic (unsigned int gsi)
 226 {
 227         int i;
 228
 229         for (i = 0; i < NR_IOSAPICS; i++) {
 230                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 231                     iosapic_lists[i].num_rte)
 232                         return i;
 233         }
 234
 235         return -1;
 236 }
 237
 238 static inline int
 239 _gsi_to_vector (unsigned int gsi)
 240 {
 241         struct iosapic_intr_info *info;
 242         struct iosapic_rte_info *rte;
 243
 244         for (info = iosapic_intr_info; info <
 245                      iosapic_intr_info + IA64_NUM_VECTORS; ++info)
 246                 list_for_each_entry(rte, &info->rtes, rte_list)
 247                         if (rte->gsi_base + rte->rte_index == gsi)
 248                                 return info - iosapic_intr_info;
 249         return -1;
 250 }
 251
 252 /*
 253  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 254  * entry exists, return -1.
 255  */
 256 inline int
 257 gsi_to_vector (unsigned int gsi)
 258 {
 259         return _gsi_to_vector(gsi);
 260 }
 261
 262 int
 263 gsi_to_irq (unsigned int gsi)
 264 {
 265         unsigned long flags;
 266         int irq;
 267         /*
 268          * XXX fix me: this assumes an identity mapping between IA-64 vector
 269          * and Linux irq numbers...
 270          */
 271         spin_lock_irqsave(&iosapic_lock, flags);
 272         {
 273                 irq = _gsi_to_vector(gsi);
 274         }
 275         spin_unlock_irqrestore(&iosapic_lock, flags);
 276
 277         return irq;
 278 }
 279
 280 static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi,
 281                                                   unsigned int vec)
 282 {
 283         struct iosapic_rte_info *rte;
 284
 285         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 286                 if (rte->gsi_base + rte->rte_index == gsi)
 287                         return rte;
 288         return NULL;
 289 }
 290
 291 static void
 292 set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
 293 {
 294         unsigned long pol, trigger, dmode;
 295         u32 low32, high32;
 296         char __iomem *addr;
 297         int rte_index;
 298         char redir;
 299         struct iosapic_rte_info *rte;
 300
 301         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 302
 303         rte = gsi_vector_to_rte(gsi, vector);
 304         if (!rte)
 305                 return;         /* not an IOSAPIC interrupt */
 306
 307         rte_index = rte->rte_index;
 308         addr    = rte->addr;
 309         pol     = iosapic_intr_info[vector].polarity;
 310         trigger = iosapic_intr_info[vector].trigger;
 311         dmode   = iosapic_intr_info[vector].dmode;
 312
 313         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 314
 315 #ifdef CONFIG_SMP
 316         {
 317                 unsigned int irq;
 318
 319                 for (irq = 0; irq < NR_IRQS; ++irq)
 320                         if (irq_to_vector(irq) == vector) {
 321                                 set_irq_affinity_info(irq,
 322                                                       (int)(dest & 0xffff),
 323                                                       redir);
 324                                 break;
 325                         }
 326         }
 327 #endif
 328
 329         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 330                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 331                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 332                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 333                  vector);
 334
 335         /* dest contains both id and eid */
 336         high32 = (dest << IOSAPIC_DEST_SHIFT);
 337
 338         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
 339         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 340         iosapic_intr_info[vector].low32 = low32;
 341         iosapic_intr_info[vector].dest = dest;
 342 }
 343
 344 static void
 345 nop (unsigned int irq)
 346 {
 347         /* do nothing... */
 348 }
 349
 350 static void
 351 mask_irq (unsigned int irq)
 352 {
 353         unsigned long flags;
 354         char __iomem *addr;
 355         u32 low32;
 356         int rte_index;
 357         ia64_vector vec = irq_to_vector(irq);
 358         struct iosapic_rte_info *rte;
 359
 360         if (list_empty(&iosapic_intr_info[vec].rtes))
 361                 return;                 /* not an IOSAPIC interrupt! */
 362
 363         spin_lock_irqsave(&iosapic_lock, flags);
 364         {
 365                 /* set only the mask bit */
 366                 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
 367                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
 368                                     rte_list) {
 369                         addr = rte->addr;
 370                         rte_index = rte->rte_index;
 371                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 372                 }
 373         }
 374         spin_unlock_irqrestore(&iosapic_lock, flags);
 375 }
 376
 377 static void
 378 unmask_irq (unsigned int irq)
 379 {
 380         unsigned long flags;
 381         char __iomem *addr;
 382         u32 low32;
 383         int rte_index;
 384         ia64_vector vec = irq_to_vector(irq);
 385         struct iosapic_rte_info *rte;
 386
 387         if (list_empty(&iosapic_intr_info[vec].rtes))
 388                 return;                 /* not an IOSAPIC interrupt! */
 389
 390         spin_lock_irqsave(&iosapic_lock, flags);
 391         {
 392                 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
 393                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
 394                                     rte_list) {
 395                         addr = rte->addr;
 396                         rte_index = rte->rte_index;
 397                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 398                 }
 399         }
 400         spin_unlock_irqrestore(&iosapic_lock, flags);
 401 }
 402
 403
 404 static void
 405 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 406 {
 407 #ifdef CONFIG_SMP
 408         unsigned long flags;
 409         u32 high32, low32;
 410         int dest, rte_index;
 411         char __iomem *addr;
 412         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 413         ia64_vector vec;
 414         struct iosapic_rte_info *rte;
 415
 416         irq &= (~IA64_IRQ_REDIRECTED);
 417         vec = irq_to_vector(irq);
 418
 419         if (cpus_empty(mask))
 420                 return;
 421
 422         dest = cpu_physical_id(first_cpu(mask));
 423
 424         if (list_empty(&iosapic_intr_info[vec].rtes))
 425                 return;                 /* not an IOSAPIC interrupt */
 426
 427         set_irq_affinity_info(irq, dest, redir);
 428
 429         /* dest contains both id and eid */
 430         high32 = dest << IOSAPIC_DEST_SHIFT;
 431
 432         spin_lock_irqsave(&iosapic_lock, flags);
 433         {
 434                 low32 = iosapic_intr_info[vec].low32 &
 435                         ~(7 << IOSAPIC_DELIVERY_SHIFT);
 436
 437                 if (redir)
 438                         /* change delivery mode to lowest priority */
 439                         low32 |= (IOSAPIC_LOWEST_PRIORITY <<
 440                                   IOSAPIC_DELIVERY_SHIFT);
 441                 else
 442                         /* change delivery mode to fixed */
 443                         low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 444
 445                 iosapic_intr_info[vec].low32 = low32;
 446                 iosapic_intr_info[vec].dest = dest;
 447                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
 448                                     rte_list) {
 449                         addr = rte->addr;
 450                         rte_index = rte->rte_index;
 451                         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index),
 452                                       high32);
 453                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 454                 }
 455         }
 456         spin_unlock_irqrestore(&iosapic_lock, flags);
 457 #endif
 458 }
 459
 460 /*
 461  * Handlers for level-triggered interrupts.
 462  */
 463
 464 static unsigned int
 465 iosapic_startup_level_irq (unsigned int irq)
 466 {
 467         unmask_irq(irq);
 468         return 0;
 469 }
 470
 471 static void
 472 iosapic_end_level_irq (unsigned int irq)
 473 {
 474         ia64_vector vec = irq_to_vector(irq);
 475         struct iosapic_rte_info *rte;
 476
 477         move_native_irq(irq);
 478         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 479                 iosapic_eoi(rte->addr, vec);
 480 }
 481
 482 #define iosapic_shutdown_level_irq      mask_irq
 483 #define iosapic_enable_level_irq        unmask_irq
 484 #define iosapic_disable_level_irq       mask_irq
 485 #define iosapic_ack_level_irq           nop
 486
 487 struct hw_interrupt_type irq_type_iosapic_level = {
 488         .typename =     "IO-SAPIC-level",
 489         .startup =      iosapic_startup_level_irq,
 490         .shutdown =     iosapic_shutdown_level_irq,
 491         .enable =       iosapic_enable_level_irq,
 492         .disable =      iosapic_disable_level_irq,
 493         .ack =          iosapic_ack_level_irq,
 494         .end =          iosapic_end_level_irq,
 495         .set_affinity = iosapic_set_affinity
 496 };
 497
 498 /*
 499  * Handlers for edge-triggered interrupts.
 500  */
 501
 502 static unsigned int
 503 iosapic_startup_edge_irq (unsigned int irq)
 504 {
 505         unmask_irq(irq);
 506         /*
 507          * IOSAPIC simply drops interrupts pended while the
 508          * corresponding pin was masked, so we can't know if an
 509          * interrupt is pending already.  Let's hope not...
 510          */
 511         return 0;
 512 }
 513
 514 static void
 515 iosapic_ack_edge_irq (unsigned int irq)
 516 {
 517         irq_desc_t *idesc = irq_desc + irq;
 518
 519         move_native_irq(irq);
 520         /*
 521          * Once we have recorded IRQ_PENDING already, we can mask the
 522          * interrupt for real. This prevents IRQ storms from unhandled
 523          * devices.
 524          */
 525         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 526             (IRQ_PENDING|IRQ_DISABLED))
 527                 mask_irq(irq);
 528 }
 529
 530 #define iosapic_enable_edge_irq         unmask_irq
 531 #define iosapic_disable_edge_irq        nop
 532 #define iosapic_end_edge_irq            nop
 533
 534 struct hw_interrupt_type irq_type_iosapic_edge = {
 535         .typename =     "IO-SAPIC-edge",
 536         .startup =      iosapic_startup_edge_irq,
 537         .shutdown =     iosapic_disable_edge_irq,
 538         .enable =       iosapic_enable_edge_irq,
 539         .disable =      iosapic_disable_edge_irq,
 540         .ack =          iosapic_ack_edge_irq,
 541         .end =          iosapic_end_edge_irq,
 542         .set_affinity = iosapic_set_affinity
 543 };
 544
 545 unsigned int
 546 iosapic_version (char __iomem *addr)
 547 {
 548         /*
 549          * IOSAPIC Version Register return 32 bit structure like:
 550          * {
 551          *      unsigned int version   : 8;
 552          *      unsigned int reserved1 : 8;
 553          *      unsigned int max_redir : 8;
 554          *      unsigned int reserved2 : 8;
 555          * }
 556          */
 557         return iosapic_read(addr, IOSAPIC_VERSION);
 558 }
 559
 560 static int iosapic_find_sharable_vector (unsigned long trigger,
 561                                          unsigned long pol)
 562 {
 563         int i, vector = -1, min_count = -1;
 564         struct iosapic_intr_info *info;
 565
 566         /*
 567          * shared vectors for edge-triggered interrupts are not
 568          * supported yet
 569          */
 570         if (trigger == IOSAPIC_EDGE)
 571                 return -1;
 572
 573         for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
 574                 info = &iosapic_intr_info[i];
 575                 if (info->trigger == trigger && info->polarity == pol &&
 576                     (info->dmode == IOSAPIC_FIXED || info->dmode ==
 577                      IOSAPIC_LOWEST_PRIORITY)) {
 578                         if (min_count == -1 || info->count < min_count) {
 579                                 vector = i;
 580                                 min_count = info->count;
 581                         }
 582                 }
 583         }
 584
 585         return vector;
 586 }
 587
 588 /*
 589  * if the given vector is already owned by other,
 590  *  assign a new vector for the other and make the vector available
 591  */
 592 static void __init
 593 iosapic_reassign_vector (int vector)
 594 {
 595         int new_vector;
 596
 597         if (!list_empty(&iosapic_intr_info[vector].rtes)) {
 598                 new_vector = assign_irq_vector(AUTO_ASSIGN);
 599                 if (new_vector < 0)
 600                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 601                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 602                        vector, new_vector);
 603                 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
 604                        sizeof(struct iosapic_intr_info));
 605                 INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes);
 606                 list_move(iosapic_intr_info[vector].rtes.next,
 607                           &iosapic_intr_info[new_vector].rtes);
 608                 memset(&iosapic_intr_info[vector], 0,
 609                        sizeof(struct iosapic_intr_info));
 610                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
 611                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 612         }
 613 }
 614
 615 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 616 {
 617         int i;
 618         struct iosapic_rte_info *rte;
 619         int preallocated = 0;
 620
 621         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 622                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
 623                                     NR_PREALLOCATE_RTE_ENTRIES);
 624                 if (!rte)
 625                         return NULL;
 626                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 627                         list_add(&rte->rte_list, &free_rte_list);
 628         }
 629
 630         if (!list_empty(&free_rte_list)) {
 631                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
 632                                  rte_list);
 633                 list_del(&rte->rte_list);
 634                 preallocated++;
 635         } else {
 636                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 637                 if (!rte)
 638                         return NULL;
 639         }
 640
 641         memset(rte, 0, sizeof(struct iosapic_rte_info));
 642         if (preallocated)
 643                 rte->flags |= RTE_PREALLOCATED;
 644
 645         return rte;
 646 }
 647
 648 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 649 {
 650         if (rte->flags & RTE_PREALLOCATED)
 651                 list_add_tail(&rte->rte_list, &free_rte_list);
 652         else
 653                 kfree(rte);
 654 }
 655
 656 static inline int vector_is_shared (int vector)
 657 {
 658         return (iosapic_intr_info[vector].count > 1);
 659 }
 660
 661 static int
 662 register_intr (unsigned int gsi, int vector, unsigned char delivery,
 663                unsigned long polarity, unsigned long trigger)
 664 {
 665         irq_desc_t *idesc;
 666         struct hw_interrupt_type *irq_type;
 667         int rte_index;
 668         int index;
 669         unsigned long gsi_base;
 670         void __iomem *iosapic_address;
 671         struct iosapic_rte_info *rte;
 672
 673         index = find_iosapic(gsi);
 674         if (index < 0) {
 675                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 676                        __FUNCTION__, gsi);
 677                 return -ENODEV;
 678         }
 679
 680         iosapic_address = iosapic_lists[index].addr;
 681         gsi_base = iosapic_lists[index].gsi_base;
 682
 683         rte = gsi_vector_to_rte(gsi, vector);
 684         if (!rte) {
 685                 rte = iosapic_alloc_rte();
 686                 if (!rte) {
 687                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 688                                __FUNCTION__);
 689                         return -ENOMEM;
 690                 }
 691
 692                 rte_index = gsi - gsi_base;
 693                 rte->rte_index  = rte_index;
 694                 rte->addr       = iosapic_address;
 695                 rte->gsi_base   = gsi_base;
 696                 rte->refcnt++;
 697                 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
 698                 iosapic_intr_info[vector].count++;
 699                 iosapic_lists[index].rtes_inuse++;
 700         }
 701         else if (vector_is_shared(vector)) {
 702                 struct iosapic_intr_info *info = &iosapic_intr_info[vector];
 703                 if (info->trigger != trigger || info->polarity != polarity) {
 704                         printk (KERN_WARNING
 705                                 "%s: cannot override the interrupt\n",
 706                                 __FUNCTION__);
 707                         return -EINVAL;
 708                 }
 709         }
 710
 711         iosapic_intr_info[vector].polarity = polarity;
 712         iosapic_intr_info[vector].dmode    = delivery;
 713         iosapic_intr_info[vector].trigger  = trigger;
 714
 715         if (is_running_on_xen())
 716                 return 0;
 717
 718         if (trigger == IOSAPIC_EDGE)
 719                 irq_type = &irq_type_iosapic_edge;
 720         else
 721                 irq_type = &irq_type_iosapic_level;
 722
 723         idesc = irq_desc + vector;
 724         if (idesc->chip != irq_type) {
 725                 if (idesc->chip != &no_irq_type)
 726                         printk(KERN_WARNING
 727                                "%s: changing vector %d from %s to %s\n",
 728                                __FUNCTION__, vector,
 729                                idesc->chip->typename, irq_type->typename);
 730                 idesc->chip = irq_type;
 731         }
 732         return 0;
 733 }
 734
 735 static unsigned int
 736 get_target_cpu (unsigned int gsi, int vector)
 737 {
 738 #ifdef CONFIG_SMP
 739         static int cpu = -1;
 740         extern int cpe_vector;
 741
 742         /*
 743          * In case of vector shared by multiple RTEs, all RTEs that
 744          * share the vector need to use the same destination CPU.
 745          */
 746         if (!list_empty(&iosapic_intr_info[vector].rtes))
 747                 return iosapic_intr_info[vector].dest;
 748
 749         /*
 750          * If the platform supports redirection via XTP, let it
 751          * distribute interrupts.
 752          */
 753         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 754                 return cpu_physical_id(smp_processor_id());
 755
 756         /*
 757          * Some interrupts (ACPI SCI, for instance) are registered
 758          * before the BSP is marked as online.
 759          */
 760         if (!cpu_online(smp_processor_id()))
 761                 return cpu_physical_id(smp_processor_id());
 762
 763 #ifdef CONFIG_ACPI
 764         if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR)
 765                 return get_cpei_target_cpu();
 766 #endif
 767
 768 #ifdef CONFIG_NUMA
 769         {
 770                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 771                 cpumask_t cpu_mask;
 772
 773                 iosapic_index = find_iosapic(gsi);
 774                 if (iosapic_index < 0 ||
 775                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 776                         goto skip_numa_setup;
 777
 778                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 779
 780                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 781                         if (!cpu_online(numa_cpu))
 782                                 cpu_clear(numa_cpu, cpu_mask);
 783                 }
 784
 785                 num_cpus = cpus_weight(cpu_mask);
 786
 787                 if (!num_cpus)
 788                         goto skip_numa_setup;
 789
 790                 /* Use vector assignment to distribute across cpus in node */
 791                 cpu_index = vector % num_cpus;
 792
 793                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 794                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 795
 796                 if (numa_cpu != NR_CPUS)
 797                         return cpu_physical_id(numa_cpu);
 798         }
 799 skip_numa_setup:
 800 #endif
 801         /*
 802          * Otherwise, round-robin interrupt vectors across all the
 803          * processors.  (It'd be nice if we could be smarter in the
 804          * case of NUMA.)
 805          */
 806         do {
 807                 if (++cpu >= NR_CPUS)
 808                         cpu = 0;
 809         } while (!cpu_online(cpu));
 810
 811         return cpu_physical_id(cpu);
 812 #else  /* CONFIG_SMP */
 813         return cpu_physical_id(smp_processor_id());
 814 #endif
 815 }
 816
 817 /*
 818  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 819  * methods.  This provides an interface to register those interrupts and
 820  * program the IOSAPIC RTE.
 821  */
 822 int
 823 iosapic_register_intr (unsigned int gsi,
 824                        unsigned long polarity, unsigned long trigger)
 825 {
 826         int vector, mask = 1, err;
 827         unsigned int dest;
 828         unsigned long flags;
 829         struct iosapic_rte_info *rte;
 830         u32 low32;
 831 again:
 832         /*
 833          * If this GSI has already been registered (i.e., it's a
 834          * shared interrupt, or we lost a race to register it),
 835          * don't touch the RTE.
 836          */
 837         spin_lock_irqsave(&iosapic_lock, flags);
 838         {
 839                 vector = gsi_to_vector(gsi);
 840                 if (vector > 0) {
 841                         rte = gsi_vector_to_rte(gsi, vector);
 842                         rte->refcnt++;
 843                         spin_unlock_irqrestore(&iosapic_lock, flags);
 844                         return vector;
 845                 }
 846         }
 847         spin_unlock_irqrestore(&iosapic_lock, flags);
 848
 849         /* If vector is running out, we try to find a sharable vector */
 850         vector = assign_irq_vector(AUTO_ASSIGN);
 851         if (vector < 0) {
 852                 vector = iosapic_find_sharable_vector(trigger, polarity);
 853                 if (vector < 0)
 854                         return -ENOSPC;
 855         }
 856
 857         spin_lock_irqsave(&irq_desc[vector].lock, flags);
 858         spin_lock(&iosapic_lock);
 859         {
 860                 if (gsi_to_vector(gsi) > 0) {
 861                         if (list_empty(&iosapic_intr_info[vector].rtes))
 862                                 free_irq_vector(vector);
 863                         spin_unlock(&iosapic_lock);
 864                         spin_unlock_irqrestore(&irq_desc[vector].lock,
 865                                                flags);
 866                         goto again;
 867                 }
 868
 869                 dest = get_target_cpu(gsi, vector);
 870                 err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
 871                               polarity, trigger);
 872                 if (err < 0) {
 873                         spin_unlock(&iosapic_lock);
 874                         spin_unlock_irqrestore(&irq_desc[vector].lock,
 875                                                flags);
 876                         return err;
 877                 }
 878
 879                 /*
 880                  * If the vector is shared and already unmasked for
 881                  * other interrupt sources, don't mask it.
 882                  */
 883                 low32 = iosapic_intr_info[vector].low32;
 884                 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
 885                         mask = 0;
 886                 set_rte(gsi, vector, dest, mask);
 887         }
 888         spin_unlock(&iosapic_lock);
 889         spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
 890
 891         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 892                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 893                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 894                cpu_logical_id(dest), dest, vector);
 895
 896         return vector;
 897 }
 898
 899 void
 900 iosapic_unregister_intr (unsigned int gsi)
 901 {
 902         unsigned long flags;
 903         int irq, vector, index;
 904         irq_desc_t *idesc;
 905         u32 low32;
 906         unsigned long trigger, polarity;
 907         unsigned int dest;
 908         struct iosapic_rte_info *rte;
 909
 910         /*
 911          * If the irq associated with the gsi is not found,
 912          * iosapic_unregister_intr() is unbalanced. We need to check
 913          * this again after getting locks.
 914          */
 915         irq = gsi_to_irq(gsi);
 916         if (irq < 0) {
 917                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 918                        gsi);
 919                 WARN_ON(1);
 920                 return;
 921         }
 922         vector = irq_to_vector(irq);
 923
 924         idesc = irq_desc + irq;
 925         spin_lock_irqsave(&idesc->lock, flags);
 926         spin_lock(&iosapic_lock);
 927         {
 928                 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
 929                         printk(KERN_ERR
 930                                "iosapic_unregister_intr(%u) unbalanced\n",
 931                                gsi);
 932                         WARN_ON(1);
 933                         goto out;
 934                 }
 935
 936                 if (--rte->refcnt > 0)
 937                         goto out;
 938
 939                 /* Mask the interrupt */
 940                 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
 941                 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index),
 942                               low32);
 943
 944                 /* Remove the rte entry from the list */
 945                 list_del(&rte->rte_list);
 946                 iosapic_intr_info[vector].count--;
 947                 iosapic_free_rte(rte);
 948                 index = find_iosapic(gsi);
 949                 iosapic_lists[index].rtes_inuse--;
 950                 WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 951
 952                 trigger  = iosapic_intr_info[vector].trigger;
 953                 polarity = iosapic_intr_info[vector].polarity;
 954                 dest     = iosapic_intr_info[vector].dest;
 955                 printk(KERN_INFO
 956                        "GSI %u (%s, %s) -> CPU %d (0x%04x)"
 957                        " vector %d unregistered\n",
 958                        gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 959                        (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 960                        cpu_logical_id(dest), dest, vector);
 961
 962                 if (list_empty(&iosapic_intr_info[vector].rtes)) {
 963                         /* Sanity check */
 964                         BUG_ON(iosapic_intr_info[vector].count);
 965
 966                         /* Clear the interrupt controller descriptor */
 967                         idesc->chip = &no_irq_type;
 968
 969                         /* Clear the interrupt information */
 970                         memset(&iosapic_intr_info[vector], 0,
 971                                sizeof(struct iosapic_intr_info));
 972                         iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
 973                         INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 974
 975                         if (idesc->action) {
 976                                 printk(KERN_ERR
 977                                        "interrupt handlers still exist on"
 978                                        "IRQ %u\n", irq);
 979                                 WARN_ON(1);
 980                         }
 981
 982                         /* Free the interrupt vector */
 983                         free_irq_vector(vector);
 984                 }
 985         }
 986  out:
 987         spin_unlock(&iosapic_lock);
 988         spin_unlock_irqrestore(&idesc->lock, flags);
 989 }
 990
 991 /*
 992  * ACPI calls this when it finds an entry for a platform interrupt.
 993  */
 994 int __init
 995 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 996                                 int iosapic_vector, u16 eid, u16 id,
 997                                 unsigned long polarity, unsigned long trigger)
 998 {
 999         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
1000         unsigned char delivery;
1001         int vector, mask = 0;
1002         unsigned int dest = ((id << 8) | eid) & 0xffff;
1003
1004         switch (int_type) {
1005               case ACPI_INTERRUPT_PMI:
1006                 vector = iosapic_vector;
1007                 /*
1008                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
1009                  * we need to make sure the vector is available
1010                  */
1011                 iosapic_reassign_vector(vector);
1012                 delivery = IOSAPIC_PMI;
1013                 break;
1014               case ACPI_INTERRUPT_INIT:
1015                 vector = assign_irq_vector(AUTO_ASSIGN);
1016                 if (vector < 0)
1017                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
1018                 delivery = IOSAPIC_INIT;
1019                 break;
1020               case ACPI_INTERRUPT_CPEI:
1021                 vector = IA64_CPE_VECTOR;
1022                 delivery = IOSAPIC_LOWEST_PRIORITY;
1023                 mask = 1;
1024                 break;
1025               default:
1026                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
1027                        int_type);
1028                 return -1;
1029         }
1030
1031         register_intr(gsi, vector, delivery, polarity, trigger);
1032
1033         printk(KERN_INFO
1034                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
1035                " vector %d\n",
1036                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
1037                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
1038                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
1039                cpu_logical_id(dest), dest, vector);
1040
1041         set_rte(gsi, vector, dest, mask);
1042         return vector;
1043 }
1044
1045 /*
1046  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
1047  */
1048 void __init
1049 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
1050                           unsigned long polarity,
1051                           unsigned long trigger)
1052 {
1053         int vector;
1054         unsigned int dest = cpu_physical_id(smp_processor_id());
1055
1056         vector = isa_irq_to_vector(isa_irq);
1057
1058         register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
1059
1060         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
1061             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
1062             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
1063             cpu_logical_id(dest), dest, vector);
1064
1065         set_rte(gsi, vector, dest, 1);
1066 }
1067
1068 void __init
1069 iosapic_system_init (int system_pcat_compat)
1070 {
1071         int vector;
1072
1073         for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
1074                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
1075                 /* mark as unused */
1076                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
1077         }
1078
1079         pcat_compat = system_pcat_compat;
1080         if (is_running_on_xen())
1081                 return;
1082
1083         if (pcat_compat) {
1084                 /*
1085                  * Disable the compatibility mode interrupts (8259 style),
1086                  * needs IN/OUT support enabled.
1087                  */
1088                 printk(KERN_INFO
1089                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
1090                        __FUNCTION__);
1091                 outb(0xff, 0xA1);
1092                 outb(0xff, 0x21);
1093         }
1094 }
1095
1096 static inline int
1097 iosapic_alloc (void)
1098 {
1099         int index;
1100
1101         for (index = 0; index < NR_IOSAPICS; index++)
1102                 if (!iosapic_lists[index].addr)
1103                         return index;
1104
1105         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
1106         return -1;
1107 }
1108
1109 static inline void
1110 iosapic_free (int index)
1111 {
1112         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1113 }
1114
1115 static inline int
1116 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1117 {
1118         int index;
1119         unsigned int gsi_end, base, end;
1120
1121         /* check gsi range */
1122         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1123         for (index = 0; index < NR_IOSAPICS; index++) {
1124                 if (!iosapic_lists[index].addr)
1125                         continue;
1126
1127                 base = iosapic_lists[index].gsi_base;
1128                 end  = base + iosapic_lists[index].num_rte - 1;
1129
1130                 if (gsi_end < base || end < gsi_base)
1131                         continue; /* OK */
1132
1133                 return -EBUSY;
1134         }
1135         return 0;
1136 }
1137
1138 int __devinit
1139 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1140 {
1141         int num_rte, err, index;
1142         unsigned int isa_irq, ver;
1143         char __iomem *addr;
1144         unsigned long flags;
1145
1146         spin_lock_irqsave(&iosapic_lock, flags);
1147         {
1148                 addr = ioremap(phys_addr, 0);
1149                 ver = iosapic_version(addr);
1150
1151                 if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1152                         iounmap(addr);
1153                         spin_unlock_irqrestore(&iosapic_lock, flags);
1154                         return err;
1155                 }
1156
1157                 /*
1158                  * The MAX_REDIR register holds the highest input pin
1159                  * number (starting from 0).
1160                  * We add 1 so that we can use it for number of pins (= RTEs)
1161                  */
1162                 num_rte = ((ver >> 16) & 0xff) + 1;
1163
1164                 index = iosapic_alloc();
1165                 iosapic_lists[index].addr = addr;
1166                 iosapic_lists[index].gsi_base = gsi_base;
1167                 iosapic_lists[index].num_rte = num_rte;
1168 #ifdef CONFIG_NUMA
1169                 iosapic_lists[index].node = MAX_NUMNODES;
1170 #endif
1171         }
1172         spin_unlock_irqrestore(&iosapic_lock, flags);
1173
1174         if ((gsi_base == 0) && pcat_compat) {
1175                 /*
1176                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1177                  * these may get reprogrammed later on with data from the ACPI
1178                  * Interrupt Source Override table.
1179                  */
1180                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1181                         iosapic_override_isa_irq(isa_irq, isa_irq,
1182                                                  IOSAPIC_POL_HIGH,
1183                                                  IOSAPIC_EDGE);
1184         }
1185         return 0;
1186 }
1187
1188 #ifdef CONFIG_HOTPLUG
1189 int
1190 iosapic_remove (unsigned int gsi_base)
1191 {
1192         int index, err = 0;
1193         unsigned long flags;
1194
1195         spin_lock_irqsave(&iosapic_lock, flags);
1196         {
1197                 index = find_iosapic(gsi_base);
1198                 if (index < 0) {
1199                         printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1200                                __FUNCTION__, gsi_base);
1201                         goto out;
1202                 }
1203
1204                 if (iosapic_lists[index].rtes_inuse) {
1205                         err = -EBUSY;
1206                         printk(KERN_WARNING
1207                                "%s: IOSAPIC for GSI base %u is busy\n",
1208                                __FUNCTION__, gsi_base);
1209                         goto out;
1210                 }
1211
1212                 iounmap(iosapic_lists[index].addr);
1213                 iosapic_free(index);
1214         }
1215  out:
1216         spin_unlock_irqrestore(&iosapic_lock, flags);
1217         return err;
1218 }
1219 #endif /* CONFIG_HOTPLUG */
1220
1221 #ifdef CONFIG_NUMA
1222 void __devinit
1223 map_iosapic_to_node(unsigned int gsi_base, int node)
1224 {
1225         int index;
1226
1227         index = find_iosapic(gsi_base);
1228         if (index < 0) {
1229                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1230                        __FUNCTION__, gsi_base);
1231                 return;
1232         }
1233         iosapic_lists[index].node = node;
1234         return;
1235 }
1236 #endif
1237
1238 static int __init iosapic_enable_kmalloc (void)
1239 {
1240         iosapic_kmalloc_ok = 1;
1241         return 0;
1242 }
1243 core_initcall (iosapic_enable_kmalloc);