arch/ia64/kernel/iosapic.c

   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/smp.h>
  90 #include <linux/smp_lock.h>
  91 #include <linux/string.h>
  92 #include <linux/bootmem.h>
  93
  94 #include <asm/delay.h>
  95 #include <asm/hw_irq.h>
  96 #include <asm/io.h>
  97 #include <asm/iosapic.h>
  98 #include <asm/machvec.h>
  99 #include <asm/processor.h>
 100 #include <asm/ptrace.h>
 101 #include <asm/system.h>
 102
 103 #undef DEBUG_INTERRUPT_ROUTING
 104
 105 #ifdef DEBUG_INTERRUPT_ROUTING
 106 #define DBG(fmt...)     printk(fmt)
 107 #else
 108 #define DBG(fmt...)
 109 #endif
 110
 111 #define NR_PREALLOCATE_RTE_ENTRIES \
 112         (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 113 #define RTE_PREALLOCATED        (1)
 114
 115 static DEFINE_SPINLOCK(iosapic_lock);
 116
 117 /*
 118  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 119  * vector.
 120  */
 121
 122 struct iosapic_rte_info {
 123         struct list_head rte_list;      /* node in list of RTEs sharing the
 124                                          * same vector */
 125         char __iomem    *addr;          /* base address of IOSAPIC */
 126         unsigned int    gsi_base;       /* first GSI assigned to this
 127                                          * IOSAPIC */
 128         char            rte_index;      /* IOSAPIC RTE index */
 129         int             refcnt;         /* reference counter */
 130         unsigned int    flags;          /* flags */
 131 } ____cacheline_aligned;
 132
 133 static struct iosapic_intr_info {
 134         struct list_head rtes;          /* RTEs using this vector (empty =>
 135                                          * not an IOSAPIC interrupt) */
 136         int             count;          /* # of RTEs that shares this vector */
 137         u32             low32;          /* current value of low word of
 138                                          * Redirection table entry */
 139         unsigned int    dest;           /* destination CPU physical ID */
 140         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 141         unsigned char   polarity: 1;    /* interrupt polarity
 142                                          * (see iosapic.h) */
 143         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 144 } iosapic_intr_info[IA64_NUM_VECTORS];
 145
 146 static struct iosapic {
 147         char __iomem    *addr;          /* base address of IOSAPIC */
 148         unsigned int    gsi_base;       /* first GSI assigned to this
 149                                          * IOSAPIC */
 150         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 151         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 152 #ifdef CONFIG_NUMA
 153         unsigned short  node;           /* numa node association via pxm */
 154 #endif
 155 } iosapic_lists[NR_IOSAPICS];
 156
 157 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 158
 159 static int iosapic_kmalloc_ok;
 160 static LIST_HEAD(free_rte_list);
 161
 162 #ifdef CONFIG_XEN
 163 #include <xen/interface/xen.h>
 164 #include <xen/interface/physdev.h>
 165 #include <asm/hypervisor.h>
 166 static inline unsigned int xen_iosapic_read(char __iomem *iosapic, unsigned int reg)
 167 {
 168         struct physdev_apic apic_op;
 169         int ret;
 170
 171         apic_op.apic_physbase = (unsigned long)iosapic -
 172                                         __IA64_UNCACHED_OFFSET;
 173         apic_op.reg = reg;
 174         ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
 175         if (ret)
 176                 return ret;
 177         return apic_op.value;
 178 }
 179
 180 static inline void xen_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
 181 {
 182         struct physdev_apic apic_op;
 183
 184         apic_op.apic_physbase = (unsigned long)iosapic -
 185                                         __IA64_UNCACHED_OFFSET;
 186         apic_op.reg = reg;
 187         apic_op.value = val;
 188         HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
 189 }
 190
 191 static inline unsigned int iosapic_read(char __iomem *iosapic, unsigned int reg)
 192 {
 193         if (!is_running_on_xen()) {
 194                 writel(reg, iosapic + IOSAPIC_REG_SELECT);
 195                 return readl(iosapic + IOSAPIC_WINDOW);
 196         } else
 197                 return xen_iosapic_read(iosapic, reg);
 198 }
 199
 200 static inline void iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
 201 {
 202         if (!is_running_on_xen()) {
 203                 writel(reg, iosapic + IOSAPIC_REG_SELECT);
 204                 writel(val, iosapic + IOSAPIC_WINDOW);
 205         } else
 206                 xen_iosapic_write(iosapic, reg, val);
 207 }
 208
 209 int xen_assign_irq_vector(int irq)
 210 {
 211         struct physdev_irq irq_op;
 212
 213         irq_op.irq = irq;
 214         if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
 215                 return -ENOSPC;
 216
 217         return irq_op.vector;
 218 }
 219 #endif /* XEN */
 220
 221 /*
 222  * Find an IOSAPIC associated with a GSI
 223  */
 224 static inline int
 225 find_iosapic (unsigned int gsi)
 226 {
 227         int i;
 228
 229         for (i = 0; i < NR_IOSAPICS; i++) {
 230                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 231                     iosapic_lists[i].num_rte)
 232                         return i;
 233         }
 234
 235         return -1;
 236 }
 237
 238 static inline int
 239 _gsi_to_vector (unsigned int gsi)
 240 {
 241         struct iosapic_intr_info *info;
 242         struct iosapic_rte_info *rte;
 243
 244         for (info = iosapic_intr_info; info <
 245                      iosapic_intr_info + IA64_NUM_VECTORS; ++info)
 246                 list_for_each_entry(rte, &info->rtes, rte_list)
 247                         if (rte->gsi_base + rte->rte_index == gsi)
 248                                 return info - iosapic_intr_info;
 249         return -1;
 250 }
 251
 252 /*
 253  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 254  * entry exists, return -1.
 255  */
 256 inline int
 257 gsi_to_vector (unsigned int gsi)
 258 {
 259         return _gsi_to_vector(gsi);
 260 }
 261
 262 int
 263 gsi_to_irq (unsigned int gsi)
 264 {
 265         unsigned long flags;
 266         int irq;
 267         /*
 268          * XXX fix me: this assumes an identity mapping between IA-64 vector
 269          * and Linux irq numbers...
 270          */
 271         spin_lock_irqsave(&iosapic_lock, flags);
 272         {
 273                 irq = _gsi_to_vector(gsi);
 274         }
 275         spin_unlock_irqrestore(&iosapic_lock, flags);
 276
 277         return irq;
 278 }
 279
 280 static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi,
 281                                                   unsigned int vec)
 282 {
 283         struct iosapic_rte_info *rte;
 284
 285         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 286                 if (rte->gsi_base + rte->rte_index == gsi)
 287                         return rte;
 288         return NULL;
 289 }
 290
 291 static void
 292 set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
 293 {
 294         unsigned long pol, trigger, dmode;
 295         u32 low32, high32;
 296         char __iomem *addr;
 297         int rte_index;
 298         char redir;
 299         struct iosapic_rte_info *rte;
 300
 301         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 302
 303         rte = gsi_vector_to_rte(gsi, vector);
 304         if (!rte)
 305                 return;         /* not an IOSAPIC interrupt */
 306
 307         rte_index = rte->rte_index;
 308         addr    = rte->addr;
 309         pol     = iosapic_intr_info[vector].polarity;
 310         trigger = iosapic_intr_info[vector].trigger;
 311         dmode   = iosapic_intr_info[vector].dmode;
 312
 313         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 314
 315 #ifdef CONFIG_SMP
 316         {
 317                 unsigned int irq;
 318
 319                 for (irq = 0; irq < NR_IRQS; ++irq)
 320                         if (irq_to_vector(irq) == vector) {
 321                                 set_irq_affinity_info(irq,
 322                                                       (int)(dest & 0xffff),
 323                                                       redir);
 324                                 break;
 325                         }
 326         }
 327 #endif
 328
 329         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 330                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 331                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 332                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 333                  vector);
 334
 335         /* dest contains both id and eid */
 336         high32 = (dest << IOSAPIC_DEST_SHIFT);
 337
 338         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
 339         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 340         iosapic_intr_info[vector].low32 = low32;
 341         iosapic_intr_info[vector].dest = dest;
 342 }
 343
 344 static void
 345 nop (unsigned int irq)
 346 {
 347         /* do nothing... */
 348 }
 349
 350
 351 #ifdef CONFIG_KEXEC
 352 void
 353 kexec_disable_iosapic(void)
 354 {
 355         struct iosapic_intr_info *info;
 356         struct iosapic_rte_info *rte;
 357         u8 vec = 0;
 358         for (info = iosapic_intr_info; info <
 359                         iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) {
 360                 list_for_each_entry(rte, &info->rtes,
 361                                 rte_list) {
 362                         iosapic_write(rte->addr,
 363                                         IOSAPIC_RTE_LOW(rte->rte_index),
 364                                         IOSAPIC_MASK|vec);
 365                         iosapic_eoi(rte->addr, vec);
 366                 }
 367         }
 368 }
 369 #endif
 370
 371 static void
 372 mask_irq (unsigned int irq)
 373 {
 374         unsigned long flags;
 375         char __iomem *addr;
 376         u32 low32;
 377         int rte_index;
 378         ia64_vector vec = irq_to_vector(irq);
 379         struct iosapic_rte_info *rte;
 380
 381         if (list_empty(&iosapic_intr_info[vec].rtes))
 382                 return;                 /* not an IOSAPIC interrupt! */
 383
 384         spin_lock_irqsave(&iosapic_lock, flags);
 385         {
 386                 /* set only the mask bit */
 387                 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
 388                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
 389                                     rte_list) {
 390                         addr = rte->addr;
 391                         rte_index = rte->rte_index;
 392                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 393                 }
 394         }
 395         spin_unlock_irqrestore(&iosapic_lock, flags);
 396 }
 397
 398 static void
 399 unmask_irq (unsigned int irq)
 400 {
 401         unsigned long flags;
 402         char __iomem *addr;
 403         u32 low32;
 404         int rte_index;
 405         ia64_vector vec = irq_to_vector(irq);
 406         struct iosapic_rte_info *rte;
 407
 408         if (list_empty(&iosapic_intr_info[vec].rtes))
 409                 return;                 /* not an IOSAPIC interrupt! */
 410
 411         spin_lock_irqsave(&iosapic_lock, flags);
 412         {
 413                 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
 414                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
 415                                     rte_list) {
 416                         addr = rte->addr;
 417                         rte_index = rte->rte_index;
 418                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 419                 }
 420         }
 421         spin_unlock_irqrestore(&iosapic_lock, flags);
 422 }
 423
 424
 425 static void
 426 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 427 {
 428 #ifdef CONFIG_SMP
 429         unsigned long flags;
 430         u32 high32, low32;
 431         int dest, rte_index;
 432         char __iomem *addr;
 433         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 434         ia64_vector vec;
 435         struct iosapic_rte_info *rte;
 436
 437         irq &= (~IA64_IRQ_REDIRECTED);
 438         vec = irq_to_vector(irq);
 439
 440         if (cpus_empty(mask))
 441                 return;
 442
 443         dest = cpu_physical_id(first_cpu(mask));
 444
 445         if (list_empty(&iosapic_intr_info[vec].rtes))
 446                 return;                 /* not an IOSAPIC interrupt */
 447
 448         set_irq_affinity_info(irq, dest, redir);
 449
 450         /* dest contains both id and eid */
 451         high32 = dest << IOSAPIC_DEST_SHIFT;
 452
 453         spin_lock_irqsave(&iosapic_lock, flags);
 454         {
 455                 low32 = iosapic_intr_info[vec].low32 &
 456                         ~(7 << IOSAPIC_DELIVERY_SHIFT);
 457
 458                 if (redir)
 459                         /* change delivery mode to lowest priority */
 460                         low32 |= (IOSAPIC_LOWEST_PRIORITY <<
 461                                   IOSAPIC_DELIVERY_SHIFT);
 462                 else
 463                         /* change delivery mode to fixed */
 464                         low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 465
 466                 iosapic_intr_info[vec].low32 = low32;
 467                 iosapic_intr_info[vec].dest = dest;
 468                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes,
 469                                     rte_list) {
 470                         addr = rte->addr;
 471                         rte_index = rte->rte_index;
 472                         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index),
 473                                       high32);
 474                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 475                 }
 476         }
 477         spin_unlock_irqrestore(&iosapic_lock, flags);
 478 #endif
 479 }
 480
 481 /*
 482  * Handlers for level-triggered interrupts.
 483  */
 484
 485 static unsigned int
 486 iosapic_startup_level_irq (unsigned int irq)
 487 {
 488         unmask_irq(irq);
 489         return 0;
 490 }
 491
 492 static void
 493 iosapic_end_level_irq (unsigned int irq)
 494 {
 495         ia64_vector vec = irq_to_vector(irq);
 496         struct iosapic_rte_info *rte;
 497
 498         move_native_irq(irq);
 499         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 500                 iosapic_eoi(rte->addr, vec);
 501 }
 502
 503 #define iosapic_shutdown_level_irq      mask_irq
 504 #define iosapic_enable_level_irq        unmask_irq
 505 #define iosapic_disable_level_irq       mask_irq
 506 #define iosapic_ack_level_irq           nop
 507
 508 struct irq_chip irq_type_iosapic_level = {
 509         .name =         "IO-SAPIC-level",
 510         .startup =      iosapic_startup_level_irq,
 511         .shutdown =     iosapic_shutdown_level_irq,
 512         .enable =       iosapic_enable_level_irq,
 513         .disable =      iosapic_disable_level_irq,
 514         .ack =          iosapic_ack_level_irq,
 515         .end =          iosapic_end_level_irq,
 516         .mask =         mask_irq,
 517         .unmask =       unmask_irq,
 518         .set_affinity = iosapic_set_affinity
 519 };
 520
 521 /*
 522  * Handlers for edge-triggered interrupts.
 523  */
 524
 525 static unsigned int
 526 iosapic_startup_edge_irq (unsigned int irq)
 527 {
 528         unmask_irq(irq);
 529         /*
 530          * IOSAPIC simply drops interrupts pended while the
 531          * corresponding pin was masked, so we can't know if an
 532          * interrupt is pending already.  Let's hope not...
 533          */
 534         return 0;
 535 }
 536
 537 static void
 538 iosapic_ack_edge_irq (unsigned int irq)
 539 {
 540         irq_desc_t *idesc = irq_desc + irq;
 541
 542         move_native_irq(irq);
 543         /*
 544          * Once we have recorded IRQ_PENDING already, we can mask the
 545          * interrupt for real. This prevents IRQ storms from unhandled
 546          * devices.
 547          */
 548         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 549             (IRQ_PENDING|IRQ_DISABLED))
 550                 mask_irq(irq);
 551 }
 552
 553 #define iosapic_enable_edge_irq         unmask_irq
 554 #define iosapic_disable_edge_irq        nop
 555 #define iosapic_end_edge_irq            nop
 556
 557 struct irq_chip irq_type_iosapic_edge = {
 558         .name =         "IO-SAPIC-edge",
 559         .startup =      iosapic_startup_edge_irq,
 560         .shutdown =     iosapic_disable_edge_irq,
 561         .enable =       iosapic_enable_edge_irq,
 562         .disable =      iosapic_disable_edge_irq,
 563         .ack =          iosapic_ack_edge_irq,
 564         .end =          iosapic_end_edge_irq,
 565         .mask =         mask_irq,
 566         .unmask =       unmask_irq,
 567         .set_affinity = iosapic_set_affinity
 568 };
 569
 570 unsigned int
 571 iosapic_version (char __iomem *addr)
 572 {
 573         /*
 574          * IOSAPIC Version Register return 32 bit structure like:
 575          * {
 576          *      unsigned int version   : 8;
 577          *      unsigned int reserved1 : 8;
 578          *      unsigned int max_redir : 8;
 579          *      unsigned int reserved2 : 8;
 580          * }
 581          */
 582         return iosapic_read(addr, IOSAPIC_VERSION);
 583 }
 584
 585 static int iosapic_find_sharable_vector (unsigned long trigger,
 586                                          unsigned long pol)
 587 {
 588         int i, vector = -1, min_count = -1;
 589         struct iosapic_intr_info *info;
 590
 591         /*
 592          * shared vectors for edge-triggered interrupts are not
 593          * supported yet
 594          */
 595         if (trigger == IOSAPIC_EDGE)
 596                 return -1;
 597
 598         for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
 599                 info = &iosapic_intr_info[i];
 600                 if (info->trigger == trigger && info->polarity == pol &&
 601                     (info->dmode == IOSAPIC_FIXED || info->dmode ==
 602                      IOSAPIC_LOWEST_PRIORITY)) {
 603                         if (min_count == -1 || info->count < min_count) {
 604                                 vector = i;
 605                                 min_count = info->count;
 606                         }
 607                 }
 608         }
 609
 610         return vector;
 611 }
 612
 613 /*
 614  * if the given vector is already owned by other,
 615  *  assign a new vector for the other and make the vector available
 616  */
 617 static void __init
 618 iosapic_reassign_vector (int vector)
 619 {
 620         int new_vector;
 621
 622         if (!list_empty(&iosapic_intr_info[vector].rtes)) {
 623                 new_vector = assign_irq_vector(AUTO_ASSIGN);
 624                 if (new_vector < 0)
 625                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 626                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 627                        vector, new_vector);
 628                 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
 629                        sizeof(struct iosapic_intr_info));
 630                 INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes);
 631                 list_move(iosapic_intr_info[vector].rtes.next,
 632                           &iosapic_intr_info[new_vector].rtes);
 633                 memset(&iosapic_intr_info[vector], 0,
 634                        sizeof(struct iosapic_intr_info));
 635                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
 636                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 637         }
 638 }
 639
 640 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 641 {
 642         int i;
 643         struct iosapic_rte_info *rte;
 644         int preallocated = 0;
 645
 646         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 647                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
 648                                     NR_PREALLOCATE_RTE_ENTRIES);
 649                 if (!rte)
 650                         return NULL;
 651                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 652                         list_add(&rte->rte_list, &free_rte_list);
 653         }
 654
 655         if (!list_empty(&free_rte_list)) {
 656                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
 657                                  rte_list);
 658                 list_del(&rte->rte_list);
 659                 preallocated++;
 660         } else {
 661                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 662                 if (!rte)
 663                         return NULL;
 664         }
 665
 666         memset(rte, 0, sizeof(struct iosapic_rte_info));
 667         if (preallocated)
 668                 rte->flags |= RTE_PREALLOCATED;
 669
 670         return rte;
 671 }
 672
 673 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 674 {
 675         if (rte->flags & RTE_PREALLOCATED)
 676                 list_add_tail(&rte->rte_list, &free_rte_list);
 677         else
 678                 kfree(rte);
 679 }
 680
 681 static inline int vector_is_shared (int vector)
 682 {
 683         return (iosapic_intr_info[vector].count > 1);
 684 }
 685
 686 static int
 687 register_intr (unsigned int gsi, int vector, unsigned char delivery,
 688                unsigned long polarity, unsigned long trigger)
 689 {
 690         irq_desc_t *idesc;
 691         struct hw_interrupt_type *irq_type;
 692         int rte_index;
 693         int index;
 694         unsigned long gsi_base;
 695         void __iomem *iosapic_address;
 696         struct iosapic_rte_info *rte;
 697
 698         index = find_iosapic(gsi);
 699         if (index < 0) {
 700                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 701                        __FUNCTION__, gsi);
 702                 return -ENODEV;
 703         }
 704
 705         iosapic_address = iosapic_lists[index].addr;
 706         gsi_base = iosapic_lists[index].gsi_base;
 707
 708         rte = gsi_vector_to_rte(gsi, vector);
 709         if (!rte) {
 710                 rte = iosapic_alloc_rte();
 711                 if (!rte) {
 712                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 713                                __FUNCTION__);
 714                         return -ENOMEM;
 715                 }
 716
 717                 rte_index = gsi - gsi_base;
 718                 rte->rte_index  = rte_index;
 719                 rte->addr       = iosapic_address;
 720                 rte->gsi_base   = gsi_base;
 721                 rte->refcnt++;
 722                 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
 723                 iosapic_intr_info[vector].count++;
 724                 iosapic_lists[index].rtes_inuse++;
 725         }
 726         else if (vector_is_shared(vector)) {
 727                 struct iosapic_intr_info *info = &iosapic_intr_info[vector];
 728                 if (info->trigger != trigger || info->polarity != polarity) {
 729                         printk (KERN_WARNING
 730                                 "%s: cannot override the interrupt\n",
 731                                 __FUNCTION__);
 732                         return -EINVAL;
 733                 }
 734         }
 735
 736         iosapic_intr_info[vector].polarity = polarity;
 737         iosapic_intr_info[vector].dmode    = delivery;
 738         iosapic_intr_info[vector].trigger  = trigger;
 739
 740         if (is_running_on_xen())
 741                 return 0;
 742
 743         if (trigger == IOSAPIC_EDGE)
 744                 irq_type = &irq_type_iosapic_edge;
 745         else
 746                 irq_type = &irq_type_iosapic_level;
 747
 748         idesc = irq_desc + vector;
 749         if (idesc->chip != irq_type) {
 750                 if (idesc->chip != &no_irq_type)
 751                         printk(KERN_WARNING
 752                                "%s: changing vector %d from %s to %s\n",
 753                                __FUNCTION__, vector,
 754                                idesc->chip->name, irq_type->name);
 755                 idesc->chip = irq_type;
 756         }
 757         return 0;
 758 }
 759
 760 static unsigned int
 761 get_target_cpu (unsigned int gsi, int vector)
 762 {
 763 #ifdef CONFIG_SMP
 764         static int cpu = -1;
 765         extern int cpe_vector;
 766
 767         /*
 768          * In case of vector shared by multiple RTEs, all RTEs that
 769          * share the vector need to use the same destination CPU.
 770          */
 771         if (!list_empty(&iosapic_intr_info[vector].rtes))
 772                 return iosapic_intr_info[vector].dest;
 773
 774         /*
 775          * If the platform supports redirection via XTP, let it
 776          * distribute interrupts.
 777          */
 778         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 779                 return cpu_physical_id(smp_processor_id());
 780
 781         /*
 782          * Some interrupts (ACPI SCI, for instance) are registered
 783          * before the BSP is marked as online.
 784          */
 785         if (!cpu_online(smp_processor_id()))
 786                 return cpu_physical_id(smp_processor_id());
 787
 788 #ifdef CONFIG_ACPI
 789         if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR)
 790                 return get_cpei_target_cpu();
 791 #endif
 792
 793 #ifdef CONFIG_NUMA
 794         {
 795                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 796                 cpumask_t cpu_mask;
 797
 798                 iosapic_index = find_iosapic(gsi);
 799                 if (iosapic_index < 0 ||
 800                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 801                         goto skip_numa_setup;
 802
 803                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 804
 805                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 806                         if (!cpu_online(numa_cpu))
 807                                 cpu_clear(numa_cpu, cpu_mask);
 808                 }
 809
 810                 num_cpus = cpus_weight(cpu_mask);
 811
 812                 if (!num_cpus)
 813                         goto skip_numa_setup;
 814
 815                 /* Use vector assignment to distribute across cpus in node */
 816                 cpu_index = vector % num_cpus;
 817
 818                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 819                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 820
 821                 if (numa_cpu != NR_CPUS)
 822                         return cpu_physical_id(numa_cpu);
 823         }
 824 skip_numa_setup:
 825 #endif
 826         /*
 827          * Otherwise, round-robin interrupt vectors across all the
 828          * processors.  (It'd be nice if we could be smarter in the
 829          * case of NUMA.)
 830          */
 831         do {
 832                 if (++cpu >= NR_CPUS)
 833                         cpu = 0;
 834         } while (!cpu_online(cpu));
 835
 836         return cpu_physical_id(cpu);
 837 #else  /* CONFIG_SMP */
 838         return cpu_physical_id(smp_processor_id());
 839 #endif
 840 }
 841
 842 /*
 843  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 844  * methods.  This provides an interface to register those interrupts and
 845  * program the IOSAPIC RTE.
 846  */
 847 int
 848 iosapic_register_intr (unsigned int gsi,
 849                        unsigned long polarity, unsigned long trigger)
 850 {
 851         int vector, mask = 1, err;
 852         unsigned int dest;
 853         unsigned long flags;
 854         struct iosapic_rte_info *rte;
 855         u32 low32;
 856 again:
 857         /*
 858          * If this GSI has already been registered (i.e., it's a
 859          * shared interrupt, or we lost a race to register it),
 860          * don't touch the RTE.
 861          */
 862         spin_lock_irqsave(&iosapic_lock, flags);
 863         {
 864                 vector = gsi_to_vector(gsi);
 865                 if (vector > 0) {
 866                         rte = gsi_vector_to_rte(gsi, vector);
 867                         rte->refcnt++;
 868                         spin_unlock_irqrestore(&iosapic_lock, flags);
 869                         return vector;
 870                 }
 871         }
 872         spin_unlock_irqrestore(&iosapic_lock, flags);
 873
 874         /* If vector is running out, we try to find a sharable vector */
 875         vector = assign_irq_vector(AUTO_ASSIGN);
 876         if (vector < 0) {
 877                 vector = iosapic_find_sharable_vector(trigger, polarity);
 878                 if (vector < 0)
 879                         return -ENOSPC;
 880         }
 881
 882         spin_lock_irqsave(&irq_desc[vector].lock, flags);
 883         spin_lock(&iosapic_lock);
 884         {
 885                 if (gsi_to_vector(gsi) > 0) {
 886                         if (list_empty(&iosapic_intr_info[vector].rtes))
 887                                 free_irq_vector(vector);
 888                         spin_unlock(&iosapic_lock);
 889                         spin_unlock_irqrestore(&irq_desc[vector].lock,
 890                                                flags);
 891                         goto again;
 892                 }
 893
 894                 dest = get_target_cpu(gsi, vector);
 895                 err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
 896                               polarity, trigger);
 897                 if (err < 0) {
 898                         spin_unlock(&iosapic_lock);
 899                         spin_unlock_irqrestore(&irq_desc[vector].lock,
 900                                                flags);
 901                         return err;
 902                 }
 903
 904                 /*
 905                  * If the vector is shared and already unmasked for
 906                  * other interrupt sources, don't mask it.
 907                  */
 908                 low32 = iosapic_intr_info[vector].low32;
 909                 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
 910                         mask = 0;
 911                 set_rte(gsi, vector, dest, mask);
 912         }
 913         spin_unlock(&iosapic_lock);
 914         spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
 915
 916         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 917                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 918                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 919                cpu_logical_id(dest), dest, vector);
 920
 921         return vector;
 922 }
 923
 924 void
 925 iosapic_unregister_intr (unsigned int gsi)
 926 {
 927         unsigned long flags;
 928         int irq, vector, index;
 929         irq_desc_t *idesc;
 930         u32 low32;
 931         unsigned long trigger, polarity;
 932         unsigned int dest;
 933         struct iosapic_rte_info *rte;
 934
 935         /*
 936          * If the irq associated with the gsi is not found,
 937          * iosapic_unregister_intr() is unbalanced. We need to check
 938          * this again after getting locks.
 939          */
 940         irq = gsi_to_irq(gsi);
 941         if (irq < 0) {
 942                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 943                        gsi);
 944                 WARN_ON(1);
 945                 return;
 946         }
 947         vector = irq_to_vector(irq);
 948
 949         idesc = irq_desc + irq;
 950         spin_lock_irqsave(&idesc->lock, flags);
 951         spin_lock(&iosapic_lock);
 952         {
 953                 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
 954                         printk(KERN_ERR
 955                                "iosapic_unregister_intr(%u) unbalanced\n",
 956                                gsi);
 957                         WARN_ON(1);
 958                         goto out;
 959                 }
 960
 961                 if (--rte->refcnt > 0)
 962                         goto out;
 963
 964                 /* Mask the interrupt */
 965                 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
 966                 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index),
 967                               low32);
 968
 969                 /* Remove the rte entry from the list */
 970                 list_del(&rte->rte_list);
 971                 iosapic_intr_info[vector].count--;
 972                 iosapic_free_rte(rte);
 973                 index = find_iosapic(gsi);
 974                 iosapic_lists[index].rtes_inuse--;
 975                 WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 976
 977                 trigger  = iosapic_intr_info[vector].trigger;
 978                 polarity = iosapic_intr_info[vector].polarity;
 979                 dest     = iosapic_intr_info[vector].dest;
 980                 printk(KERN_INFO
 981                        "GSI %u (%s, %s) -> CPU %d (0x%04x)"
 982                        " vector %d unregistered\n",
 983                        gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 984                        (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 985                        cpu_logical_id(dest), dest, vector);
 986
 987                 if (list_empty(&iosapic_intr_info[vector].rtes)) {
 988                         /* Sanity check */
 989                         BUG_ON(iosapic_intr_info[vector].count);
 990
 991                         /* Clear the interrupt controller descriptor */
 992                         idesc->chip = &no_irq_type;
 993
 994                         /* Clear the interrupt information */
 995                         memset(&iosapic_intr_info[vector], 0,
 996                                sizeof(struct iosapic_intr_info));
 997                         iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
 998                         INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 999
1000                         if (idesc->action) {
1001                                 printk(KERN_ERR
1002                                        "interrupt handlers still exist on"
1003                                        "IRQ %u\n", irq);
1004                                 WARN_ON(1);
1005                         }
1006
1007                         /* Free the interrupt vector */
1008                         free_irq_vector(vector);
1009                 }
1010         }
1011  out:
1012         spin_unlock(&iosapic_lock);
1013         spin_unlock_irqrestore(&idesc->lock, flags);
1014 }
1015
1016 /*
1017  * ACPI calls this when it finds an entry for a platform interrupt.
1018  */
1019 int __init
1020 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
1021                                 int iosapic_vector, u16 eid, u16 id,
1022                                 unsigned long polarity, unsigned long trigger)
1023 {
1024         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
1025         unsigned char delivery;
1026         int vector, mask = 0;
1027         unsigned int dest = ((id << 8) | eid) & 0xffff;
1028
1029         switch (int_type) {
1030               case ACPI_INTERRUPT_PMI:
1031                 vector = iosapic_vector;
1032                 /*
1033                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
1034                  * we need to make sure the vector is available
1035                  */
1036                 iosapic_reassign_vector(vector);
1037                 delivery = IOSAPIC_PMI;
1038                 break;
1039               case ACPI_INTERRUPT_INIT:
1040                 vector = assign_irq_vector(AUTO_ASSIGN);
1041                 if (vector < 0)
1042                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
1043                 delivery = IOSAPIC_INIT;
1044                 break;
1045               case ACPI_INTERRUPT_CPEI:
1046                 vector = IA64_CPE_VECTOR;
1047                 delivery = IOSAPIC_LOWEST_PRIORITY;
1048                 mask = 1;
1049                 break;
1050               default:
1051                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
1052                        int_type);
1053                 return -1;
1054         }
1055
1056         register_intr(gsi, vector, delivery, polarity, trigger);
1057
1058         printk(KERN_INFO
1059                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
1060                " vector %d\n",
1061                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
1062                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
1063                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
1064                cpu_logical_id(dest), dest, vector);
1065
1066         set_rte(gsi, vector, dest, mask);
1067         return vector;
1068 }
1069
1070 /*
1071  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
1072  */
1073 void __init
1074 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
1075                           unsigned long polarity,
1076                           unsigned long trigger)
1077 {
1078         int vector;
1079         unsigned int dest = cpu_physical_id(smp_processor_id());
1080
1081         vector = isa_irq_to_vector(isa_irq);
1082
1083         register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
1084
1085         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
1086             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
1087             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
1088             cpu_logical_id(dest), dest, vector);
1089
1090         set_rte(gsi, vector, dest, 1);
1091 }
1092
1093 void __init
1094 iosapic_system_init (int system_pcat_compat)
1095 {
1096         int vector;
1097
1098         for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
1099                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
1100                 /* mark as unused */
1101                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
1102         }
1103
1104         pcat_compat = system_pcat_compat;
1105         if (is_running_on_xen())
1106                 return;
1107
1108         if (pcat_compat) {
1109                 /*
1110                  * Disable the compatibility mode interrupts (8259 style),
1111                  * needs IN/OUT support enabled.
1112                  */
1113                 printk(KERN_INFO
1114                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
1115                        __FUNCTION__);
1116                 outb(0xff, 0xA1);
1117                 outb(0xff, 0x21);
1118         }
1119 }
1120
1121 static inline int
1122 iosapic_alloc (void)
1123 {
1124         int index;
1125
1126         for (index = 0; index < NR_IOSAPICS; index++)
1127                 if (!iosapic_lists[index].addr)
1128                         return index;
1129
1130         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
1131         return -1;
1132 }
1133
1134 static inline void
1135 iosapic_free (int index)
1136 {
1137         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1138 }
1139
1140 static inline int
1141 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1142 {
1143         int index;
1144         unsigned int gsi_end, base, end;
1145
1146         /* check gsi range */
1147         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1148         for (index = 0; index < NR_IOSAPICS; index++) {
1149                 if (!iosapic_lists[index].addr)
1150                         continue;
1151
1152                 base = iosapic_lists[index].gsi_base;
1153                 end  = base + iosapic_lists[index].num_rte - 1;
1154
1155                 if (gsi_end < base || end < gsi_base)
1156                         continue; /* OK */
1157
1158                 return -EBUSY;
1159         }
1160         return 0;
1161 }
1162
1163 int __devinit
1164 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1165 {
1166         int num_rte, err, index;
1167         unsigned int isa_irq, ver;
1168         char __iomem *addr;
1169         unsigned long flags;
1170
1171         spin_lock_irqsave(&iosapic_lock, flags);
1172         {
1173                 addr = ioremap(phys_addr, 0);
1174                 ver = iosapic_version(addr);
1175
1176                 if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1177                         iounmap(addr);
1178                         spin_unlock_irqrestore(&iosapic_lock, flags);
1179                         return err;
1180                 }
1181
1182                 /*
1183                  * The MAX_REDIR register holds the highest input pin
1184                  * number (starting from 0).
1185                  * We add 1 so that we can use it for number of pins (= RTEs)
1186                  */
1187                 num_rte = ((ver >> 16) & 0xff) + 1;
1188
1189                 index = iosapic_alloc();
1190                 iosapic_lists[index].addr = addr;
1191                 iosapic_lists[index].gsi_base = gsi_base;
1192                 iosapic_lists[index].num_rte = num_rte;
1193 #ifdef CONFIG_NUMA
1194                 iosapic_lists[index].node = MAX_NUMNODES;
1195 #endif
1196         }
1197         spin_unlock_irqrestore(&iosapic_lock, flags);
1198
1199         if ((gsi_base == 0) && pcat_compat) {
1200                 /*
1201                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1202                  * these may get reprogrammed later on with data from the ACPI
1203                  * Interrupt Source Override table.
1204                  */
1205                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1206                         iosapic_override_isa_irq(isa_irq, isa_irq,
1207                                                  IOSAPIC_POL_HIGH,
1208                                                  IOSAPIC_EDGE);
1209         }
1210         return 0;
1211 }
1212
1213 #ifdef CONFIG_HOTPLUG
1214 int
1215 iosapic_remove (unsigned int gsi_base)
1216 {
1217         int index, err = 0;
1218         unsigned long flags;
1219
1220         spin_lock_irqsave(&iosapic_lock, flags);
1221         {
1222                 index = find_iosapic(gsi_base);
1223                 if (index < 0) {
1224                         printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1225                                __FUNCTION__, gsi_base);
1226                         goto out;
1227                 }
1228
1229                 if (iosapic_lists[index].rtes_inuse) {
1230                         err = -EBUSY;
1231                         printk(KERN_WARNING
1232                                "%s: IOSAPIC for GSI base %u is busy\n",
1233                                __FUNCTION__, gsi_base);
1234                         goto out;
1235                 }
1236
1237                 iounmap(iosapic_lists[index].addr);
1238                 iosapic_free(index);
1239         }
1240  out:
1241         spin_unlock_irqrestore(&iosapic_lock, flags);
1242         return err;
1243 }
1244 #endif /* CONFIG_HOTPLUG */
1245
1246 #ifdef CONFIG_NUMA
1247 void __devinit
1248 map_iosapic_to_node(unsigned int gsi_base, int node)
1249 {
1250         int index;
1251
1252         index = find_iosapic(gsi_base);
1253         if (index < 0) {
1254                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1255                        __FUNCTION__, gsi_base);
1256                 return;
1257         }
1258         iosapic_lists[index].node = node;
1259         return;
1260 }
1261 #endif
1262
1263 static int __init iosapic_enable_kmalloc (void)
1264 {
1265         iosapic_kmalloc_ok = 1;
1266         return 0;
1267 }
1268 core_initcall (iosapic_enable_kmalloc);