4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
13 * In particular, we now have separate handlers for edge
14 * and level triggered interrupts.
15 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
16 * PCI to vector mapping, shared PCI interrupts.
17 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
18 * Clean up much of the old IOSAPIC cruft.
19 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
20 * ACPI S5(SoftOff) support.
21 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
22 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
23 * iosapic_set_affinity(), initializations for
24 * /proc/irq/#/smp_affinity
25 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
26 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
27 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
29 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
30 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
31 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
32 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
33 * Remove iosapic_address & gsi_base from external interfaces.
34 * Rationalize __init/__devinit attributes.
35 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
36 * Updated to work with irq migration necessary for CPU Hotplug
39 * Here is what the interrupt logic between a PCI device and the kernel looks like:
41 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
42 * device is uniquely identified by its bus--, and slot-number (the function
43 * number does not matter here because all functions share the same interrupt
46 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
47 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
48 * triggered and use the same polarity). Each interrupt line has a unique Global
49 * System Interrupt (GSI) number which can be calculated as the sum of the controller's
50 * base GSI number and the IOSAPIC pin number to which the line connects.
52 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
53 * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
55 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
56 * architecture-independent interrupt handling mechanism in Linux. As an
57 * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
58 * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
59 * IRQ. A platform can implement platform_irq_to_vector(irq) and
60 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
61 * Please see also include/asm-ia64/hw_irq.h for those APIs.
63 * To sum up, there are three levels of mappings involved:
65 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
67 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
68 * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
71 #include <linux/config.h>
73 #include <linux/acpi.h>
74 #include <linux/init.h>
75 #include <linux/irq.h>
76 #include <linux/kernel.h>
77 #include <linux/list.h>
78 #include <linux/pci.h>
79 #include <linux/smp.h>
80 #include <linux/smp_lock.h>
81 #include <linux/string.h>
83 #include <asm/delay.h>
84 #include <asm/hw_irq.h>
86 #include <asm/iosapic.h>
87 #include <asm/machvec.h>
88 #include <asm/processor.h>
89 #include <asm/ptrace.h>
90 #include <asm/system.h>
93 #undef DEBUG_INTERRUPT_ROUTING
96 #ifdef DEBUG_INTERRUPT_ROUTING
97 #define DBG(fmt...) printk(fmt)
102 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
104 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
106 static struct iosapic_intr_info {
107 char *addr; /* base address of IOSAPIC */
108 u32 low32; /* current value of low word of Redirection table entry */
109 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
110 char rte_index; /* IOSAPIC RTE index (-1 => not an IOSAPIC interrupt) */
111 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
112 unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */
113 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
114 } iosapic_intr_info[IA64_NUM_VECTORS];
116 static struct iosapic {
117 char *addr; /* base address of IOSAPIC */
118 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
119 unsigned short num_rte; /* number of RTE in this IOSAPIC */
120 } iosapic_lists[NR_IOSAPICS];
122 static int num_iosapic;
124 static unsigned char pcat_compat __initdata; /* 8259 compatibility flag */
128 * Find an IOSAPIC associated with a GSI
131 find_iosapic (unsigned int gsi)
135 for (i = 0; i < num_iosapic; i++) {
136 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
144 _gsi_to_vector (unsigned int gsi)
146 struct iosapic_intr_info *info;
148 for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
149 if (info->gsi_base + info->rte_index == gsi)
150 return info - iosapic_intr_info;
155 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
156 * entry exists, return -1.
159 gsi_to_vector (unsigned int gsi)
161 return _gsi_to_vector(gsi);
165 gsi_to_irq (unsigned int gsi)
168 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
171 return _gsi_to_vector(gsi);
175 set_rte (unsigned int vector, unsigned int dest, int mask)
177 unsigned long pol, trigger, dmode, flags;
183 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
185 rte_index = iosapic_intr_info[vector].rte_index;
187 return; /* not an IOSAPIC interrupt */
189 addr = iosapic_intr_info[vector].addr;
190 pol = iosapic_intr_info[vector].polarity;
191 trigger = iosapic_intr_info[vector].trigger;
192 dmode = iosapic_intr_info[vector].dmode;
193 vector &= (~IA64_IRQ_REDIRECTED);
195 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
201 for (irq = 0; irq < NR_IRQS; ++irq)
202 if (irq_to_vector(irq) == vector) {
203 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
209 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
210 (trigger << IOSAPIC_TRIGGER_SHIFT) |
211 (dmode << IOSAPIC_DELIVERY_SHIFT) |
212 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
215 /* dest contains both id and eid */
216 high32 = (dest << IOSAPIC_DEST_SHIFT);
218 spin_lock_irqsave(&iosapic_lock, flags);
220 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
221 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
222 iosapic_intr_info[vector].low32 = low32;
224 spin_unlock_irqrestore(&iosapic_lock, flags);
228 nop (unsigned int vector)
234 mask_irq (unsigned int irq)
240 ia64_vector vec = irq_to_vector(irq);
242 addr = iosapic_intr_info[vec].addr;
243 rte_index = iosapic_intr_info[vec].rte_index;
246 return; /* not an IOSAPIC interrupt! */
248 spin_lock_irqsave(&iosapic_lock, flags);
250 /* set only the mask bit */
251 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
252 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
254 spin_unlock_irqrestore(&iosapic_lock, flags);
258 unmask_irq (unsigned int irq)
264 ia64_vector vec = irq_to_vector(irq);
266 addr = iosapic_intr_info[vec].addr;
267 rte_index = iosapic_intr_info[vec].rte_index;
269 return; /* not an IOSAPIC interrupt! */
271 spin_lock_irqsave(&iosapic_lock, flags);
273 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
274 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
276 spin_unlock_irqrestore(&iosapic_lock, flags);
281 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
288 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
291 irq &= (~IA64_IRQ_REDIRECTED);
292 vec = irq_to_vector(irq);
294 if (cpus_empty(mask))
297 dest = cpu_physical_id(first_cpu(mask));
299 rte_index = iosapic_intr_info[vec].rte_index;
300 addr = iosapic_intr_info[vec].addr;
303 return; /* not an IOSAPIC interrupt */
305 set_irq_affinity_info(irq, dest, redir);
307 /* dest contains both id and eid */
308 high32 = dest << IOSAPIC_DEST_SHIFT;
310 spin_lock_irqsave(&iosapic_lock, flags);
312 low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
315 /* change delivery mode to lowest priority */
316 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
318 /* change delivery mode to fixed */
319 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
321 iosapic_intr_info[vec].low32 = low32;
322 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
323 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
325 spin_unlock_irqrestore(&iosapic_lock, flags);
330 * Handlers for level-triggered interrupts.
334 iosapic_startup_level_irq (unsigned int irq)
341 iosapic_end_level_irq (unsigned int irq)
343 ia64_vector vec = irq_to_vector(irq);
346 iosapic_eoi(iosapic_intr_info[vec].addr, vec);
349 #define iosapic_shutdown_level_irq mask_irq
350 #define iosapic_enable_level_irq unmask_irq
351 #define iosapic_disable_level_irq mask_irq
352 #define iosapic_ack_level_irq nop
354 struct hw_interrupt_type irq_type_iosapic_level = {
355 .typename = "IO-SAPIC-level",
356 .startup = iosapic_startup_level_irq,
357 .shutdown = iosapic_shutdown_level_irq,
358 .enable = iosapic_enable_level_irq,
359 .disable = iosapic_disable_level_irq,
360 .ack = iosapic_ack_level_irq,
361 .end = iosapic_end_level_irq,
362 .set_affinity = iosapic_set_affinity
366 * Handlers for edge-triggered interrupts.
370 iosapic_startup_edge_irq (unsigned int irq)
374 * IOSAPIC simply drops interrupts pended while the
375 * corresponding pin was masked, so we can't know if an
376 * interrupt is pending already. Let's hope not...
382 iosapic_ack_edge_irq (unsigned int irq)
384 irq_desc_t *idesc = irq_descp(irq);
388 * Once we have recorded IRQ_PENDING already, we can mask the
389 * interrupt for real. This prevents IRQ storms from unhandled
392 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
396 #define iosapic_enable_edge_irq unmask_irq
397 #define iosapic_disable_edge_irq nop
398 #define iosapic_end_edge_irq nop
400 struct hw_interrupt_type irq_type_iosapic_edge = {
401 .typename = "IO-SAPIC-edge",
402 .startup = iosapic_startup_edge_irq,
403 .shutdown = iosapic_disable_edge_irq,
404 .enable = iosapic_enable_edge_irq,
405 .disable = iosapic_disable_edge_irq,
406 .ack = iosapic_ack_edge_irq,
407 .end = iosapic_end_edge_irq,
408 .set_affinity = iosapic_set_affinity
412 iosapic_version (char *addr)
415 * IOSAPIC Version Register return 32 bit structure like:
417 * unsigned int version : 8;
418 * unsigned int reserved1 : 8;
419 * unsigned int max_redir : 8;
420 * unsigned int reserved2 : 8;
423 return iosapic_read(addr, IOSAPIC_VERSION);
427 * if the given vector is already owned by other,
428 * assign a new vector for the other and make the vector available
431 iosapic_reassign_vector (int vector)
435 if (iosapic_intr_info[vector].rte_index >= 0 || iosapic_intr_info[vector].addr
436 || iosapic_intr_info[vector].gsi_base || iosapic_intr_info[vector].dmode
437 || iosapic_intr_info[vector].polarity || iosapic_intr_info[vector].trigger)
439 new_vector = assign_irq_vector(AUTO_ASSIGN);
440 printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
441 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
442 sizeof(struct iosapic_intr_info));
443 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
444 iosapic_intr_info[vector].rte_index = -1;
449 register_intr (unsigned int gsi, int vector, unsigned char delivery,
450 unsigned long polarity, unsigned long trigger)
453 struct hw_interrupt_type *irq_type;
456 unsigned long gsi_base;
457 char *iosapic_address;
459 index = find_iosapic(gsi);
461 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi);
465 iosapic_address = iosapic_lists[index].addr;
466 gsi_base = iosapic_lists[index].gsi_base;
468 rte_index = gsi - gsi_base;
469 iosapic_intr_info[vector].rte_index = rte_index;
470 iosapic_intr_info[vector].polarity = polarity;
471 iosapic_intr_info[vector].dmode = delivery;
472 iosapic_intr_info[vector].addr = iosapic_address;
473 iosapic_intr_info[vector].gsi_base = gsi_base;
474 iosapic_intr_info[vector].trigger = trigger;
476 if (trigger == IOSAPIC_EDGE)
477 irq_type = &irq_type_iosapic_edge;
479 irq_type = &irq_type_iosapic_level;
481 idesc = irq_descp(vector);
482 if (idesc->handler != irq_type) {
483 if (idesc->handler != &no_irq_type)
484 printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
485 __FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
486 idesc->handler = irq_type;
491 get_target_cpu (void)
497 * If the platform supports redirection via XTP, let it
498 * distribute interrupts.
500 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
501 return hard_smp_processor_id();
504 * Some interrupts (ACPI SCI, for instance) are registered
505 * before the BSP is marked as online.
507 if (!cpu_online(smp_processor_id()))
508 return hard_smp_processor_id();
511 * Otherwise, round-robin interrupt vectors across all the
512 * processors. (It'd be nice if we could be smarter in the
516 if (++cpu >= NR_CPUS)
518 } while (!cpu_online(cpu));
520 return cpu_physical_id(cpu);
522 return hard_smp_processor_id();
527 * ACPI can describe IOSAPIC interrupts via static tables and namespace
528 * methods. This provides an interface to register those interrupts and
529 * program the IOSAPIC RTE.
532 iosapic_register_intr (unsigned int gsi,
533 unsigned long polarity, unsigned long trigger)
540 * If this GSI has already been registered (i.e., it's a
541 * shared interrupt, or we lost a race to register it),
542 * don't touch the RTE.
544 spin_lock_irqsave(&iosapic_lock, flags);
546 vector = gsi_to_vector(gsi);
548 spin_unlock_irqrestore(&iosapic_lock, flags);
552 vector = assign_irq_vector(AUTO_ASSIGN);
553 dest = get_target_cpu();
554 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
557 spin_unlock_irqrestore(&iosapic_lock, flags);
559 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
560 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
561 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
562 cpu_logical_id(dest), dest, vector);
564 set_rte(vector, dest, 1);
569 * ACPI calls this when it finds an entry for a platform interrupt.
570 * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
573 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
574 int iosapic_vector, u16 eid, u16 id,
575 unsigned long polarity, unsigned long trigger)
577 static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
578 unsigned char delivery;
579 int vector, mask = 0;
580 unsigned int dest = ((id << 8) | eid) & 0xffff;
583 case ACPI_INTERRUPT_PMI:
584 vector = iosapic_vector;
586 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
587 * we need to make sure the vector is available
589 iosapic_reassign_vector(vector);
590 delivery = IOSAPIC_PMI;
592 case ACPI_INTERRUPT_INIT:
593 vector = assign_irq_vector(AUTO_ASSIGN);
594 delivery = IOSAPIC_INIT;
596 case ACPI_INTERRUPT_CPEI:
597 vector = IA64_CPE_VECTOR;
598 delivery = IOSAPIC_LOWEST_PRIORITY;
602 printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type);
606 register_intr(gsi, vector, delivery, polarity, trigger);
608 printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
609 int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
610 int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
611 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
612 cpu_logical_id(dest), dest, vector);
614 set_rte(vector, dest, mask);
620 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
621 * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
624 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
625 unsigned long polarity,
626 unsigned long trigger)
629 unsigned int dest = hard_smp_processor_id();
631 vector = isa_irq_to_vector(isa_irq);
633 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
635 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
636 isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
637 polarity == IOSAPIC_POL_HIGH ? "high" : "low",
638 cpu_logical_id(dest), dest, vector);
640 set_rte(vector, dest, 1);
644 iosapic_system_init (int system_pcat_compat)
648 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
649 iosapic_intr_info[vector].rte_index = -1; /* mark as unused */
651 pcat_compat = system_pcat_compat;
654 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
657 printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
664 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
667 unsigned int isa_irq, ver;
670 addr = ioremap(phys_addr, 0);
671 ver = iosapic_version(addr);
674 * The MAX_REDIR register holds the highest input pin
675 * number (starting from 0).
676 * We add 1 so that we can use it for number of pins (= RTEs)
678 num_rte = ((ver >> 16) & 0xff) + 1;
680 iosapic_lists[num_iosapic].addr = addr;
681 iosapic_lists[num_iosapic].gsi_base = gsi_base;
682 iosapic_lists[num_iosapic].num_rte = num_rte;
685 if ((gsi_base == 0) && pcat_compat) {
687 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
688 * get reprogrammed later on with data from the ACPI Interrupt Source
691 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
692 iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);