arch/ia64/kernel/irq_ia64.c

   1 /*
   2  * linux/arch/ia64/kernel/irq.c
   3  *
   4  * Copyright (C) 1998-2001 Hewlett-Packard Co
   5  *      Stephane Eranian <eranian@hpl.hp.com>
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  *  6/10/99: Updated to bring in sync with x86 version to facilitate
   9  *           support for SMP and different interrupt controllers.
  10  *
  11  * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
  12  *                      PCI to vector allocation routine.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/module.h>
  17
  18 #include <linux/jiffies.h>
  19 #include <linux/errno.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/slab.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/random.h>       /* for rand_initialize_irq() */
  27 #include <linux/signal.h>
  28 #include <linux/smp.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/threads.h>
  31
  32 #include <asm/bitops.h>
  33 #include <asm/delay.h>
  34 #include <asm/intrinsics.h>
  35 #include <asm/io.h>
  36 #include <asm/hw_irq.h>
  37 #include <asm/machvec.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/system.h>
  40
  41 #ifdef CONFIG_PERFMON
  42 # include <asm/perfmon.h>
  43 #endif
  44
  45 #define IRQ_DEBUG       0
  46
  47 /* default base addr of IPI table */
  48 unsigned long ipi_base_addr = (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR);
  49
  50 /*
  51  * Legacy IRQ to IA-64 vector translation table.
  52  */
  53 __u8 isa_irq_to_vector_map[16] = {
  54         /* 8259 IRQ translation, first 16 entries */
  55         0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
  56         0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
  57 };
  58 EXPORT_SYMBOL(isa_irq_to_vector_map);
  59
  60 static inline void
  61 irq_enter (void)
  62 {
  63         preempt_count() += HARDIRQ_OFFSET;
  64 }
  65
  66 static inline void
  67 irq_exit (void)
  68 {
  69         preempt_count() -= IRQ_EXIT_OFFSET;
  70         if (!in_interrupt() && local_softirq_pending())
  71                 do_softirq();
  72         preempt_enable_no_resched();
  73 }
  74
  75 int
  76 assign_irq_vector (int irq)
  77 {
  78         static int next_vector = IA64_FIRST_DEVICE_VECTOR;
  79
  80         if (next_vector > IA64_LAST_DEVICE_VECTOR)
  81                 /* XXX could look for sharable vectors instead of panic'ing... */
  82                 panic("assign_irq_vector: out of interrupt vectors!");
  83         return next_vector++;
  84 }
  85
  86 extern unsigned int do_IRQ(unsigned long irq, struct pt_regs *regs);
  87
  88 /*
  89  * That's where the IVT branches when we get an external
  90  * interrupt. This branches to the correct hardware IRQ handler via
  91  * function ptr.
  92  */
  93 void
  94 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
  95 {
  96         unsigned long saved_tpr;
  97 #ifdef CONFIG_SMP
  98 #       define IS_RESCHEDULE(vec)       (vec == IA64_IPI_RESCHEDULE)
  99 #else
 100 #       define IS_RESCHEDULE(vec)       (0)
 101 #endif
 102
 103 #if IRQ_DEBUG
 104         {
 105                 unsigned long bsp, sp;
 106
 107                 /*
 108                  * Note: if the interrupt happened while executing in
 109                  * the context switch routine (ia64_switch_to), we may
 110                  * get a spurious stack overflow here.  This is
 111                  * because the register and the memory stack are not
 112                  * switched atomically.
 113                  */
 114                 bsp = ia64_getreg(_IA64_REG_AR_BSP);
 115                 sp = ia64_getreg(_IA64_REG_AR_SP);
 116
 117                 if ((sp - bsp) < 1024) {
 118                         static unsigned char count;
 119                         static long last_time;
 120
 121                         if (jiffies - last_time > 5*HZ)
 122                                 count = 0;
 123                         if (++count < 5) {
 124                                 last_time = jiffies;
 125                                 printk("ia64_handle_irq: DANGER: less than "
 126                                        "1KB of free stack space!!\n"
 127                                        "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
 128                         }
 129                 }
 130         }
 131 #endif /* IRQ_DEBUG */
 132
 133         /*
 134          * Always set TPR to limit maximum interrupt nesting depth to
 135          * 16 (without this, it would be ~240, which could easily lead
 136          * to kernel stack overflows).
 137          */
 138         irq_enter();
 139         saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 140         ia64_srlz_d();
 141         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 142                 if (!IS_RESCHEDULE(vector)) {
 143                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 144                         ia64_srlz_d();
 145
 146                         do_IRQ(local_vector_to_irq(vector), regs);
 147
 148                         /*
 149                          * Disable interrupts and send EOI:
 150                          */
 151                         local_irq_disable();
 152                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 153                 }
 154                 ia64_eoi();
 155                 vector = ia64_get_ivr();
 156         }
 157         /*
 158          * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
 159          * handler needs to be able to wait for further keyboard interrupts, which can't
 160          * come through until ia64_eoi() has been done.
 161          */
 162         irq_exit();
 163 }
 164
 165 #ifdef CONFIG_SMP
 166 extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
 167
 168 static struct irqaction ipi_irqaction = {
 169         .handler =      handle_IPI,
 170         .flags =        SA_INTERRUPT,
 171         .name =         "IPI"
 172 };
 173 #endif
 174
 175 void
 176 register_percpu_irq (ia64_vector vec, struct irqaction *action)
 177 {
 178         irq_desc_t *desc;
 179         unsigned int irq;
 180
 181         for (irq = 0; irq < NR_IRQS; ++irq)
 182                 if (irq_to_vector(irq) == vec) {
 183                         desc = irq_descp(irq);
 184                         desc->status |= IRQ_PER_CPU;
 185                         desc->handler = &irq_type_ia64_lsapic;
 186                         if (action)
 187                                 setup_irq(irq, action);
 188                 }
 189 }
 190
 191 void __init
 192 init_IRQ (void)
 193 {
 194         register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
 195 #ifdef CONFIG_SMP
 196         register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
 197 #endif
 198 #ifdef CONFIG_PERFMON
 199         pfm_init_percpu();
 200 #endif
 201         platform_irq_init();
 202 }
 203
 204 void
 205 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
 206 {
 207         unsigned long ipi_addr;
 208         unsigned long ipi_data;
 209         unsigned long phys_cpu_id;
 210
 211 #ifdef CONFIG_SMP
 212         phys_cpu_id = cpu_physical_id(cpu);
 213 #else
 214         phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
 215 #endif
 216
 217         /*
 218          * cpu number is in 8bit ID and 8bit EID
 219          */
 220
 221         ipi_data = (delivery_mode << 8) | (vector & 0xff);
 222         ipi_addr = ipi_base_addr | (phys_cpu_id << 4) | ((redirect & 1)  << 3);
 223
 224         writeq(ipi_data, ipi_addr);
 225 }