arch/ia64/kernel/irq_ia64.c

   1 /*
   2  * linux/arch/ia64/kernel/irq.c
   3  *
   4  * Copyright (C) 1998-2001 Hewlett-Packard Co
   5  *      Stephane Eranian <eranian@hpl.hp.com>
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  *  6/10/99: Updated to bring in sync with x86 version to facilitate
   9  *           support for SMP and different interrupt controllers.
  10  *
  11  * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
  12  *                      PCI to vector allocation routine.
  13  * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
  14  *                                              Added CPU Hotplug handling for IPF.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/module.h>
  19
  20 #include <linux/jiffies.h>
  21 #include <linux/errno.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/kernel_stat.h>
  26 #include <linux/slab.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/random.h>       /* for rand_initialize_irq() */
  29 #include <linux/signal.h>
  30 #include <linux/smp.h>
  31 #include <linux/smp_lock.h>
  32 #include <linux/threads.h>
  33
  34 #include <asm/bitops.h>
  35 #include <asm/delay.h>
  36 #include <asm/intrinsics.h>
  37 #include <asm/io.h>
  38 #include <asm/hw_irq.h>
  39 #include <asm/machvec.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/system.h>
  42
  43 #ifdef CONFIG_PERFMON
  44 # include <asm/perfmon.h>
  45 #endif
  46
  47 #define IRQ_DEBUG       0
  48
  49 /* default base addr of IPI table */
  50 unsigned long ipi_base_addr = (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR);
  51
  52 /*
  53  * Legacy IRQ to IA-64 vector translation table.
  54  */
  55 __u8 isa_irq_to_vector_map[16] = {
  56         /* 8259 IRQ translation, first 16 entries */
  57         0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
  58         0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
  59 };
  60 EXPORT_SYMBOL(isa_irq_to_vector_map);
  61
  62 static inline void
  63 irq_enter (void)
  64 {
  65         preempt_count() += HARDIRQ_OFFSET;
  66 }
  67
  68 static inline void
  69 irq_exit (void)
  70 {
  71         preempt_count() -= IRQ_EXIT_OFFSET;
  72         if (!in_interrupt() && local_softirq_pending())
  73                 do_softirq();
  74         preempt_enable_no_resched();
  75 }
  76
  77 int
  78 assign_irq_vector (int irq)
  79 {
  80         static int next_vector = IA64_FIRST_DEVICE_VECTOR;
  81
  82         if (next_vector > IA64_LAST_DEVICE_VECTOR)
  83                 /* XXX could look for sharable vectors instead of panic'ing... */
  84                 panic("assign_irq_vector: out of interrupt vectors!");
  85         return next_vector++;
  86 }
  87
  88 extern unsigned int do_IRQ(unsigned long irq, struct pt_regs *regs);
  89
  90 #ifdef CONFIG_SMP
  91 #       define IS_RESCHEDULE(vec)       (vec == IA64_IPI_RESCHEDULE)
  92 #else
  93 #       define IS_RESCHEDULE(vec)       (0)
  94 #endif
  95 /*
  96  * That's where the IVT branches when we get an external
  97  * interrupt. This branches to the correct hardware IRQ handler via
  98  * function ptr.
  99  */
 100 void
 101 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
 102 {
 103         unsigned long saved_tpr;
 104
 105 #if IRQ_DEBUG
 106         {
 107                 unsigned long bsp, sp;
 108
 109                 /*
 110                  * Note: if the interrupt happened while executing in
 111                  * the context switch routine (ia64_switch_to), we may
 112                  * get a spurious stack overflow here.  This is
 113                  * because the register and the memory stack are not
 114                  * switched atomically.
 115                  */
 116                 bsp = ia64_getreg(_IA64_REG_AR_BSP);
 117                 sp = ia64_getreg(_IA64_REG_AR_SP);
 118
 119                 if ((sp - bsp) < 1024) {
 120                         static unsigned char count;
 121                         static long last_time;
 122
 123                         if (jiffies - last_time > 5*HZ)
 124                                 count = 0;
 125                         if (++count < 5) {
 126                                 last_time = jiffies;
 127                                 printk("ia64_handle_irq: DANGER: less than "
 128                                        "1KB of free stack space!!\n"
 129                                        "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
 130                         }
 131                 }
 132         }
 133 #endif /* IRQ_DEBUG */
 134
 135         /*
 136          * Always set TPR to limit maximum interrupt nesting depth to
 137          * 16 (without this, it would be ~240, which could easily lead
 138          * to kernel stack overflows).
 139          */
 140         irq_enter();
 141         saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 142         ia64_srlz_d();
 143         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 144                 if (!IS_RESCHEDULE(vector)) {
 145                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 146                         ia64_srlz_d();
 147
 148                         do_IRQ(local_vector_to_irq(vector), regs);
 149
 150                         /*
 151                          * Disable interrupts and send EOI:
 152                          */
 153                         local_irq_disable();
 154                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 155                 }
 156                 ia64_eoi();
 157                 vector = ia64_get_ivr();
 158         }
 159         /*
 160          * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
 161          * handler needs to be able to wait for further keyboard interrupts, which can't
 162          * come through until ia64_eoi() has been done.
 163          */
 164         irq_exit();
 165 }
 166
 167 #ifdef CONFIG_HOTPLUG_CPU
 168 /*
 169  * This function emulates a interrupt processing when a cpu is about to be
 170  * brought down.
 171  */
 172 void ia64_process_pending_intr(void)
 173 {
 174         ia64_vector vector;
 175         unsigned long saved_tpr;
 176         extern unsigned int vectors_in_migration[NR_IRQS];
 177
 178         vector = ia64_get_ivr();
 179
 180          irq_enter();
 181          saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 182          ia64_srlz_d();
 183
 184          /*
 185           * Perform normal interrupt style processing
 186           */
 187         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 188                 if (!IS_RESCHEDULE(vector)) {
 189                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 190                         ia64_srlz_d();
 191
 192                         /*
 193                          * Now try calling normal ia64_handle_irq as it would have got called
 194                          * from a real intr handler. Try passing null for pt_regs, hopefully
 195                          * it will work. I hope it works!.
 196                          * Probably could shared code.
 197                          */
 198                         vectors_in_migration[local_vector_to_irq(vector)]=0;
 199                         do_IRQ(local_vector_to_irq(vector), NULL);
 200
 201                         /*
 202                          * Disable interrupts and send EOI
 203                          */
 204                         local_irq_disable();
 205                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 206                 }
 207                 ia64_eoi();
 208                 vector = ia64_get_ivr();
 209         }
 210         irq_exit();
 211 }
 212 #endif
 213
 214
 215 #ifdef CONFIG_SMP
 216 extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
 217
 218 static struct irqaction ipi_irqaction = {
 219         .handler =      handle_IPI,
 220         .flags =        SA_INTERRUPT,
 221         .name =         "IPI"
 222 };
 223 #endif
 224
 225 void
 226 register_percpu_irq (ia64_vector vec, struct irqaction *action)
 227 {
 228         irq_desc_t *desc;
 229         unsigned int irq;
 230
 231         for (irq = 0; irq < NR_IRQS; ++irq)
 232                 if (irq_to_vector(irq) == vec) {
 233                         desc = irq_descp(irq);
 234                         desc->status |= IRQ_PER_CPU;
 235                         desc->handler = &irq_type_ia64_lsapic;
 236                         if (action)
 237                                 setup_irq(irq, action);
 238                 }
 239 }
 240
 241 void __init
 242 init_IRQ (void)
 243 {
 244         register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
 245 #ifdef CONFIG_SMP
 246         register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
 247 #endif
 248 #ifdef CONFIG_PERFMON
 249         pfm_init_percpu();
 250 #endif
 251         platform_irq_init();
 252 }
 253
 254 void
 255 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
 256 {
 257         unsigned long ipi_addr;
 258         unsigned long ipi_data;
 259         unsigned long phys_cpu_id;
 260
 261 #ifdef CONFIG_SMP
 262         phys_cpu_id = cpu_physical_id(cpu);
 263 #else
 264         phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
 265 #endif
 266
 267         /*
 268          * cpu number is in 8bit ID and 8bit EID
 269          */
 270
 271         ipi_data = (delivery_mode << 8) | (vector & 0xff);
 272         ipi_addr = ipi_base_addr | (phys_cpu_id << 4) | ((redirect & 1)  << 3);
 273
 274         writeq(ipi_data, ipi_addr);
 275 }