2 * arch/ia64/kernel/ivt.S
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
17 * This file defines the interruption vector table used by the CPU.
18 * It does not include one entry per possible cause of interruption.
20 * The first 20 entries of the table contain 64 bundles each while the
21 * remaining 48 entries contain only 16 bundles each.
23 * The 64 bundles are used to allow inlining the whole handler for critical
24 * interruptions like TLB misses.
26 * For each entry, the comment is as follows:
28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
29 * entry offset ----/ / / / /
30 * entry number ---------/ / / /
31 * size of the entry -------------/ / /
32 * vector name -------------------------------------/ /
33 * interruptions triggering this vector ----------------------/
35 * The table is 32KB in size and must be aligned on 32KB boundary.
36 * (The CPU ignores the 15 lower bits of the address)
38 * Table is based upon EAS2.6 (Oct 1999)
41 #include <linux/config.h>
43 #include <asm/asmmacro.h>
44 #include <asm/break.h>
46 #include <asm/kregs.h>
47 #include <asm/offsets.h>
48 #include <asm/pgtable.h>
49 #include <asm/processor.h>
50 #include <asm/ptrace.h>
51 #include <asm/system.h>
52 #include <asm/thread_info.h>
53 #include <asm/unistd.h>
56 # define PSR_DEFAULT_BITS psr.ac
58 # define PSR_DEFAULT_BITS 0
63 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
64 * needed for something else before enabling this...
66 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
71 #define MINSTATE_VIRT /* needed by minstate.h */
76 mov r19=n;; /* prepare to save predicates */ \
77 br.sptk.many dispatch_to_fault_handler
79 .section .text.ivt,"ax"
81 .align 32768 // align on 32KB boundary
84 /////////////////////////////////////////////////////////////////////////////////////////
85 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
89 * The VHPT vector is invoked when the TLB entry for the virtual page table
90 * is missing. This happens only as a result of a previous
91 * (the "original") TLB miss, which may either be caused by an instruction
92 * fetch or a data access (or non-access).
94 * What we do here is normal TLB miss handing for the _original_ miss, followed
95 * by inserting the TLB entry for the virtual page table page that the VHPT
96 * walker was attempting to access. The latter gets inserted as long
97 * as both L1 and L2 have valid mappings for the faulting address.
98 * The TLB entry for the original miss gets inserted only if
99 * the L3 entry indicates that the page is present.
101 * do_page_fault gets invoked in the following cases:
102 * - the faulting virtual address uses unimplemented address bits
103 * - the faulting virtual address has no L1, L2, or L3 mapping
105 mov r16=cr.ifa // get address that caused the TLB miss
106 #ifdef CONFIG_HUGETLB_PAGE
111 rsm psr.dt // use physical addressing for data
112 mov r31=pr // save the predicate registers
113 mov r19=IA64_KR(PT_BASE) // get page table base address
114 shl r21=r16,3 // shift bit 60 into sign bit
115 shr.u r17=r16,61 // get the region number into r17
118 #ifdef CONFIG_HUGETLB_PAGE
124 (p8) dep r25=r18,r25,2,6
128 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
129 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
131 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
134 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
136 .pred.rel "mutex", p6, p7
137 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
138 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
140 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
141 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
142 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
143 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
145 ld8 r17=[r17] // fetch the L1 entry (may be 0)
147 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
148 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
150 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
151 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
153 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
154 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
156 (p7) ld8 r18=[r21] // read the L3 PTE
157 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
159 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
160 mov r22=cr.iha // get the VHPT address that caused the TLB miss
161 ;; // avoid RAW on p7
162 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
163 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
165 (p10) itc.i r18 // insert the instruction TLB entry
166 (p11) itc.d r18 // insert the data TLB entry
167 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
170 #ifdef CONFIG_HUGETLB_PAGE
171 (p8) mov cr.itir=r25 // change to default page-size for VHPT
175 * Now compute and insert the TLB entry for the virtual page table. We never
176 * execute in a page table page so there is no need to set the exception deferral
179 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
185 * Tell the assemblers dependency-violation checker that the above "itc" instructions
186 * cannot possibly affect the following loads:
191 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
192 * between reading the pagetable and the "itc". If so, flush the entry we
193 * inserted and retry.
195 ld8 r25=[r21] // read L3 PTE again
196 ld8 r26=[r17] // read L2 entry again
198 cmp.ne p6,p7=r26,r20 // did L2 entry change
199 mov r27=PAGE_SHIFT<<2
201 (p6) ptc.l r22,r27 // purge PTE page translation
202 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
204 (p6) ptc.l r16,r27 // purge translation
207 mov pr=r31,-1 // restore predicate registers
212 /////////////////////////////////////////////////////////////////////////////////////////
213 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
217 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
218 * page table. If a nested TLB miss occurs, we switch into physical
219 * mode, walk the page table, and then re-execute the L3 PTE read
220 * and go on normally after that.
222 mov r16=cr.ifa // get virtual address
223 mov r29=b0 // save b0
224 mov r31=pr // save predicates
226 mov r17=cr.iha // get virtual address of L3 PTE
227 movl r30=1f // load nested fault continuation point
229 1: ld8 r18=[r17] // read L3 PTE
232 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
233 (p6) br.cond.spnt page_fault
239 * Tell the assemblers dependency-violation checker that the above "itc" instructions
240 * cannot possibly affect the following loads:
244 ld8 r19=[r17] // read L3 PTE again and see if same
245 mov r20=PAGE_SHIFT<<2 // setup page size for purge
256 /////////////////////////////////////////////////////////////////////////////////////////
257 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
261 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
262 * page table. If a nested TLB miss occurs, we switch into physical
263 * mode, walk the page table, and then re-execute the L3 PTE read
264 * and go on normally after that.
266 mov r16=cr.ifa // get virtual address
267 mov r29=b0 // save b0
268 mov r31=pr // save predicates
270 mov r17=cr.iha // get virtual address of L3 PTE
271 movl r30=1f // load nested fault continuation point
273 1: ld8 r18=[r17] // read L3 PTE
276 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
277 (p6) br.cond.spnt page_fault
283 * Tell the assemblers dependency-violation checker that the above "itc" instructions
284 * cannot possibly affect the following loads:
288 ld8 r19=[r17] // read L3 PTE again and see if same
289 mov r20=PAGE_SHIFT<<2 // setup page size for purge
300 /////////////////////////////////////////////////////////////////////////////////////////
301 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
304 mov r16=cr.ifa // get address that caused the TLB miss
307 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
310 #ifdef CONFIG_DISABLE_VHPT
311 shr.u r22=r16,61 // get the region number into r21
313 cmp.gt p8,p0=6,r22 // user mode
318 (p8) mov r29=b0 // save b0
319 (p8) br.cond.dptk .itlb_fault
321 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
322 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
323 shr.u r18=r16,57 // move address bit 61 to bit 4
325 andcm r18=0x10,r18 // bit 4=~address-bit(61)
326 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
327 or r19=r17,r19 // insert PTE control bits into r19
329 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
330 (p8) br.cond.spnt page_fault
332 itc.i r19 // insert the TLB entry
338 /////////////////////////////////////////////////////////////////////////////////////////
339 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
342 mov r16=cr.ifa // get address that caused the TLB miss
345 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
349 #ifdef CONFIG_DISABLE_VHPT
350 shr.u r22=r16,61 // get the region number into r21
352 cmp.gt p8,p0=6,r22 // access to region 0-5
357 (p8) mov r29=b0 // save b0
358 (p8) br.cond.dptk dtlb_fault
360 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
361 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
362 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
363 shr.u r18=r16,57 // move address bit 61 to bit 4
364 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
365 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
367 andcm r18=0x10,r18 // bit 4=~address-bit(61)
369 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
370 (p8) br.cond.spnt page_fault
372 dep r21=-1,r21,IA64_PSR_ED_BIT,1
373 or r19=r19,r17 // insert PTE control bits into r19
375 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
378 (p7) itc.d r19 // insert the TLB entry
384 /////////////////////////////////////////////////////////////////////////////////////////
385 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
386 ENTRY(nested_dtlb_miss)
388 * In the absence of kernel bugs, we get here when the virtually mapped linear
389 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
390 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
391 * table is missing, a nested TLB miss fault is triggered and control is
392 * transferred to this point. When this happens, we lookup the pte for the
393 * faulting address by walking the page table in physical mode and return to the
394 * continuation point passed in register r30 (or call page_fault if the address is
397 * Input: r16: faulting address
399 * r30: continuation address
402 * Output: r17: physical address of L3 PTE of faulting address
404 * r30: continuation address
407 * Clobbered: b0, r18, r19, r21, psr.dt (cleared)
409 rsm psr.dt // switch to using physical data addressing
410 mov r19=IA64_KR(PT_BASE) // get the page table base address
411 shl r21=r16,3 // shift bit 60 into sign bit
413 shr.u r17=r16,61 // get the region number into r17
415 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
416 shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address
418 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
421 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
423 .pred.rel "mutex", p6, p7
424 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
425 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
427 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
428 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
429 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
430 shr.u r18=r16,PMD_SHIFT // shift L2 index into position
432 ld8 r17=[r17] // fetch the L1 entry (may be 0)
434 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
435 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
437 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
438 shr.u r19=r16,PAGE_SHIFT // shift L3 index into position
440 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
441 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
442 (p6) br.cond.spnt page_fault
444 br.sptk.many b0 // return to continuation point
445 END(nested_dtlb_miss)
448 /////////////////////////////////////////////////////////////////////////////////////////
449 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
455 //-----------------------------------------------------------------------------------
456 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
463 alloc r15=ar.pfs,0,0,3,0
466 adds r3=8,r2 // set up second base pointer
468 ssm psr.ic | PSR_DEFAULT_BITS
470 srlz.i // guarantee that interruption collectin is on
472 (p15) ssm psr.i // restore psr.i
473 movl r14=ia64_leave_kernel
478 adds out2=16,r12 // out2 = pointer to pt_regs
479 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
483 /////////////////////////////////////////////////////////////////////////////////////////
484 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
491 /////////////////////////////////////////////////////////////////////////////////////////
492 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
496 * What we do here is to simply turn on the dirty bit in the PTE. We need to
497 * update both the page-table and the TLB entry. To efficiently access the PTE,
498 * we address it through the virtual page table. Most likely, the TLB entry for
499 * the relevant virtual page table page is still present in the TLB so we can
500 * normally do this without additional TLB misses. In case the necessary virtual
501 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
502 * up the physical address of the L3 PTE and then continue at label 1 below.
504 mov r16=cr.ifa // get the address that caused the fault
505 movl r30=1f // load continuation point in case of nested fault
507 thash r17=r16 // compute virtual address of L3 PTE
508 mov r29=b0 // save b0 in case of nested fault
509 mov r31=pr // save pr
511 mov r28=ar.ccv // save ar.ccv
514 ;; // avoid RAW on r18
515 mov ar.ccv=r18 // set compare value for cmpxchg
516 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
518 cmpxchg8.acq r26=[r17],r25,ar.ccv
519 mov r24=PAGE_SHIFT<<2
523 (p6) itc.d r25 // install updated PTE
526 * Tell the assemblers dependency-violation checker that the above "itc" instructions
527 * cannot possibly affect the following loads:
531 ld8 r18=[r17] // read PTE again
533 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
536 mov b0=r29 // restore b0
541 ;; // avoid RAW on r18
542 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
543 mov b0=r29 // restore b0
545 st8 [r17]=r18 // store back updated PTE
546 itc.d r18 // install updated PTE
548 mov pr=r31,-1 // restore pr
553 /////////////////////////////////////////////////////////////////////////////////////////
554 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
557 // Like Entry 8, except for instruction access
558 mov r16=cr.ifa // get the address that caused the fault
559 movl r30=1f // load continuation point in case of nested fault
560 mov r31=pr // save predicates
561 #ifdef CONFIG_ITANIUM
563 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
568 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
570 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
571 #endif /* CONFIG_ITANIUM */
573 thash r17=r16 // compute virtual address of L3 PTE
574 mov r29=b0 // save b0 in case of nested fault)
576 mov r28=ar.ccv // save ar.ccv
580 mov ar.ccv=r18 // set compare value for cmpxchg
581 or r25=_PAGE_A,r18 // set the accessed bit
583 cmpxchg8.acq r26=[r17],r25,ar.ccv
584 mov r24=PAGE_SHIFT<<2
588 (p6) itc.i r25 // install updated PTE
591 * Tell the assemblers dependency-violation checker that the above "itc" instructions
592 * cannot possibly affect the following loads:
596 ld8 r18=[r17] // read PTE again
598 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
601 mov b0=r29 // restore b0
603 #else /* !CONFIG_SMP */
607 or r18=_PAGE_A,r18 // set the accessed bit
608 mov b0=r29 // restore b0
610 st8 [r17]=r18 // store back updated PTE
611 itc.i r18 // install updated PTE
612 #endif /* !CONFIG_SMP */
618 /////////////////////////////////////////////////////////////////////////////////////////
619 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
622 // Like Entry 8, except for data access
623 mov r16=cr.ifa // get the address that caused the fault
624 movl r30=1f // load continuation point in case of nested fault
626 thash r17=r16 // compute virtual address of L3 PTE
628 mov r29=b0 // save b0 in case of nested fault)
630 mov r28=ar.ccv // save ar.ccv
633 ;; // avoid RAW on r18
634 mov ar.ccv=r18 // set compare value for cmpxchg
635 or r25=_PAGE_A,r18 // set the dirty bit
637 cmpxchg8.acq r26=[r17],r25,ar.ccv
638 mov r24=PAGE_SHIFT<<2
642 (p6) itc.d r25 // install updated PTE
644 * Tell the assemblers dependency-violation checker that the above "itc" instructions
645 * cannot possibly affect the following loads:
649 ld8 r18=[r17] // read PTE again
651 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
658 ;; // avoid RAW on r18
659 or r18=_PAGE_A,r18 // set the accessed bit
661 st8 [r17]=r18 // store back updated PTE
662 itc.d r18 // install updated PTE
664 mov b0=r29 // restore b0
670 /////////////////////////////////////////////////////////////////////////////////////////
671 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
674 * The streamlined system call entry/exit paths only save/restore the initial part
675 * of pt_regs. This implies that the callers of system-calls must adhere to the
676 * normal procedure calling conventions.
678 * Registers to be saved & restored:
679 * CR registers: cr.ipsr, cr.iip, cr.ifs
680 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
681 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
682 * Registers to be restored only:
683 * r8-r11: output value from the system call.
685 * During system call exit, scratch registers (including r15) are modified/cleared
686 * to prevent leaking bits from kernel to user level.
689 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat.
691 mov r18=__IA64_BREAK_SYSCALL
699 mov r31=pr // prepare to save predicates
702 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
703 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so)
704 (p7) br.cond.spnt non_syscall
706 ld1 r17=[r16] // load current->thread.on_ustack flag
707 st1 [r16]=r0 // clear current->thread.on_ustack flag
708 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT
712 /* adjust return address so we skip over the break instruction: */
714 extr.u r8=r29,41,2 // extract ei field from cr.ipsr
716 cmp.eq p6,p7=2,r8 // isr.ei==2?
717 mov r2=r1 // setup r2 for ia64_syscall_setup
719 (p6) mov r8=0 // clear ei to 0
720 (p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
721 (p7) adds r8=1,r8 // increment ei to next slot
723 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
724 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
727 // switch from user to kernel RBS:
728 MINSTATE_START_SAVE_MIN_VIRT
729 br.call.sptk.many b7=ia64_syscall_setup
731 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
732 ssm psr.ic | PSR_DEFAULT_BITS
734 srlz.i // guarantee that interruption collection is on
736 (p15) ssm psr.i // restore psr.i
738 mov r3=NR_syscalls - 1
739 movl r16=sys_call_table
741 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024
742 movl r2=ia64_ret_from_syscall
744 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
745 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
746 mov rp=r2 // set the real return addr
748 (p6) ld8 r20=[r20] // load address of syscall entry point
749 (p7) movl r20=sys_ni_syscall
751 add r2=TI_FLAGS+IA64_TASK_SIZE,r13
753 ld4 r2=[r2] // r2 = current_thread_info()->flags
755 tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
758 (p8) br.call.sptk.many b6=b6 // ignore this return addr
759 br.cond.sptk ia64_trace_syscall
764 /////////////////////////////////////////////////////////////////////////////////////////
765 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
768 mov r31=pr // prepare to save predicates
770 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
771 ssm psr.ic | PSR_DEFAULT_BITS
773 adds r3=8,r2 // set up second base pointer for SAVE_REST
774 srlz.i // ensure everybody knows psr.ic is back on
778 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
779 mov out0=cr.ivr // pass cr.ivr as first arg
780 add out1=16,sp // pass pointer to pt_regs as second arg
782 srlz.d // make sure we see the effect of cr.ivr
783 movl r14=ia64_leave_kernel
786 br.call.sptk.many b6=ia64_handle_irq
790 /////////////////////////////////////////////////////////////////////////////////////////
791 // 0x3400 Entry 13 (size 64 bundles) Reserved
796 /////////////////////////////////////////////////////////////////////////////////////////
797 // 0x3800 Entry 14 (size 64 bundles) Reserved
802 * There is no particular reason for this code to be here, other than that
803 * there happens to be space here that would go unused otherwise. If this
804 * fault ever gets "unreserved", simply moved the following code to a more
807 * ia64_syscall_setup() is a separate subroutine so that it can
808 * allocate stacked registers so it can safely demine any
809 * potential NaT values from the input registers.
812 * - executing on bank 0 or bank 1 register set (doesn't matter)
813 * - r1: stack pointer
814 * - r2: current task pointer
816 * - r11: original contents (saved ar.pfs to be saved)
817 * - r12: original contents (sp to be saved)
818 * - r13: original contents (tp to be saved)
819 * - r15: original contents (syscall # to be saved)
820 * - r18: saved bsp (after switching to kernel stack)
822 * - r20: saved r1 (gp)
823 * - r21: saved ar.fpsr
824 * - r22: kernel's register backing store base (krbs_base)
825 * - r23: saved ar.bspstore
826 * - r24: saved ar.rnat
827 * - r25: saved ar.unat
828 * - r26: saved ar.pfs
829 * - r27: saved ar.rsc
830 * - r28: saved cr.iip
831 * - r29: saved cr.ipsr
833 * - b0: original contents (to be saved)
835 * - executing on bank 1 registers
836 * - psr.ic enabled, interrupts restored
838 * - r3: preserved (same as on entry)
839 * - r12: points to kernel stack
840 * - r13: points to current task
841 * - p15: TRUE if interrupts need to be re-enabled
842 * - ar.fpsr: set to kernel settings
844 GLOBAL_ENTRY(ia64_syscall_setup)
846 # error This code assumes that b6 is the first field in pt_regs.
848 st8 [r1]=r19 // save b6
849 add r16=PT(CR_IPSR),r1 // initialize first base pointer
850 add r17=PT(R11),r1 // initialize second base pointer
852 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
853 st8 [r16]=r29,PT(CR_IFS)-PT(CR_IPSR) // save cr.ipsr
856 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
858 (pKStk) mov r18=r0 // make sure r18 isn't NaT
861 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
862 mov r28=b0 // save b0 (2 cyc)
866 st8 [r16]=r0,PT(AR_PFS)-PT(CR_IFS) // clear cr.ifs
867 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
871 st8 [r16]=r26,PT(AR_RNAT)-PT(AR_PFS) // save ar.pfs
872 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
875 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
876 tbit.nz p15,p0=r29,IA64_PSR_I_BIT
879 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
880 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
887 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
888 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
889 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
891 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
892 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
895 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
896 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
900 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
901 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
904 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
905 st8.spill [r17]=r15 // save r15
908 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
909 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
912 mov r13=r2 // establish `current'
913 movl r1=__gp // establish kernel global pointer
918 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
919 movl r17=FPSR_DEFAULT
921 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
924 END(ia64_syscall_setup)
927 /////////////////////////////////////////////////////////////////////////////////////////
928 // 0x3c00 Entry 15 (size 64 bundles) Reserved
933 * Squatting in this space ...
935 * This special case dispatcher for illegal operation faults allows preserved
936 * registers to be modified through a callback function (asm only) that is handed
937 * back from the fault handler in r8. Up to three arguments can be passed to the
938 * callback function by returning an aggregate with the callback as its first
939 * element, followed by the arguments.
941 ENTRY(dispatch_illegal_op_fault)
943 ssm psr.ic | PSR_DEFAULT_BITS
945 srlz.i // guarantee that interruption collection is on
947 (p15) ssm psr.i // restore psr.i
948 adds r3=8,r2 // set up second base pointer for SAVE_REST
950 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
955 br.call.sptk.many rp=ia64_illegal_op_fault
957 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
961 movl r15=ia64_leave_kernel
967 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
968 br.sptk.many ia64_leave_kernel
969 END(dispatch_illegal_op_fault)
972 /////////////////////////////////////////////////////////////////////////////////////////
973 // 0x4000 Entry 16 (size 64 bundles) Reserved
978 /////////////////////////////////////////////////////////////////////////////////////////
979 // 0x4400 Entry 17 (size 64 bundles) Reserved
986 // There is no particular reason for this code to be here, other than that
987 // there happens to be space here that would go unused otherwise. If this
988 // fault ever gets "unreserved", simply moved the following code to a more
991 alloc r14=ar.pfs,0,0,2,0
994 adds r3=8,r2 // set up second base pointer for SAVE_REST
996 ssm psr.ic | PSR_DEFAULT_BITS
998 srlz.i // guarantee that interruption collection is on
1000 (p15) ssm psr.i // restore psr.i
1001 movl r15=ia64_leave_kernel
1006 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1009 .org ia64_ivt+0x4800
1010 /////////////////////////////////////////////////////////////////////////////////////////
1011 // 0x4800 Entry 18 (size 64 bundles) Reserved
1016 * There is no particular reason for this code to be here, other than that
1017 * there happens to be space here that would go unused otherwise. If this
1018 * fault ever gets "unreserved", simply moved the following code to a more
1022 ENTRY(dispatch_unaligned_handler)
1025 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1029 ssm psr.ic | PSR_DEFAULT_BITS
1031 srlz.i // guarantee that interruption collection is on
1033 (p15) ssm psr.i // restore psr.i
1034 adds r3=8,r2 // set up second base pointer
1037 movl r14=ia64_leave_kernel
1040 br.sptk.many ia64_prepare_handle_unaligned
1041 END(dispatch_unaligned_handler)
1043 .org ia64_ivt+0x4c00
1044 /////////////////////////////////////////////////////////////////////////////////////////
1045 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1050 * There is no particular reason for this code to be here, other than that
1051 * there happens to be space here that would go unused otherwise. If this
1052 * fault ever gets "unreserved", simply moved the following code to a more
1056 ENTRY(dispatch_to_fault_handler)
1060 * r19: fault vector number (e.g., 24 for General Exception)
1061 * r31: contains saved predicates (pr)
1063 SAVE_MIN_WITH_COVER_R19
1064 alloc r14=ar.pfs,0,0,5,0
1071 ssm psr.ic | PSR_DEFAULT_BITS
1073 srlz.i // guarantee that interruption collection is on
1075 (p15) ssm psr.i // restore psr.i
1076 adds r3=8,r2 // set up second base pointer for SAVE_REST
1079 movl r14=ia64_leave_kernel
1082 br.call.sptk.many b6=ia64_fault
1083 END(dispatch_to_fault_handler)
1086 // --- End of long entries, Beginning of short entries
1089 .org ia64_ivt+0x5000
1090 /////////////////////////////////////////////////////////////////////////////////////////
1091 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1092 ENTRY(page_not_present)
1097 * The Linux page fault handler doesn't expect non-present pages to be in
1098 * the TLB. Flush the existing entry now, so we meet that expectation.
1100 mov r17=PAGE_SHIFT<<2
1106 br.sptk.many page_fault
1107 END(page_not_present)
1109 .org ia64_ivt+0x5100
1110 /////////////////////////////////////////////////////////////////////////////////////////
1111 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1112 ENTRY(key_permission)
1119 br.sptk.many page_fault
1122 .org ia64_ivt+0x5200
1123 /////////////////////////////////////////////////////////////////////////////////////////
1124 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1125 ENTRY(iaccess_rights)
1132 br.sptk.many page_fault
1135 .org ia64_ivt+0x5300
1136 /////////////////////////////////////////////////////////////////////////////////////////
1137 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1138 ENTRY(daccess_rights)
1145 br.sptk.many page_fault
1148 .org ia64_ivt+0x5400
1149 /////////////////////////////////////////////////////////////////////////////////////////
1150 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1151 ENTRY(general_exception)
1157 (p6) br.sptk.many dispatch_illegal_op_fault
1159 mov r19=24 // fault number
1160 br.sptk.many dispatch_to_fault_handler
1161 END(general_exception)
1163 .org ia64_ivt+0x5500
1164 /////////////////////////////////////////////////////////////////////////////////////////
1165 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1166 ENTRY(disabled_fp_reg)
1168 rsm psr.dfh // ensure we can access fph
1173 br.sptk.many dispatch_to_fault_handler
1174 END(disabled_fp_reg)
1176 .org ia64_ivt+0x5600
1177 /////////////////////////////////////////////////////////////////////////////////////////
1178 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1179 ENTRY(nat_consumption)
1182 END(nat_consumption)
1184 .org ia64_ivt+0x5700
1185 /////////////////////////////////////////////////////////////////////////////////////////
1186 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1187 ENTRY(speculation_vector)
1190 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1191 * this part of the architecture is not implemented in hardware on some CPUs, such
1192 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1193 * the relative target (not yet sign extended). So after sign extending it we
1194 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1195 * i.e., the slot to restart into.
1197 * cr.imm contains zero_ext(imm21)
1202 shl r18=r18,43 // put sign bit in position (43=64-21)
1206 shr r18=r18,39 // sign extend (39=43-4)
1209 add r17=r17,r18 // now add the offset
1212 dep r16=0,r16,41,2 // clear EI
1219 END(speculation_vector)
1221 .org ia64_ivt+0x5800
1222 /////////////////////////////////////////////////////////////////////////////////////////
1223 // 0x5800 Entry 28 (size 16 bundles) Reserved
1227 .org ia64_ivt+0x5900
1228 /////////////////////////////////////////////////////////////////////////////////////////
1229 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1235 .org ia64_ivt+0x5a00
1236 /////////////////////////////////////////////////////////////////////////////////////////
1237 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1238 ENTRY(unaligned_access)
1241 mov r31=pr // prepare to save predicates
1243 br.sptk.many dispatch_unaligned_handler
1244 END(unaligned_access)
1246 .org ia64_ivt+0x5b00
1247 /////////////////////////////////////////////////////////////////////////////////////////
1248 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1249 ENTRY(unsupported_data_reference)
1252 END(unsupported_data_reference)
1254 .org ia64_ivt+0x5c00
1255 /////////////////////////////////////////////////////////////////////////////////////////
1256 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1257 ENTRY(floating_point_fault)
1260 END(floating_point_fault)
1262 .org ia64_ivt+0x5d00
1263 /////////////////////////////////////////////////////////////////////////////////////////
1264 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1265 ENTRY(floating_point_trap)
1268 END(floating_point_trap)
1270 .org ia64_ivt+0x5e00
1271 /////////////////////////////////////////////////////////////////////////////////////////
1272 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1273 ENTRY(lower_privilege_trap)
1276 END(lower_privilege_trap)
1278 .org ia64_ivt+0x5f00
1279 /////////////////////////////////////////////////////////////////////////////////////////
1280 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1281 ENTRY(taken_branch_trap)
1284 END(taken_branch_trap)
1286 .org ia64_ivt+0x6000
1287 /////////////////////////////////////////////////////////////////////////////////////////
1288 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1289 ENTRY(single_step_trap)
1292 END(single_step_trap)
1294 .org ia64_ivt+0x6100
1295 /////////////////////////////////////////////////////////////////////////////////////////
1296 // 0x6100 Entry 37 (size 16 bundles) Reserved
1300 .org ia64_ivt+0x6200
1301 /////////////////////////////////////////////////////////////////////////////////////////
1302 // 0x6200 Entry 38 (size 16 bundles) Reserved
1306 .org ia64_ivt+0x6300
1307 /////////////////////////////////////////////////////////////////////////////////////////
1308 // 0x6300 Entry 39 (size 16 bundles) Reserved
1312 .org ia64_ivt+0x6400
1313 /////////////////////////////////////////////////////////////////////////////////////////
1314 // 0x6400 Entry 40 (size 16 bundles) Reserved
1318 .org ia64_ivt+0x6500
1319 /////////////////////////////////////////////////////////////////////////////////////////
1320 // 0x6500 Entry 41 (size 16 bundles) Reserved
1324 .org ia64_ivt+0x6600
1325 /////////////////////////////////////////////////////////////////////////////////////////
1326 // 0x6600 Entry 42 (size 16 bundles) Reserved
1330 .org ia64_ivt+0x6700
1331 /////////////////////////////////////////////////////////////////////////////////////////
1332 // 0x6700 Entry 43 (size 16 bundles) Reserved
1336 .org ia64_ivt+0x6800
1337 /////////////////////////////////////////////////////////////////////////////////////////
1338 // 0x6800 Entry 44 (size 16 bundles) Reserved
1342 .org ia64_ivt+0x6900
1343 /////////////////////////////////////////////////////////////////////////////////////////
1344 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1345 ENTRY(ia32_exception)
1350 .org ia64_ivt+0x6a00
1351 /////////////////////////////////////////////////////////////////////////////////////////
1352 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1353 ENTRY(ia32_intercept)
1355 #ifdef CONFIG_IA32_SUPPORT
1359 extr.u r17=r16,16,8 // get ISR.code
1361 mov r19=cr.iim // old eflag value
1364 (p6) br.cond.spnt 1f // not a system flag fault
1367 extr.u r17=r16,18,1 // get the eflags.ac bit
1370 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1372 mov pr=r31,-1 // restore predicate registers
1376 #endif // CONFIG_IA32_SUPPORT
1380 .org ia64_ivt+0x6b00
1381 /////////////////////////////////////////////////////////////////////////////////////////
1382 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1383 ENTRY(ia32_interrupt)
1385 #ifdef CONFIG_IA32_SUPPORT
1387 br.sptk.many dispatch_to_ia32_handler
1393 .org ia64_ivt+0x6c00
1394 /////////////////////////////////////////////////////////////////////////////////////////
1395 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1399 .org ia64_ivt+0x6d00
1400 /////////////////////////////////////////////////////////////////////////////////////////
1401 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1405 .org ia64_ivt+0x6e00
1406 /////////////////////////////////////////////////////////////////////////////////////////
1407 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1411 .org ia64_ivt+0x6f00
1412 /////////////////////////////////////////////////////////////////////////////////////////
1413 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1417 .org ia64_ivt+0x7000
1418 /////////////////////////////////////////////////////////////////////////////////////////
1419 // 0x7000 Entry 52 (size 16 bundles) Reserved
1423 .org ia64_ivt+0x7100
1424 /////////////////////////////////////////////////////////////////////////////////////////
1425 // 0x7100 Entry 53 (size 16 bundles) Reserved
1429 .org ia64_ivt+0x7200
1430 /////////////////////////////////////////////////////////////////////////////////////////
1431 // 0x7200 Entry 54 (size 16 bundles) Reserved
1435 .org ia64_ivt+0x7300
1436 /////////////////////////////////////////////////////////////////////////////////////////
1437 // 0x7300 Entry 55 (size 16 bundles) Reserved
1441 .org ia64_ivt+0x7400
1442 /////////////////////////////////////////////////////////////////////////////////////////
1443 // 0x7400 Entry 56 (size 16 bundles) Reserved
1447 .org ia64_ivt+0x7500
1448 /////////////////////////////////////////////////////////////////////////////////////////
1449 // 0x7500 Entry 57 (size 16 bundles) Reserved
1453 .org ia64_ivt+0x7600
1454 /////////////////////////////////////////////////////////////////////////////////////////
1455 // 0x7600 Entry 58 (size 16 bundles) Reserved
1459 .org ia64_ivt+0x7700
1460 /////////////////////////////////////////////////////////////////////////////////////////
1461 // 0x7700 Entry 59 (size 16 bundles) Reserved
1465 .org ia64_ivt+0x7800
1466 /////////////////////////////////////////////////////////////////////////////////////////
1467 // 0x7800 Entry 60 (size 16 bundles) Reserved
1471 .org ia64_ivt+0x7900
1472 /////////////////////////////////////////////////////////////////////////////////////////
1473 // 0x7900 Entry 61 (size 16 bundles) Reserved
1477 .org ia64_ivt+0x7a00
1478 /////////////////////////////////////////////////////////////////////////////////////////
1479 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1483 .org ia64_ivt+0x7b00
1484 /////////////////////////////////////////////////////////////////////////////////////////
1485 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1489 .org ia64_ivt+0x7c00
1490 /////////////////////////////////////////////////////////////////////////////////////////
1491 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1495 .org ia64_ivt+0x7d00
1496 /////////////////////////////////////////////////////////////////////////////////////////
1497 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1501 .org ia64_ivt+0x7e00
1502 /////////////////////////////////////////////////////////////////////////////////////////
1503 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1507 .org ia64_ivt+0x7f00
1508 /////////////////////////////////////////////////////////////////////////////////////////
1509 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1513 #ifdef CONFIG_IA32_SUPPORT
1516 * There is no particular reason for this code to be here, other than that
1517 * there happens to be space here that would go unused otherwise. If this
1518 * fault ever gets "unreserved", simply moved the following code to a more
1522 // IA32 interrupt entry point
1524 ENTRY(dispatch_to_ia32_handler)
1528 ssm psr.ic | PSR_DEFAULT_BITS
1530 srlz.i // guarantee that interruption collection is on
1533 adds r3=8,r2 // Base pointer for SAVE_REST
1538 shr r14=r14,16 // Get interrupt number
1540 cmp.ne p6,p0=r14,r15
1541 (p6) br.call.dpnt.many b6=non_ia32_syscall
1543 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1544 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1546 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1547 ld8 r8=[r14] // get r8
1549 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1551 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1553 ld4 r8=[r14],8 // r8 == eax (syscall number)
1554 mov r15=IA32_NR_syscalls
1556 cmp.ltu.unc p6,p7=r8,r15
1557 ld4 out1=[r14],8 // r9 == ecx
1559 ld4 out2=[r14],8 // r10 == edx
1561 ld4 out0=[r14] // r11 == ebx
1562 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
1564 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
1566 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
1567 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
1569 ld4 out4=[r14] // r15 == edi
1570 movl r16=ia32_syscall_table
1572 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
1573 ld4 r2=[r2] // r2 = current_thread_info()->flags
1576 tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
1579 movl r15=ia32_ret_from_syscall
1582 (p8) br.call.sptk.many b6=b6
1583 br.cond.sptk ia32_trace_syscall
1586 alloc r15=ar.pfs,0,0,2,0
1587 mov out0=r14 // interrupt #
1588 add out1=16,sp // pointer to pt_regs
1589 ;; // avoid WAW on CFM
1590 br.call.sptk.many rp=ia32_bad_interrupt
1591 .ret1: movl r15=ia64_leave_kernel
1595 END(dispatch_to_ia32_handler)
1597 #endif /* CONFIG_IA32_SUPPORT */