2 * arch/ia64/kernel/ivt.S
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
17 * This file defines the interruption vector table used by the CPU.
18 * It does not include one entry per possible cause of interruption.
20 * The first 20 entries of the table contain 64 bundles each while the
21 * remaining 48 entries contain only 16 bundles each.
23 * The 64 bundles are used to allow inlining the whole handler for critical
24 * interruptions like TLB misses.
26 * For each entry, the comment is as follows:
28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
29 * entry offset ----/ / / / /
30 * entry number ---------/ / / /
31 * size of the entry -------------/ / /
32 * vector name -------------------------------------/ /
33 * interruptions triggering this vector ----------------------/
35 * The table is 32KB in size and must be aligned on 32KB boundary.
36 * (The CPU ignores the 15 lower bits of the address)
38 * Table is based upon EAS2.6 (Oct 1999)
41 #include <linux/config.h>
43 #include <asm/asmmacro.h>
44 #include <asm/break.h>
46 #include <asm/kregs.h>
47 #include <asm/offsets.h>
48 #include <asm/pgtable.h>
49 #include <asm/processor.h>
50 #include <asm/ptrace.h>
51 #include <asm/system.h>
52 #include <asm/thread_info.h>
53 #include <asm/unistd.h>
54 #include <asm/errno.h>
57 # define PSR_DEFAULT_BITS psr.ac
59 # define PSR_DEFAULT_BITS 0
64 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
65 * needed for something else before enabling this...
67 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
72 #define MINSTATE_VIRT /* needed by minstate.h */
77 mov r19=n;; /* prepare to save predicates */ \
78 br.sptk.many dispatch_to_fault_handler
80 .section .text.ivt,"ax"
82 .align 32768 // align on 32KB boundary
85 /////////////////////////////////////////////////////////////////////////////////////////
86 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
90 * The VHPT vector is invoked when the TLB entry for the virtual page table
91 * is missing. This happens only as a result of a previous
92 * (the "original") TLB miss, which may either be caused by an instruction
93 * fetch or a data access (or non-access).
95 * What we do here is normal TLB miss handing for the _original_ miss, followed
96 * by inserting the TLB entry for the virtual page table page that the VHPT
97 * walker was attempting to access. The latter gets inserted as long
98 * as both L1 and L2 have valid mappings for the faulting address.
99 * The TLB entry for the original miss gets inserted only if
100 * the L3 entry indicates that the page is present.
102 * do_page_fault gets invoked in the following cases:
103 * - the faulting virtual address uses unimplemented address bits
104 * - the faulting virtual address has no L1, L2, or L3 mapping
106 mov r16=cr.ifa // get address that caused the TLB miss
107 #ifdef CONFIG_HUGETLB_PAGE
112 rsm psr.dt // use physical addressing for data
113 mov r31=pr // save the predicate registers
114 mov r19=IA64_KR(PT_BASE) // get page table base address
115 shl r21=r16,3 // shift bit 60 into sign bit
116 shr.u r17=r16,61 // get the region number into r17
119 #ifdef CONFIG_HUGETLB_PAGE
125 (p8) dep r25=r18,r25,2,6
129 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
130 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
132 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
135 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
137 .pred.rel "mutex", p6, p7
138 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
139 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
141 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
142 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
143 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
144 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
146 ld8 r17=[r17] // fetch the L1 entry (may be 0)
148 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
149 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
151 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
152 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
154 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
155 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
157 (p7) ld8 r18=[r21] // read the L3 PTE
158 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
160 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
161 mov r22=cr.iha // get the VHPT address that caused the TLB miss
162 ;; // avoid RAW on p7
163 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
164 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
166 (p10) itc.i r18 // insert the instruction TLB entry
167 (p11) itc.d r18 // insert the data TLB entry
168 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
171 #ifdef CONFIG_HUGETLB_PAGE
172 (p8) mov cr.itir=r25 // change to default page-size for VHPT
176 * Now compute and insert the TLB entry for the virtual page table. We never
177 * execute in a page table page so there is no need to set the exception deferral
180 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
186 * Tell the assemblers dependency-violation checker that the above "itc" instructions
187 * cannot possibly affect the following loads:
192 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
193 * between reading the pagetable and the "itc". If so, flush the entry we
194 * inserted and retry.
196 ld8 r25=[r21] // read L3 PTE again
197 ld8 r26=[r17] // read L2 entry again
199 cmp.ne p6,p7=r26,r20 // did L2 entry change
200 mov r27=PAGE_SHIFT<<2
202 (p6) ptc.l r22,r27 // purge PTE page translation
203 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
205 (p6) ptc.l r16,r27 // purge translation
208 mov pr=r31,-1 // restore predicate registers
213 /////////////////////////////////////////////////////////////////////////////////////////
214 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
218 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
219 * page table. If a nested TLB miss occurs, we switch into physical
220 * mode, walk the page table, and then re-execute the L3 PTE read
221 * and go on normally after that.
223 mov r16=cr.ifa // get virtual address
224 mov r29=b0 // save b0
225 mov r31=pr // save predicates
227 mov r17=cr.iha // get virtual address of L3 PTE
228 movl r30=1f // load nested fault continuation point
230 1: ld8 r18=[r17] // read L3 PTE
233 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
234 (p6) br.cond.spnt page_fault
240 * Tell the assemblers dependency-violation checker that the above "itc" instructions
241 * cannot possibly affect the following loads:
245 ld8 r19=[r17] // read L3 PTE again and see if same
246 mov r20=PAGE_SHIFT<<2 // setup page size for purge
257 /////////////////////////////////////////////////////////////////////////////////////////
258 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
262 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
263 * page table. If a nested TLB miss occurs, we switch into physical
264 * mode, walk the page table, and then re-execute the L3 PTE read
265 * and go on normally after that.
267 mov r16=cr.ifa // get virtual address
268 mov r29=b0 // save b0
269 mov r31=pr // save predicates
271 mov r17=cr.iha // get virtual address of L3 PTE
272 movl r30=1f // load nested fault continuation point
274 1: ld8 r18=[r17] // read L3 PTE
277 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
278 (p6) br.cond.spnt page_fault
284 * Tell the assemblers dependency-violation checker that the above "itc" instructions
285 * cannot possibly affect the following loads:
289 ld8 r19=[r17] // read L3 PTE again and see if same
290 mov r20=PAGE_SHIFT<<2 // setup page size for purge
301 /////////////////////////////////////////////////////////////////////////////////////////
302 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
305 mov r16=cr.ifa // get address that caused the TLB miss
308 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
311 #ifdef CONFIG_DISABLE_VHPT
312 shr.u r22=r16,61 // get the region number into r21
314 cmp.gt p8,p0=6,r22 // user mode
319 (p8) mov r29=b0 // save b0
320 (p8) br.cond.dptk .itlb_fault
322 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
323 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
324 shr.u r18=r16,57 // move address bit 61 to bit 4
326 andcm r18=0x10,r18 // bit 4=~address-bit(61)
327 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
328 or r19=r17,r19 // insert PTE control bits into r19
330 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
331 (p8) br.cond.spnt page_fault
333 itc.i r19 // insert the TLB entry
339 /////////////////////////////////////////////////////////////////////////////////////////
340 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
343 mov r16=cr.ifa // get address that caused the TLB miss
346 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
350 #ifdef CONFIG_DISABLE_VHPT
351 shr.u r22=r16,61 // get the region number into r21
353 cmp.gt p8,p0=6,r22 // access to region 0-5
358 (p8) mov r29=b0 // save b0
359 (p8) br.cond.dptk dtlb_fault
361 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
362 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
363 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
364 shr.u r18=r16,57 // move address bit 61 to bit 4
365 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
366 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
368 andcm r18=0x10,r18 // bit 4=~address-bit(61)
370 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
371 (p8) br.cond.spnt page_fault
373 dep r21=-1,r21,IA64_PSR_ED_BIT,1
374 or r19=r19,r17 // insert PTE control bits into r19
376 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
379 (p7) itc.d r19 // insert the TLB entry
385 /////////////////////////////////////////////////////////////////////////////////////////
386 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
387 ENTRY(nested_dtlb_miss)
389 * In the absence of kernel bugs, we get here when the virtually mapped linear
390 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
391 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
392 * table is missing, a nested TLB miss fault is triggered and control is
393 * transferred to this point. When this happens, we lookup the pte for the
394 * faulting address by walking the page table in physical mode and return to the
395 * continuation point passed in register r30 (or call page_fault if the address is
398 * Input: r16: faulting address
400 * r30: continuation address
403 * Output: r17: physical address of L3 PTE of faulting address
405 * r30: continuation address
408 * Clobbered: b0, r18, r19, r21, psr.dt (cleared)
410 rsm psr.dt // switch to using physical data addressing
411 mov r19=IA64_KR(PT_BASE) // get the page table base address
412 shl r21=r16,3 // shift bit 60 into sign bit
414 shr.u r17=r16,61 // get the region number into r17
416 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
417 shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address
419 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
422 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
424 .pred.rel "mutex", p6, p7
425 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
426 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
428 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
429 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
430 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
431 shr.u r18=r16,PMD_SHIFT // shift L2 index into position
433 ld8 r17=[r17] // fetch the L1 entry (may be 0)
435 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
436 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
438 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
439 shr.u r19=r16,PAGE_SHIFT // shift L3 index into position
441 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
442 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
443 (p6) br.cond.spnt page_fault
445 br.sptk.many b0 // return to continuation point
446 END(nested_dtlb_miss)
449 /////////////////////////////////////////////////////////////////////////////////////////
450 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
456 //-----------------------------------------------------------------------------------
457 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
464 alloc r15=ar.pfs,0,0,3,0
467 adds r3=8,r2 // set up second base pointer
469 ssm psr.ic | PSR_DEFAULT_BITS
471 srlz.i // guarantee that interruption collectin is on
473 (p15) ssm psr.i // restore psr.i
474 movl r14=ia64_leave_kernel
479 adds out2=16,r12 // out2 = pointer to pt_regs
480 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
484 /////////////////////////////////////////////////////////////////////////////////////////
485 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
492 /////////////////////////////////////////////////////////////////////////////////////////
493 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
497 * What we do here is to simply turn on the dirty bit in the PTE. We need to
498 * update both the page-table and the TLB entry. To efficiently access the PTE,
499 * we address it through the virtual page table. Most likely, the TLB entry for
500 * the relevant virtual page table page is still present in the TLB so we can
501 * normally do this without additional TLB misses. In case the necessary virtual
502 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
503 * up the physical address of the L3 PTE and then continue at label 1 below.
505 mov r16=cr.ifa // get the address that caused the fault
506 movl r30=1f // load continuation point in case of nested fault
508 thash r17=r16 // compute virtual address of L3 PTE
509 mov r29=b0 // save b0 in case of nested fault
510 mov r31=pr // save pr
512 mov r28=ar.ccv // save ar.ccv
515 ;; // avoid RAW on r18
516 mov ar.ccv=r18 // set compare value for cmpxchg
517 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
519 cmpxchg8.acq r26=[r17],r25,ar.ccv
520 mov r24=PAGE_SHIFT<<2
524 (p6) itc.d r25 // install updated PTE
527 * Tell the assemblers dependency-violation checker that the above "itc" instructions
528 * cannot possibly affect the following loads:
532 ld8 r18=[r17] // read PTE again
534 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
537 mov b0=r29 // restore b0
542 ;; // avoid RAW on r18
543 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
544 mov b0=r29 // restore b0
546 st8 [r17]=r18 // store back updated PTE
547 itc.d r18 // install updated PTE
549 mov pr=r31,-1 // restore pr
554 /////////////////////////////////////////////////////////////////////////////////////////
555 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
558 // Like Entry 8, except for instruction access
559 mov r16=cr.ifa // get the address that caused the fault
560 movl r30=1f // load continuation point in case of nested fault
561 mov r31=pr // save predicates
562 #ifdef CONFIG_ITANIUM
564 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
569 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
571 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
572 #endif /* CONFIG_ITANIUM */
574 thash r17=r16 // compute virtual address of L3 PTE
575 mov r29=b0 // save b0 in case of nested fault)
577 mov r28=ar.ccv // save ar.ccv
581 mov ar.ccv=r18 // set compare value for cmpxchg
582 or r25=_PAGE_A,r18 // set the accessed bit
584 cmpxchg8.acq r26=[r17],r25,ar.ccv
585 mov r24=PAGE_SHIFT<<2
589 (p6) itc.i r25 // install updated PTE
592 * Tell the assemblers dependency-violation checker that the above "itc" instructions
593 * cannot possibly affect the following loads:
597 ld8 r18=[r17] // read PTE again
599 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
602 mov b0=r29 // restore b0
604 #else /* !CONFIG_SMP */
608 or r18=_PAGE_A,r18 // set the accessed bit
609 mov b0=r29 // restore b0
611 st8 [r17]=r18 // store back updated PTE
612 itc.i r18 // install updated PTE
613 #endif /* !CONFIG_SMP */
619 /////////////////////////////////////////////////////////////////////////////////////////
620 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
623 // Like Entry 8, except for data access
624 mov r16=cr.ifa // get the address that caused the fault
625 movl r30=1f // load continuation point in case of nested fault
627 thash r17=r16 // compute virtual address of L3 PTE
629 mov r29=b0 // save b0 in case of nested fault)
631 mov r28=ar.ccv // save ar.ccv
634 ;; // avoid RAW on r18
635 mov ar.ccv=r18 // set compare value for cmpxchg
636 or r25=_PAGE_A,r18 // set the dirty bit
638 cmpxchg8.acq r26=[r17],r25,ar.ccv
639 mov r24=PAGE_SHIFT<<2
643 (p6) itc.d r25 // install updated PTE
645 * Tell the assemblers dependency-violation checker that the above "itc" instructions
646 * cannot possibly affect the following loads:
650 ld8 r18=[r17] // read PTE again
652 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
659 ;; // avoid RAW on r18
660 or r18=_PAGE_A,r18 // set the accessed bit
662 st8 [r17]=r18 // store back updated PTE
663 itc.d r18 // install updated PTE
665 mov b0=r29 // restore b0
671 /////////////////////////////////////////////////////////////////////////////////////////
672 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
675 * The streamlined system call entry/exit paths only save/restore the initial part
676 * of pt_regs. This implies that the callers of system-calls must adhere to the
677 * normal procedure calling conventions.
679 * Registers to be saved & restored:
680 * CR registers: cr.ipsr, cr.iip, cr.ifs
681 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
682 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
683 * Registers to be restored only:
684 * r8-r11: output value from the system call.
686 * During system call exit, scratch registers (including r15) are modified/cleared
687 * to prevent leaking bits from kernel to user level.
690 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat.
692 mov r18=__IA64_BREAK_SYSCALL
700 mov r31=pr // prepare to save predicates
703 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
704 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so)
705 (p7) br.cond.spnt non_syscall
707 ld1 r17=[r16] // load current->thread.on_ustack flag
708 st1 [r16]=r0 // clear current->thread.on_ustack flag
709 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT
713 /* adjust return address so we skip over the break instruction: */
715 extr.u r8=r29,41,2 // extract ei field from cr.ipsr
717 cmp.eq p6,p7=2,r8 // isr.ei==2?
718 mov r2=r1 // setup r2 for ia64_syscall_setup
720 (p6) mov r8=0 // clear ei to 0
721 (p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
722 (p7) adds r8=1,r8 // increment ei to next slot
724 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
725 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
728 // switch from user to kernel RBS:
729 MINSTATE_START_SAVE_MIN_VIRT
730 br.call.sptk.many b7=ia64_syscall_setup
732 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
733 ssm psr.ic | PSR_DEFAULT_BITS
735 srlz.i // guarantee that interruption collection is on
736 mov r3=NR_syscalls - 1
738 (p15) ssm psr.i // restore psr.i
739 // p10==true means out registers are more than 8 or r15's Nat is true
740 (p10) br.cond.spnt.many ia64_ret_from_syscall
742 movl r16=sys_call_table
744 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024
745 movl r2=ia64_ret_from_syscall
747 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
748 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
749 mov rp=r2 // set the real return addr
751 (p6) ld8 r20=[r20] // load address of syscall entry point
752 (p7) movl r20=sys_ni_syscall
754 add r2=TI_FLAGS+IA64_TASK_SIZE,r13
756 ld4 r2=[r2] // r2 = current_thread_info()->flags
758 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
763 (p8) br.call.sptk.many b6=b6 // ignore this return addr
764 br.cond.sptk ia64_trace_syscall
769 /////////////////////////////////////////////////////////////////////////////////////////
770 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
773 mov r31=pr // prepare to save predicates
775 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
776 ssm psr.ic | PSR_DEFAULT_BITS
778 adds r3=8,r2 // set up second base pointer for SAVE_REST
779 srlz.i // ensure everybody knows psr.ic is back on
783 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
784 mov out0=cr.ivr // pass cr.ivr as first arg
785 add out1=16,sp // pass pointer to pt_regs as second arg
787 srlz.d // make sure we see the effect of cr.ivr
788 movl r14=ia64_leave_kernel
791 br.call.sptk.many b6=ia64_handle_irq
795 /////////////////////////////////////////////////////////////////////////////////////////
796 // 0x3400 Entry 13 (size 64 bundles) Reserved
801 /////////////////////////////////////////////////////////////////////////////////////////
802 // 0x3800 Entry 14 (size 64 bundles) Reserved
807 * There is no particular reason for this code to be here, other than that
808 * there happens to be space here that would go unused otherwise. If this
809 * fault ever gets "unreserved", simply moved the following code to a more
812 * ia64_syscall_setup() is a separate subroutine so that it can
813 * allocate stacked registers so it can safely demine any
814 * potential NaT values from the input registers.
817 * - executing on bank 0 or bank 1 register set (doesn't matter)
818 * - r1: stack pointer
819 * - r2: current task pointer
821 * - r11: original contents (saved ar.pfs to be saved)
822 * - r12: original contents (sp to be saved)
823 * - r13: original contents (tp to be saved)
824 * - r15: original contents (syscall # to be saved)
825 * - r18: saved bsp (after switching to kernel stack)
827 * - r20: saved r1 (gp)
828 * - r21: saved ar.fpsr
829 * - r22: kernel's register backing store base (krbs_base)
830 * - r23: saved ar.bspstore
831 * - r24: saved ar.rnat
832 * - r25: saved ar.unat
833 * - r26: saved ar.pfs
834 * - r27: saved ar.rsc
835 * - r28: saved cr.iip
836 * - r29: saved cr.ipsr
838 * - b0: original contents (to be saved)
840 * - executing on bank 1 registers
841 * - psr.ic enabled, interrupts restored
842 * - p10: TRUE if syscall is invoked with more than 8 out
843 * registers or r15's Nat is true
845 * - r3: preserved (same as on entry)
846 * - r8: -EINVAL if p10 is true
847 * - r12: points to kernel stack
848 * - r13: points to current task
849 * - p15: TRUE if interrupts need to be re-enabled
850 * - ar.fpsr: set to kernel settings
852 GLOBAL_ENTRY(ia64_syscall_setup)
854 # error This code assumes that b6 is the first field in pt_regs.
856 st8 [r1]=r19 // save b6
857 add r16=PT(CR_IPSR),r1 // initialize first base pointer
858 add r17=PT(R11),r1 // initialize second base pointer
860 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
861 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
864 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
866 (pKStk) mov r18=r0 // make sure r18 isn't NaT
869 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
870 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
871 mov r28=b0 // save b0 (2 cyc)
874 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
875 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
879 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
880 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
881 and r8=0x7f,r19 // A // get sof of ar.pfs
883 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
884 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
888 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
892 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
893 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
897 tnat.nz p12,p0=in4 // [I0]
900 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
901 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
902 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
904 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
905 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
906 tnat.nz p13,p0=in5 // [I0]
908 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
909 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
913 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
914 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
917 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
919 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
921 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
922 (p9) tnat.nz p10,p0=r15
923 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
925 st8.spill [r17]=r15 // save r15
929 mov r13=r2 // establish `current'
930 movl r1=__gp // establish kernel global pointer
936 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
937 movl r17=FPSR_DEFAULT
939 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
942 END(ia64_syscall_setup)
945 /////////////////////////////////////////////////////////////////////////////////////////
946 // 0x3c00 Entry 15 (size 64 bundles) Reserved
951 * Squatting in this space ...
953 * This special case dispatcher for illegal operation faults allows preserved
954 * registers to be modified through a callback function (asm only) that is handed
955 * back from the fault handler in r8. Up to three arguments can be passed to the
956 * callback function by returning an aggregate with the callback as its first
957 * element, followed by the arguments.
959 ENTRY(dispatch_illegal_op_fault)
961 ssm psr.ic | PSR_DEFAULT_BITS
963 srlz.i // guarantee that interruption collection is on
965 (p15) ssm psr.i // restore psr.i
966 adds r3=8,r2 // set up second base pointer for SAVE_REST
968 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
973 br.call.sptk.many rp=ia64_illegal_op_fault
975 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
979 movl r15=ia64_leave_kernel
985 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
986 br.sptk.many ia64_leave_kernel
987 END(dispatch_illegal_op_fault)
990 /////////////////////////////////////////////////////////////////////////////////////////
991 // 0x4000 Entry 16 (size 64 bundles) Reserved
996 /////////////////////////////////////////////////////////////////////////////////////////
997 // 0x4400 Entry 17 (size 64 bundles) Reserved
1004 // There is no particular reason for this code to be here, other than that
1005 // there happens to be space here that would go unused otherwise. If this
1006 // fault ever gets "unreserved", simply moved the following code to a more
1009 alloc r14=ar.pfs,0,0,2,0
1012 adds r3=8,r2 // set up second base pointer for SAVE_REST
1014 ssm psr.ic | PSR_DEFAULT_BITS
1016 srlz.i // guarantee that interruption collection is on
1018 (p15) ssm psr.i // restore psr.i
1019 movl r15=ia64_leave_kernel
1024 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1027 .org ia64_ivt+0x4800
1028 /////////////////////////////////////////////////////////////////////////////////////////
1029 // 0x4800 Entry 18 (size 64 bundles) Reserved
1034 * There is no particular reason for this code to be here, other than that
1035 * there happens to be space here that would go unused otherwise. If this
1036 * fault ever gets "unreserved", simply moved the following code to a more
1040 ENTRY(dispatch_unaligned_handler)
1043 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1047 ssm psr.ic | PSR_DEFAULT_BITS
1049 srlz.i // guarantee that interruption collection is on
1051 (p15) ssm psr.i // restore psr.i
1052 adds r3=8,r2 // set up second base pointer
1055 movl r14=ia64_leave_kernel
1058 br.sptk.many ia64_prepare_handle_unaligned
1059 END(dispatch_unaligned_handler)
1061 .org ia64_ivt+0x4c00
1062 /////////////////////////////////////////////////////////////////////////////////////////
1063 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1068 * There is no particular reason for this code to be here, other than that
1069 * there happens to be space here that would go unused otherwise. If this
1070 * fault ever gets "unreserved", simply moved the following code to a more
1074 ENTRY(dispatch_to_fault_handler)
1078 * r19: fault vector number (e.g., 24 for General Exception)
1079 * r31: contains saved predicates (pr)
1081 SAVE_MIN_WITH_COVER_R19
1082 alloc r14=ar.pfs,0,0,5,0
1089 ssm psr.ic | PSR_DEFAULT_BITS
1091 srlz.i // guarantee that interruption collection is on
1093 (p15) ssm psr.i // restore psr.i
1094 adds r3=8,r2 // set up second base pointer for SAVE_REST
1097 movl r14=ia64_leave_kernel
1100 br.call.sptk.many b6=ia64_fault
1101 END(dispatch_to_fault_handler)
1104 // --- End of long entries, Beginning of short entries
1107 .org ia64_ivt+0x5000
1108 /////////////////////////////////////////////////////////////////////////////////////////
1109 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1110 ENTRY(page_not_present)
1115 * The Linux page fault handler doesn't expect non-present pages to be in
1116 * the TLB. Flush the existing entry now, so we meet that expectation.
1118 mov r17=PAGE_SHIFT<<2
1124 br.sptk.many page_fault
1125 END(page_not_present)
1127 .org ia64_ivt+0x5100
1128 /////////////////////////////////////////////////////////////////////////////////////////
1129 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1130 ENTRY(key_permission)
1137 br.sptk.many page_fault
1140 .org ia64_ivt+0x5200
1141 /////////////////////////////////////////////////////////////////////////////////////////
1142 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1143 ENTRY(iaccess_rights)
1150 br.sptk.many page_fault
1153 .org ia64_ivt+0x5300
1154 /////////////////////////////////////////////////////////////////////////////////////////
1155 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1156 ENTRY(daccess_rights)
1163 br.sptk.many page_fault
1166 .org ia64_ivt+0x5400
1167 /////////////////////////////////////////////////////////////////////////////////////////
1168 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1169 ENTRY(general_exception)
1175 (p6) br.sptk.many dispatch_illegal_op_fault
1177 mov r19=24 // fault number
1178 br.sptk.many dispatch_to_fault_handler
1179 END(general_exception)
1181 .org ia64_ivt+0x5500
1182 /////////////////////////////////////////////////////////////////////////////////////////
1183 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1184 ENTRY(disabled_fp_reg)
1186 rsm psr.dfh // ensure we can access fph
1191 br.sptk.many dispatch_to_fault_handler
1192 END(disabled_fp_reg)
1194 .org ia64_ivt+0x5600
1195 /////////////////////////////////////////////////////////////////////////////////////////
1196 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1197 ENTRY(nat_consumption)
1200 END(nat_consumption)
1202 .org ia64_ivt+0x5700
1203 /////////////////////////////////////////////////////////////////////////////////////////
1204 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1205 ENTRY(speculation_vector)
1208 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1209 * this part of the architecture is not implemented in hardware on some CPUs, such
1210 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1211 * the relative target (not yet sign extended). So after sign extending it we
1212 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1213 * i.e., the slot to restart into.
1215 * cr.imm contains zero_ext(imm21)
1220 shl r18=r18,43 // put sign bit in position (43=64-21)
1224 shr r18=r18,39 // sign extend (39=43-4)
1227 add r17=r17,r18 // now add the offset
1230 dep r16=0,r16,41,2 // clear EI
1237 END(speculation_vector)
1239 .org ia64_ivt+0x5800
1240 /////////////////////////////////////////////////////////////////////////////////////////
1241 // 0x5800 Entry 28 (size 16 bundles) Reserved
1245 .org ia64_ivt+0x5900
1246 /////////////////////////////////////////////////////////////////////////////////////////
1247 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1253 .org ia64_ivt+0x5a00
1254 /////////////////////////////////////////////////////////////////////////////////////////
1255 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1256 ENTRY(unaligned_access)
1259 mov r31=pr // prepare to save predicates
1261 br.sptk.many dispatch_unaligned_handler
1262 END(unaligned_access)
1264 .org ia64_ivt+0x5b00
1265 /////////////////////////////////////////////////////////////////////////////////////////
1266 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1267 ENTRY(unsupported_data_reference)
1270 END(unsupported_data_reference)
1272 .org ia64_ivt+0x5c00
1273 /////////////////////////////////////////////////////////////////////////////////////////
1274 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1275 ENTRY(floating_point_fault)
1278 END(floating_point_fault)
1280 .org ia64_ivt+0x5d00
1281 /////////////////////////////////////////////////////////////////////////////////////////
1282 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1283 ENTRY(floating_point_trap)
1286 END(floating_point_trap)
1288 .org ia64_ivt+0x5e00
1289 /////////////////////////////////////////////////////////////////////////////////////////
1290 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1291 ENTRY(lower_privilege_trap)
1294 END(lower_privilege_trap)
1296 .org ia64_ivt+0x5f00
1297 /////////////////////////////////////////////////////////////////////////////////////////
1298 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1299 ENTRY(taken_branch_trap)
1302 END(taken_branch_trap)
1304 .org ia64_ivt+0x6000
1305 /////////////////////////////////////////////////////////////////////////////////////////
1306 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1307 ENTRY(single_step_trap)
1310 END(single_step_trap)
1312 .org ia64_ivt+0x6100
1313 /////////////////////////////////////////////////////////////////////////////////////////
1314 // 0x6100 Entry 37 (size 16 bundles) Reserved
1318 .org ia64_ivt+0x6200
1319 /////////////////////////////////////////////////////////////////////////////////////////
1320 // 0x6200 Entry 38 (size 16 bundles) Reserved
1324 .org ia64_ivt+0x6300
1325 /////////////////////////////////////////////////////////////////////////////////////////
1326 // 0x6300 Entry 39 (size 16 bundles) Reserved
1330 .org ia64_ivt+0x6400
1331 /////////////////////////////////////////////////////////////////////////////////////////
1332 // 0x6400 Entry 40 (size 16 bundles) Reserved
1336 .org ia64_ivt+0x6500
1337 /////////////////////////////////////////////////////////////////////////////////////////
1338 // 0x6500 Entry 41 (size 16 bundles) Reserved
1342 .org ia64_ivt+0x6600
1343 /////////////////////////////////////////////////////////////////////////////////////////
1344 // 0x6600 Entry 42 (size 16 bundles) Reserved
1348 .org ia64_ivt+0x6700
1349 /////////////////////////////////////////////////////////////////////////////////////////
1350 // 0x6700 Entry 43 (size 16 bundles) Reserved
1354 .org ia64_ivt+0x6800
1355 /////////////////////////////////////////////////////////////////////////////////////////
1356 // 0x6800 Entry 44 (size 16 bundles) Reserved
1360 .org ia64_ivt+0x6900
1361 /////////////////////////////////////////////////////////////////////////////////////////
1362 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1363 ENTRY(ia32_exception)
1368 .org ia64_ivt+0x6a00
1369 /////////////////////////////////////////////////////////////////////////////////////////
1370 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1371 ENTRY(ia32_intercept)
1373 #ifdef CONFIG_IA32_SUPPORT
1377 extr.u r17=r16,16,8 // get ISR.code
1379 mov r19=cr.iim // old eflag value
1382 (p6) br.cond.spnt 1f // not a system flag fault
1385 extr.u r17=r16,18,1 // get the eflags.ac bit
1388 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1390 mov pr=r31,-1 // restore predicate registers
1394 #endif // CONFIG_IA32_SUPPORT
1398 .org ia64_ivt+0x6b00
1399 /////////////////////////////////////////////////////////////////////////////////////////
1400 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1401 ENTRY(ia32_interrupt)
1403 #ifdef CONFIG_IA32_SUPPORT
1405 br.sptk.many dispatch_to_ia32_handler
1411 .org ia64_ivt+0x6c00
1412 /////////////////////////////////////////////////////////////////////////////////////////
1413 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1417 .org ia64_ivt+0x6d00
1418 /////////////////////////////////////////////////////////////////////////////////////////
1419 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1423 .org ia64_ivt+0x6e00
1424 /////////////////////////////////////////////////////////////////////////////////////////
1425 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1429 .org ia64_ivt+0x6f00
1430 /////////////////////////////////////////////////////////////////////////////////////////
1431 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1435 .org ia64_ivt+0x7000
1436 /////////////////////////////////////////////////////////////////////////////////////////
1437 // 0x7000 Entry 52 (size 16 bundles) Reserved
1441 .org ia64_ivt+0x7100
1442 /////////////////////////////////////////////////////////////////////////////////////////
1443 // 0x7100 Entry 53 (size 16 bundles) Reserved
1447 .org ia64_ivt+0x7200
1448 /////////////////////////////////////////////////////////////////////////////////////////
1449 // 0x7200 Entry 54 (size 16 bundles) Reserved
1453 .org ia64_ivt+0x7300
1454 /////////////////////////////////////////////////////////////////////////////////////////
1455 // 0x7300 Entry 55 (size 16 bundles) Reserved
1459 .org ia64_ivt+0x7400
1460 /////////////////////////////////////////////////////////////////////////////////////////
1461 // 0x7400 Entry 56 (size 16 bundles) Reserved
1465 .org ia64_ivt+0x7500
1466 /////////////////////////////////////////////////////////////////////////////////////////
1467 // 0x7500 Entry 57 (size 16 bundles) Reserved
1471 .org ia64_ivt+0x7600
1472 /////////////////////////////////////////////////////////////////////////////////////////
1473 // 0x7600 Entry 58 (size 16 bundles) Reserved
1477 .org ia64_ivt+0x7700
1478 /////////////////////////////////////////////////////////////////////////////////////////
1479 // 0x7700 Entry 59 (size 16 bundles) Reserved
1483 .org ia64_ivt+0x7800
1484 /////////////////////////////////////////////////////////////////////////////////////////
1485 // 0x7800 Entry 60 (size 16 bundles) Reserved
1489 .org ia64_ivt+0x7900
1490 /////////////////////////////////////////////////////////////////////////////////////////
1491 // 0x7900 Entry 61 (size 16 bundles) Reserved
1495 .org ia64_ivt+0x7a00
1496 /////////////////////////////////////////////////////////////////////////////////////////
1497 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1501 .org ia64_ivt+0x7b00
1502 /////////////////////////////////////////////////////////////////////////////////////////
1503 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1507 .org ia64_ivt+0x7c00
1508 /////////////////////////////////////////////////////////////////////////////////////////
1509 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1513 .org ia64_ivt+0x7d00
1514 /////////////////////////////////////////////////////////////////////////////////////////
1515 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1519 .org ia64_ivt+0x7e00
1520 /////////////////////////////////////////////////////////////////////////////////////////
1521 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1525 .org ia64_ivt+0x7f00
1526 /////////////////////////////////////////////////////////////////////////////////////////
1527 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1531 #ifdef CONFIG_IA32_SUPPORT
1534 * There is no particular reason for this code to be here, other than that
1535 * there happens to be space here that would go unused otherwise. If this
1536 * fault ever gets "unreserved", simply moved the following code to a more
1540 // IA32 interrupt entry point
1542 ENTRY(dispatch_to_ia32_handler)
1546 ssm psr.ic | PSR_DEFAULT_BITS
1548 srlz.i // guarantee that interruption collection is on
1551 adds r3=8,r2 // Base pointer for SAVE_REST
1556 shr r14=r14,16 // Get interrupt number
1558 cmp.ne p6,p0=r14,r15
1559 (p6) br.call.dpnt.many b6=non_ia32_syscall
1561 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1562 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1564 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1565 ld8 r8=[r14] // get r8
1567 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1569 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1571 ld4 r8=[r14],8 // r8 == eax (syscall number)
1572 mov r15=IA32_NR_syscalls
1574 cmp.ltu.unc p6,p7=r8,r15
1575 ld4 out1=[r14],8 // r9 == ecx
1577 ld4 out2=[r14],8 // r10 == edx
1579 ld4 out0=[r14] // r11 == ebx
1580 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
1582 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
1584 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
1585 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
1587 ld4 out4=[r14] // r15 == edi
1588 movl r16=ia32_syscall_table
1590 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
1591 ld4 r2=[r2] // r2 = current_thread_info()->flags
1594 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
1597 movl r15=ia32_ret_from_syscall
1601 (p8) br.call.sptk.many b6=b6
1602 br.cond.sptk ia32_trace_syscall
1605 alloc r15=ar.pfs,0,0,2,0
1606 mov out0=r14 // interrupt #
1607 add out1=16,sp // pointer to pt_regs
1608 ;; // avoid WAW on CFM
1609 br.call.sptk.many rp=ia32_bad_interrupt
1610 .ret1: movl r15=ia64_leave_kernel
1614 END(dispatch_to_ia32_handler)
1616 #endif /* CONFIG_IA32_SUPPORT */