2 * arch/ia64/kernel/ivt.S
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
17 * This file defines the interruption vector table used by the CPU.
18 * It does not include one entry per possible cause of interruption.
20 * The first 20 entries of the table contain 64 bundles each while the
21 * remaining 48 entries contain only 16 bundles each.
23 * The 64 bundles are used to allow inlining the whole handler for critical
24 * interruptions like TLB misses.
26 * For each entry, the comment is as follows:
28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
29 * entry offset ----/ / / / /
30 * entry number ---------/ / / /
31 * size of the entry -------------/ / /
32 * vector name -------------------------------------/ /
33 * interruptions triggering this vector ----------------------/
35 * The table is 32KB in size and must be aligned on 32KB boundary.
36 * (The CPU ignores the 15 lower bits of the address)
38 * Table is based upon EAS2.6 (Oct 1999)
41 #include <linux/config.h>
43 #include <asm/asmmacro.h>
44 #include <asm/break.h>
46 #include <asm/kregs.h>
47 #include <asm/offsets.h>
48 #include <asm/pgtable.h>
49 #include <asm/processor.h>
50 #include <asm/ptrace.h>
51 #include <asm/system.h>
52 #include <asm/thread_info.h>
53 #include <asm/unistd.h>
56 # define PSR_DEFAULT_BITS psr.ac
58 # define PSR_DEFAULT_BITS 0
63 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
64 * needed for something else before enabling this...
66 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
71 #define MINSTATE_VIRT /* needed by minstate.h */
76 mov r19=n;; /* prepare to save predicates */ \
77 br.sptk.many dispatch_to_fault_handler
79 .section .text.ivt,"ax"
81 .align 32768 // align on 32KB boundary
84 /////////////////////////////////////////////////////////////////////////////////////////
85 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
89 * The VHPT vector is invoked when the TLB entry for the virtual page table
90 * is missing. This happens only as a result of a previous
91 * (the "original") TLB miss, which may either be caused by an instruction
92 * fetch or a data access (or non-access).
94 * What we do here is normal TLB miss handing for the _original_ miss, followed
95 * by inserting the TLB entry for the virtual page table page that the VHPT
96 * walker was attempting to access. The latter gets inserted as long
97 * as both L1 and L2 have valid mappings for the faulting address.
98 * The TLB entry for the original miss gets inserted only if
99 * the L3 entry indicates that the page is present.
101 * do_page_fault gets invoked in the following cases:
102 * - the faulting virtual address uses unimplemented address bits
103 * - the faulting virtual address has no L1, L2, or L3 mapping
105 mov r16=cr.ifa // get address that caused the TLB miss
106 #ifdef CONFIG_HUGETLB_PAGE
111 rsm psr.dt // use physical addressing for data
112 mov r31=pr // save the predicate registers
113 mov r19=IA64_KR(PT_BASE) // get page table base address
114 shl r21=r16,3 // shift bit 60 into sign bit
115 shr.u r17=r16,61 // get the region number into r17
118 #ifdef CONFIG_HUGETLB_PAGE
124 (p8) dep r25=r18,r25,2,6
128 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
129 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
131 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
134 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
136 .pred.rel "mutex", p6, p7
137 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
138 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
140 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
141 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
142 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
143 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
145 ld8 r17=[r17] // fetch the L1 entry (may be 0)
147 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
148 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
150 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
151 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
153 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
154 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
156 (p7) ld8 r18=[r21] // read the L3 PTE
157 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
159 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
160 mov r22=cr.iha // get the VHPT address that caused the TLB miss
161 ;; // avoid RAW on p7
162 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
163 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
165 (p10) itc.i r18 // insert the instruction TLB entry
166 (p11) itc.d r18 // insert the data TLB entry
167 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
170 #ifdef CONFIG_HUGETLB_PAGE
171 (p8) mov cr.itir=r25 // change to default page-size for VHPT
175 * Now compute and insert the TLB entry for the virtual page table. We never
176 * execute in a page table page so there is no need to set the exception deferral
179 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
185 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
186 * between reading the pagetable and the "itc". If so, flush the entry we
187 * inserted and retry.
189 ld8 r25=[r21] // read L3 PTE again
190 ld8 r26=[r17] // read L2 entry again
192 cmp.ne p6,p7=r26,r20 // did L2 entry change
193 mov r27=PAGE_SHIFT<<2
195 (p6) ptc.l r22,r27 // purge PTE page translation
196 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
198 (p6) ptc.l r16,r27 // purge translation
201 mov pr=r31,-1 // restore predicate registers
206 /////////////////////////////////////////////////////////////////////////////////////////
207 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
211 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
212 * page table. If a nested TLB miss occurs, we switch into physical
213 * mode, walk the page table, and then re-execute the L3 PTE read
214 * and go on normally after that.
216 mov r16=cr.ifa // get virtual address
217 mov r29=b0 // save b0
218 mov r31=pr // save predicates
220 mov r17=cr.iha // get virtual address of L3 PTE
221 movl r30=1f // load nested fault continuation point
223 1: ld8 r18=[r17] // read L3 PTE
226 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
227 (p6) br.cond.spnt page_fault
232 ld8 r19=[r17] // read L3 PTE again and see if same
233 mov r20=PAGE_SHIFT<<2 // setup page size for purge
244 /////////////////////////////////////////////////////////////////////////////////////////
245 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
249 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
250 * page table. If a nested TLB miss occurs, we switch into physical
251 * mode, walk the page table, and then re-execute the L3 PTE read
252 * and go on normally after that.
254 mov r16=cr.ifa // get virtual address
255 mov r29=b0 // save b0
256 mov r31=pr // save predicates
258 mov r17=cr.iha // get virtual address of L3 PTE
259 movl r30=1f // load nested fault continuation point
261 1: ld8 r18=[r17] // read L3 PTE
264 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
265 (p6) br.cond.spnt page_fault
270 ld8 r19=[r17] // read L3 PTE again and see if same
271 mov r20=PAGE_SHIFT<<2 // setup page size for purge
282 /////////////////////////////////////////////////////////////////////////////////////////
283 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
286 mov r16=cr.ifa // get address that caused the TLB miss
289 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
292 #ifdef CONFIG_DISABLE_VHPT
293 shr.u r22=r16,61 // get the region number into r21
295 cmp.gt p8,p0=6,r22 // user mode
300 (p8) mov r29=b0 // save b0
301 (p8) br.cond.dptk .itlb_fault
303 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
304 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
305 shr.u r18=r16,57 // move address bit 61 to bit 4
307 andcm r18=0x10,r18 // bit 4=~address-bit(61)
308 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
309 or r19=r17,r19 // insert PTE control bits into r19
311 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
312 (p8) br.cond.spnt page_fault
314 itc.i r19 // insert the TLB entry
320 /////////////////////////////////////////////////////////////////////////////////////////
321 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
324 mov r16=cr.ifa // get address that caused the TLB miss
327 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
331 #ifdef CONFIG_DISABLE_VHPT
332 shr.u r22=r16,61 // get the region number into r21
334 cmp.gt p8,p0=6,r22 // access to region 0-5
339 (p8) mov r29=b0 // save b0
340 (p8) br.cond.dptk dtlb_fault
342 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
343 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
344 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
345 shr.u r18=r16,57 // move address bit 61 to bit 4
346 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
347 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
349 andcm r18=0x10,r18 // bit 4=~address-bit(61)
351 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
352 (p8) br.cond.spnt page_fault
354 dep r21=-1,r21,IA64_PSR_ED_BIT,1
355 or r19=r19,r17 // insert PTE control bits into r19
357 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
360 (p7) itc.d r19 // insert the TLB entry
366 /////////////////////////////////////////////////////////////////////////////////////////
367 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
368 ENTRY(nested_dtlb_miss)
370 * In the absence of kernel bugs, we get here when the virtually mapped linear
371 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
372 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
373 * table is missing, a nested TLB miss fault is triggered and control is
374 * transferred to this point. When this happens, we lookup the pte for the
375 * faulting address by walking the page table in physical mode and return to the
376 * continuation point passed in register r30 (or call page_fault if the address is
379 * Input: r16: faulting address
381 * r30: continuation address
384 * Output: r17: physical address of L3 PTE of faulting address
386 * r30: continuation address
389 * Clobbered: b0, r18, r19, r21, psr.dt (cleared)
391 rsm psr.dt // switch to using physical data addressing
392 mov r19=IA64_KR(PT_BASE) // get the page table base address
393 shl r21=r16,3 // shift bit 60 into sign bit
395 shr.u r17=r16,61 // get the region number into r17
397 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
398 shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address
400 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
403 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
405 .pred.rel "mutex", p6, p7
406 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
407 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
409 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
410 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
411 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
412 shr.u r18=r16,PMD_SHIFT // shift L2 index into position
414 ld8 r17=[r17] // fetch the L1 entry (may be 0)
416 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
417 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
419 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
420 shr.u r19=r16,PAGE_SHIFT // shift L3 index into position
422 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
423 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
424 (p6) br.cond.spnt page_fault
426 br.sptk.many b0 // return to continuation point
427 END(nested_dtlb_miss)
430 /////////////////////////////////////////////////////////////////////////////////////////
431 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
437 //-----------------------------------------------------------------------------------
438 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
445 alloc r15=ar.pfs,0,0,3,0
448 adds r3=8,r2 // set up second base pointer
450 ssm psr.ic | PSR_DEFAULT_BITS
452 srlz.i // guarantee that interruption collectin is on
454 (p15) ssm psr.i // restore psr.i
455 movl r14=ia64_leave_kernel
460 adds out2=16,r12 // out2 = pointer to pt_regs
461 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
465 /////////////////////////////////////////////////////////////////////////////////////////
466 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
473 /////////////////////////////////////////////////////////////////////////////////////////
474 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
478 * What we do here is to simply turn on the dirty bit in the PTE. We need to
479 * update both the page-table and the TLB entry. To efficiently access the PTE,
480 * we address it through the virtual page table. Most likely, the TLB entry for
481 * the relevant virtual page table page is still present in the TLB so we can
482 * normally do this without additional TLB misses. In case the necessary virtual
483 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
484 * up the physical address of the L3 PTE and then continue at label 1 below.
486 mov r16=cr.ifa // get the address that caused the fault
487 movl r30=1f // load continuation point in case of nested fault
489 thash r17=r16 // compute virtual address of L3 PTE
490 mov r29=b0 // save b0 in case of nested fault
491 mov r31=pr // save pr
493 mov r28=ar.ccv // save ar.ccv
496 ;; // avoid RAW on r18
497 mov ar.ccv=r18 // set compare value for cmpxchg
498 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
500 cmpxchg8.acq r26=[r17],r25,ar.ccv
501 mov r24=PAGE_SHIFT<<2
505 (p6) itc.d r25 // install updated PTE
507 ld8 r18=[r17] // read PTE again
509 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
512 mov b0=r29 // restore b0
517 ;; // avoid RAW on r18
518 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
519 mov b0=r29 // restore b0
521 st8 [r17]=r18 // store back updated PTE
522 itc.d r18 // install updated PTE
524 mov pr=r31,-1 // restore pr
529 /////////////////////////////////////////////////////////////////////////////////////////
530 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
533 // Like Entry 8, except for instruction access
534 mov r16=cr.ifa // get the address that caused the fault
535 movl r30=1f // load continuation point in case of nested fault
536 mov r31=pr // save predicates
537 #ifdef CONFIG_ITANIUM
539 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
544 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
546 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
547 #endif /* CONFIG_ITANIUM */
549 thash r17=r16 // compute virtual address of L3 PTE
550 mov r29=b0 // save b0 in case of nested fault)
552 mov r28=ar.ccv // save ar.ccv
556 mov ar.ccv=r18 // set compare value for cmpxchg
557 or r25=_PAGE_A,r18 // set the accessed bit
559 cmpxchg8.acq r26=[r17],r25,ar.ccv
560 mov r24=PAGE_SHIFT<<2
564 (p6) itc.i r25 // install updated PTE
566 ld8 r18=[r17] // read PTE again
568 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
571 mov b0=r29 // restore b0
573 #else /* !CONFIG_SMP */
577 or r18=_PAGE_A,r18 // set the accessed bit
578 mov b0=r29 // restore b0
580 st8 [r17]=r18 // store back updated PTE
581 itc.i r18 // install updated PTE
582 #endif /* !CONFIG_SMP */
588 /////////////////////////////////////////////////////////////////////////////////////////
589 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
592 // Like Entry 8, except for data access
593 mov r16=cr.ifa // get the address that caused the fault
594 movl r30=1f // load continuation point in case of nested fault
596 thash r17=r16 // compute virtual address of L3 PTE
598 mov r29=b0 // save b0 in case of nested fault)
600 mov r28=ar.ccv // save ar.ccv
603 ;; // avoid RAW on r18
604 mov ar.ccv=r18 // set compare value for cmpxchg
605 or r25=_PAGE_A,r18 // set the dirty bit
607 cmpxchg8.acq r26=[r17],r25,ar.ccv
608 mov r24=PAGE_SHIFT<<2
612 (p6) itc.d r25 // install updated PTE
614 ld8 r18=[r17] // read PTE again
616 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
623 ;; // avoid RAW on r18
624 or r18=_PAGE_A,r18 // set the accessed bit
626 st8 [r17]=r18 // store back updated PTE
627 itc.d r18 // install updated PTE
629 mov b0=r29 // restore b0
635 /////////////////////////////////////////////////////////////////////////////////////////
636 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
639 * The streamlined system call entry/exit paths only save/restore the initial part
640 * of pt_regs. This implies that the callers of system-calls must adhere to the
641 * normal procedure calling conventions.
643 * Registers to be saved & restored:
644 * CR registers: cr.ipsr, cr.iip, cr.ifs
645 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
646 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
647 * Registers to be restored only:
648 * r8-r11: output value from the system call.
650 * During system call exit, scratch registers (including r15) are modified/cleared
651 * to prevent leaking bits from kernel to user level.
654 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat.
656 mov r18=__IA64_BREAK_SYSCALL
664 mov r31=pr // prepare to save predicates
667 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
668 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so)
669 (p7) br.cond.spnt non_syscall
671 ld1 r17=[r16] // load current->thread.on_ustack flag
672 st1 [r16]=r0 // clear current->thread.on_ustack flag
673 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT
677 /* adjust return address so we skip over the break instruction: */
679 extr.u r8=r29,41,2 // extract ei field from cr.ipsr
681 cmp.eq p6,p7=2,r8 // isr.ei==2?
682 mov r2=r1 // setup r2 for ia64_syscall_setup
684 (p6) mov r8=0 // clear ei to 0
685 (p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
686 (p7) adds r8=1,r8 // increment ei to next slot
688 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
689 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
692 // switch from user to kernel RBS:
693 MINSTATE_START_SAVE_MIN_VIRT
694 br.call.sptk.many b7=ia64_syscall_setup
696 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
697 ssm psr.ic | PSR_DEFAULT_BITS
699 srlz.i // guarantee that interruption collection is on
701 (p15) ssm psr.i // restore psr.i
703 mov r3=NR_syscalls - 1
704 movl r16=sys_call_table
706 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024
707 movl r2=ia64_ret_from_syscall
709 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
710 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
711 mov rp=r2 // set the real return addr
713 (p6) ld8 r20=[r20] // load address of syscall entry point
714 (p7) movl r20=sys_ni_syscall
716 add r2=TI_FLAGS+IA64_TASK_SIZE,r13
718 ld4 r2=[r2] // r2 = current_thread_info()->flags
720 tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
723 (p8) br.call.sptk.many b6=b6 // ignore this return addr
724 br.cond.sptk ia64_trace_syscall
729 /////////////////////////////////////////////////////////////////////////////////////////
730 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
733 mov r31=pr // prepare to save predicates
735 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
736 ssm psr.ic | PSR_DEFAULT_BITS
738 adds r3=8,r2 // set up second base pointer for SAVE_REST
739 srlz.i // ensure everybody knows psr.ic is back on
743 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
744 mov out0=cr.ivr // pass cr.ivr as first arg
745 add out1=16,sp // pass pointer to pt_regs as second arg
747 srlz.d // make sure we see the effect of cr.ivr
748 movl r14=ia64_leave_kernel
751 br.call.sptk.many b6=ia64_handle_irq
755 /////////////////////////////////////////////////////////////////////////////////////////
756 // 0x3400 Entry 13 (size 64 bundles) Reserved
761 /////////////////////////////////////////////////////////////////////////////////////////
762 // 0x3800 Entry 14 (size 64 bundles) Reserved
767 * There is no particular reason for this code to be here, other than that
768 * there happens to be space here that would go unused otherwise. If this
769 * fault ever gets "unreserved", simply moved the following code to a more
772 * ia64_syscall_setup() is a separate subroutine so that it can
773 * allocate stacked registers so it can safely demine any
774 * potential NaT values from the input registers.
777 * - executing on bank 0 or bank 1 register set (doesn't matter)
778 * - r1: stack pointer
779 * - r2: current task pointer
781 * - r11: original contents (saved ar.pfs to be saved)
782 * - r12: original contents (sp to be saved)
783 * - r13: original contents (tp to be saved)
784 * - r15: original contents (syscall # to be saved)
785 * - r18: saved bsp (after switching to kernel stack)
787 * - r20: saved r1 (gp)
788 * - r21: saved ar.fpsr
789 * - r22: kernel's register backing store base (krbs_base)
790 * - r23: saved ar.bspstore
791 * - r24: saved ar.rnat
792 * - r25: saved ar.unat
793 * - r26: saved ar.pfs
794 * - r27: saved ar.rsc
795 * - r28: saved cr.iip
796 * - r29: saved cr.ipsr
798 * - b0: original contents (to be saved)
800 * - executing on bank 1 registers
801 * - psr.ic enabled, interrupts restored
803 * - r3: preserved (same as on entry)
804 * - r12: points to kernel stack
805 * - r13: points to current task
806 * - p15: TRUE if interrupts need to be re-enabled
807 * - ar.fpsr: set to kernel settings
809 GLOBAL_ENTRY(ia64_syscall_setup)
811 # error This code assumes that b6 is the first field in pt_regs.
813 st8 [r1]=r19 // save b6
814 add r16=PT(CR_IPSR),r1 // initialize first base pointer
815 add r17=PT(R11),r1 // initialize second base pointer
817 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
818 st8 [r16]=r29,PT(CR_IFS)-PT(CR_IPSR) // save cr.ipsr
821 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
823 (pKStk) mov r18=r0 // make sure r18 isn't NaT
826 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
827 mov r28=b0 // save b0 (2 cyc)
831 st8 [r16]=r0,PT(AR_PFS)-PT(CR_IFS) // clear cr.ifs
832 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
836 st8 [r16]=r26,PT(AR_RNAT)-PT(AR_PFS) // save ar.pfs
837 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
840 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
841 tbit.nz p15,p0=r29,IA64_PSR_I_BIT
844 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
845 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
852 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
853 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
854 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
856 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
857 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
860 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
861 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
865 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
866 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
869 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
870 st8.spill [r17]=r15 // save r15
873 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
874 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
877 mov r13=r2 // establish `current'
878 movl r1=__gp // establish kernel global pointer
883 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
884 movl r17=FPSR_DEFAULT
886 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
889 END(ia64_syscall_setup)
892 /////////////////////////////////////////////////////////////////////////////////////////
893 // 0x3c00 Entry 15 (size 64 bundles) Reserved
898 * Squatting in this space ...
900 * This special case dispatcher for illegal operation faults allows preserved
901 * registers to be modified through a callback function (asm only) that is handed
902 * back from the fault handler in r8. Up to three arguments can be passed to the
903 * callback function by returning an aggregate with the callback as its first
904 * element, followed by the arguments.
906 ENTRY(dispatch_illegal_op_fault)
908 ssm psr.ic | PSR_DEFAULT_BITS
910 srlz.i // guarantee that interruption collection is on
912 (p15) ssm psr.i // restore psr.i
913 adds r3=8,r2 // set up second base pointer for SAVE_REST
915 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
920 br.call.sptk.many rp=ia64_illegal_op_fault
922 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
926 movl r15=ia64_leave_kernel
932 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
933 br.sptk.many ia64_leave_kernel
934 END(dispatch_illegal_op_fault)
937 /////////////////////////////////////////////////////////////////////////////////////////
938 // 0x4000 Entry 16 (size 64 bundles) Reserved
943 /////////////////////////////////////////////////////////////////////////////////////////
944 // 0x4400 Entry 17 (size 64 bundles) Reserved
951 // There is no particular reason for this code to be here, other than that
952 // there happens to be space here that would go unused otherwise. If this
953 // fault ever gets "unreserved", simply moved the following code to a more
956 alloc r14=ar.pfs,0,0,2,0
959 adds r3=8,r2 // set up second base pointer for SAVE_REST
961 ssm psr.ic | PSR_DEFAULT_BITS
963 srlz.i // guarantee that interruption collection is on
965 (p15) ssm psr.i // restore psr.i
966 movl r15=ia64_leave_kernel
971 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
975 /////////////////////////////////////////////////////////////////////////////////////////
976 // 0x4800 Entry 18 (size 64 bundles) Reserved
981 * There is no particular reason for this code to be here, other than that
982 * there happens to be space here that would go unused otherwise. If this
983 * fault ever gets "unreserved", simply moved the following code to a more
987 ENTRY(dispatch_unaligned_handler)
990 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
994 ssm psr.ic | PSR_DEFAULT_BITS
996 srlz.i // guarantee that interruption collection is on
998 (p15) ssm psr.i // restore psr.i
999 adds r3=8,r2 // set up second base pointer
1002 movl r14=ia64_leave_kernel
1005 br.sptk.many ia64_prepare_handle_unaligned
1006 END(dispatch_unaligned_handler)
1008 .org ia64_ivt+0x4c00
1009 /////////////////////////////////////////////////////////////////////////////////////////
1010 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1015 * There is no particular reason for this code to be here, other than that
1016 * there happens to be space here that would go unused otherwise. If this
1017 * fault ever gets "unreserved", simply moved the following code to a more
1021 ENTRY(dispatch_to_fault_handler)
1025 * r19: fault vector number (e.g., 24 for General Exception)
1026 * r31: contains saved predicates (pr)
1028 SAVE_MIN_WITH_COVER_R19
1029 alloc r14=ar.pfs,0,0,5,0
1036 ssm psr.ic | PSR_DEFAULT_BITS
1038 srlz.i // guarantee that interruption collection is on
1040 (p15) ssm psr.i // restore psr.i
1041 adds r3=8,r2 // set up second base pointer for SAVE_REST
1044 movl r14=ia64_leave_kernel
1047 br.call.sptk.many b6=ia64_fault
1048 END(dispatch_to_fault_handler)
1051 // --- End of long entries, Beginning of short entries
1054 .org ia64_ivt+0x5000
1055 /////////////////////////////////////////////////////////////////////////////////////////
1056 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1057 ENTRY(page_not_present)
1062 * The Linux page fault handler doesn't expect non-present pages to be in
1063 * the TLB. Flush the existing entry now, so we meet that expectation.
1065 mov r17=PAGE_SHIFT<<2
1071 br.sptk.many page_fault
1072 END(page_not_present)
1074 .org ia64_ivt+0x5100
1075 /////////////////////////////////////////////////////////////////////////////////////////
1076 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1077 ENTRY(key_permission)
1084 br.sptk.many page_fault
1087 .org ia64_ivt+0x5200
1088 /////////////////////////////////////////////////////////////////////////////////////////
1089 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1090 ENTRY(iaccess_rights)
1097 br.sptk.many page_fault
1100 .org ia64_ivt+0x5300
1101 /////////////////////////////////////////////////////////////////////////////////////////
1102 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1103 ENTRY(daccess_rights)
1110 br.sptk.many page_fault
1113 .org ia64_ivt+0x5400
1114 /////////////////////////////////////////////////////////////////////////////////////////
1115 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1116 ENTRY(general_exception)
1122 (p6) br.sptk.many dispatch_illegal_op_fault
1124 mov r19=24 // fault number
1125 br.sptk.many dispatch_to_fault_handler
1126 END(general_exception)
1128 .org ia64_ivt+0x5500
1129 /////////////////////////////////////////////////////////////////////////////////////////
1130 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1131 ENTRY(disabled_fp_reg)
1133 rsm psr.dfh // ensure we can access fph
1138 br.sptk.many dispatch_to_fault_handler
1139 END(disabled_fp_reg)
1141 .org ia64_ivt+0x5600
1142 /////////////////////////////////////////////////////////////////////////////////////////
1143 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1144 ENTRY(nat_consumption)
1147 END(nat_consumption)
1149 .org ia64_ivt+0x5700
1150 /////////////////////////////////////////////////////////////////////////////////////////
1151 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1152 ENTRY(speculation_vector)
1155 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1156 * this part of the architecture is not implemented in hardware on some CPUs, such
1157 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1158 * the relative target (not yet sign extended). So after sign extending it we
1159 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1160 * i.e., the slot to restart into.
1162 * cr.imm contains zero_ext(imm21)
1167 shl r18=r18,43 // put sign bit in position (43=64-21)
1171 shr r18=r18,39 // sign extend (39=43-4)
1174 add r17=r17,r18 // now add the offset
1177 dep r16=0,r16,41,2 // clear EI
1184 END(speculation_vector)
1186 .org ia64_ivt+0x5800
1187 /////////////////////////////////////////////////////////////////////////////////////////
1188 // 0x5800 Entry 28 (size 16 bundles) Reserved
1192 .org ia64_ivt+0x5900
1193 /////////////////////////////////////////////////////////////////////////////////////////
1194 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1200 .org ia64_ivt+0x5a00
1201 /////////////////////////////////////////////////////////////////////////////////////////
1202 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1203 ENTRY(unaligned_access)
1206 mov r31=pr // prepare to save predicates
1208 br.sptk.many dispatch_unaligned_handler
1209 END(unaligned_access)
1211 .org ia64_ivt+0x5b00
1212 /////////////////////////////////////////////////////////////////////////////////////////
1213 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1214 ENTRY(unsupported_data_reference)
1217 END(unsupported_data_reference)
1219 .org ia64_ivt+0x5c00
1220 /////////////////////////////////////////////////////////////////////////////////////////
1221 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1222 ENTRY(floating_point_fault)
1225 END(floating_point_fault)
1227 .org ia64_ivt+0x5d00
1228 /////////////////////////////////////////////////////////////////////////////////////////
1229 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1230 ENTRY(floating_point_trap)
1233 END(floating_point_trap)
1235 .org ia64_ivt+0x5e00
1236 /////////////////////////////////////////////////////////////////////////////////////////
1237 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1238 ENTRY(lower_privilege_trap)
1241 END(lower_privilege_trap)
1243 .org ia64_ivt+0x5f00
1244 /////////////////////////////////////////////////////////////////////////////////////////
1245 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1246 ENTRY(taken_branch_trap)
1249 END(taken_branch_trap)
1251 .org ia64_ivt+0x6000
1252 /////////////////////////////////////////////////////////////////////////////////////////
1253 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1254 ENTRY(single_step_trap)
1257 END(single_step_trap)
1259 .org ia64_ivt+0x6100
1260 /////////////////////////////////////////////////////////////////////////////////////////
1261 // 0x6100 Entry 37 (size 16 bundles) Reserved
1265 .org ia64_ivt+0x6200
1266 /////////////////////////////////////////////////////////////////////////////////////////
1267 // 0x6200 Entry 38 (size 16 bundles) Reserved
1271 .org ia64_ivt+0x6300
1272 /////////////////////////////////////////////////////////////////////////////////////////
1273 // 0x6300 Entry 39 (size 16 bundles) Reserved
1277 .org ia64_ivt+0x6400
1278 /////////////////////////////////////////////////////////////////////////////////////////
1279 // 0x6400 Entry 40 (size 16 bundles) Reserved
1283 .org ia64_ivt+0x6500
1284 /////////////////////////////////////////////////////////////////////////////////////////
1285 // 0x6500 Entry 41 (size 16 bundles) Reserved
1289 .org ia64_ivt+0x6600
1290 /////////////////////////////////////////////////////////////////////////////////////////
1291 // 0x6600 Entry 42 (size 16 bundles) Reserved
1295 .org ia64_ivt+0x6700
1296 /////////////////////////////////////////////////////////////////////////////////////////
1297 // 0x6700 Entry 43 (size 16 bundles) Reserved
1301 .org ia64_ivt+0x6800
1302 /////////////////////////////////////////////////////////////////////////////////////////
1303 // 0x6800 Entry 44 (size 16 bundles) Reserved
1307 .org ia64_ivt+0x6900
1308 /////////////////////////////////////////////////////////////////////////////////////////
1309 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1310 ENTRY(ia32_exception)
1315 .org ia64_ivt+0x6a00
1316 /////////////////////////////////////////////////////////////////////////////////////////
1317 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1318 ENTRY(ia32_intercept)
1320 #ifdef CONFIG_IA32_SUPPORT
1324 extr.u r17=r16,16,8 // get ISR.code
1326 mov r19=cr.iim // old eflag value
1329 (p6) br.cond.spnt 1f // not a system flag fault
1332 extr.u r17=r16,18,1 // get the eflags.ac bit
1335 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1337 mov pr=r31,-1 // restore predicate registers
1341 #endif // CONFIG_IA32_SUPPORT
1345 .org ia64_ivt+0x6b00
1346 /////////////////////////////////////////////////////////////////////////////////////////
1347 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1348 ENTRY(ia32_interrupt)
1350 #ifdef CONFIG_IA32_SUPPORT
1352 br.sptk.many dispatch_to_ia32_handler
1358 .org ia64_ivt+0x6c00
1359 /////////////////////////////////////////////////////////////////////////////////////////
1360 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1364 .org ia64_ivt+0x6d00
1365 /////////////////////////////////////////////////////////////////////////////////////////
1366 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1370 .org ia64_ivt+0x6e00
1371 /////////////////////////////////////////////////////////////////////////////////////////
1372 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1376 .org ia64_ivt+0x6f00
1377 /////////////////////////////////////////////////////////////////////////////////////////
1378 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1382 .org ia64_ivt+0x7000
1383 /////////////////////////////////////////////////////////////////////////////////////////
1384 // 0x7000 Entry 52 (size 16 bundles) Reserved
1388 .org ia64_ivt+0x7100
1389 /////////////////////////////////////////////////////////////////////////////////////////
1390 // 0x7100 Entry 53 (size 16 bundles) Reserved
1394 .org ia64_ivt+0x7200
1395 /////////////////////////////////////////////////////////////////////////////////////////
1396 // 0x7200 Entry 54 (size 16 bundles) Reserved
1400 .org ia64_ivt+0x7300
1401 /////////////////////////////////////////////////////////////////////////////////////////
1402 // 0x7300 Entry 55 (size 16 bundles) Reserved
1406 .org ia64_ivt+0x7400
1407 /////////////////////////////////////////////////////////////////////////////////////////
1408 // 0x7400 Entry 56 (size 16 bundles) Reserved
1412 .org ia64_ivt+0x7500
1413 /////////////////////////////////////////////////////////////////////////////////////////
1414 // 0x7500 Entry 57 (size 16 bundles) Reserved
1418 .org ia64_ivt+0x7600
1419 /////////////////////////////////////////////////////////////////////////////////////////
1420 // 0x7600 Entry 58 (size 16 bundles) Reserved
1424 .org ia64_ivt+0x7700
1425 /////////////////////////////////////////////////////////////////////////////////////////
1426 // 0x7700 Entry 59 (size 16 bundles) Reserved
1430 .org ia64_ivt+0x7800
1431 /////////////////////////////////////////////////////////////////////////////////////////
1432 // 0x7800 Entry 60 (size 16 bundles) Reserved
1436 .org ia64_ivt+0x7900
1437 /////////////////////////////////////////////////////////////////////////////////////////
1438 // 0x7900 Entry 61 (size 16 bundles) Reserved
1442 .org ia64_ivt+0x7a00
1443 /////////////////////////////////////////////////////////////////////////////////////////
1444 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1448 .org ia64_ivt+0x7b00
1449 /////////////////////////////////////////////////////////////////////////////////////////
1450 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1454 .org ia64_ivt+0x7c00
1455 /////////////////////////////////////////////////////////////////////////////////////////
1456 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1460 .org ia64_ivt+0x7d00
1461 /////////////////////////////////////////////////////////////////////////////////////////
1462 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1466 .org ia64_ivt+0x7e00
1467 /////////////////////////////////////////////////////////////////////////////////////////
1468 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1472 .org ia64_ivt+0x7f00
1473 /////////////////////////////////////////////////////////////////////////////////////////
1474 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1478 #ifdef CONFIG_IA32_SUPPORT
1481 * There is no particular reason for this code to be here, other than that
1482 * there happens to be space here that would go unused otherwise. If this
1483 * fault ever gets "unreserved", simply moved the following code to a more
1487 // IA32 interrupt entry point
1489 ENTRY(dispatch_to_ia32_handler)
1493 ssm psr.ic | PSR_DEFAULT_BITS
1495 srlz.i // guarantee that interruption collection is on
1498 adds r3=8,r2 // Base pointer for SAVE_REST
1503 shr r14=r14,16 // Get interrupt number
1505 cmp.ne p6,p0=r14,r15
1506 (p6) br.call.dpnt.many b6=non_ia32_syscall
1508 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1509 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1511 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1512 ld8 r8=[r14] // get r8
1514 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1516 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1518 ld4 r8=[r14],8 // r8 == eax (syscall number)
1519 mov r15=IA32_NR_syscalls
1521 cmp.ltu.unc p6,p7=r8,r15
1522 ld4 out1=[r14],8 // r9 == ecx
1524 ld4 out2=[r14],8 // r10 == edx
1526 ld4 out0=[r14] // r11 == ebx
1527 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
1529 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
1531 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
1532 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
1534 ld4 out4=[r14] // r15 == edi
1535 movl r16=ia32_syscall_table
1537 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
1538 ld4 r2=[r2] // r2 = current_thread_info()->flags
1541 tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
1544 movl r15=ia32_ret_from_syscall
1547 (p8) br.call.sptk.many b6=b6
1548 br.cond.sptk ia32_trace_syscall
1551 alloc r15=ar.pfs,0,0,2,0
1552 mov out0=r14 // interrupt #
1553 add out1=16,sp // pointer to pt_regs
1554 ;; // avoid WAW on CFM
1555 br.call.sptk.many rp=ia32_bad_interrupt
1556 .ret1: movl r15=ia64_leave_kernel
1560 END(dispatch_to_ia32_handler)
1562 #endif /* CONFIG_IA32_SUPPORT */