arch/ia64/kernel/mca.c

   1 /*
   2  * File:        mca.c
   3  * Purpose:     Generic MCA handling layer
   4  *
   5  * Updated for latest kernel
   6  * Copyright (C) 2003 Hewlett-Packard Co
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *
   9  * Copyright (C) 2002 Dell Inc.
  10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
  11  *
  12  * Copyright (C) 2002 Intel
  13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
  14  *
  15  * Copyright (C) 2001 Intel
  16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  17  *
  18  * Copyright (C) 2000 Intel
  19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
  20  *
  21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
  22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  23  *
  24  * 03/04/15 D. Mosberger Added INIT backtrace support.
  25  * 02/03/25 M. Domsch   GUID cleanups
  26  *
  27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
  28  *                      error flag, set SAL default return values, changed
  29  *                      error record structure to linked list, added init call
  30  *                      to sal_get_state_info_size().
  31  *
  32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  33  *                      platform errors, completed code for logging of
  34  *                      corrected & uncorrected machine check errors, and
  35  *                      updated for conformance with Nov. 2000 revision of the
  36  *                      SAL 3.0 spec.
  37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  38  *                           added min save state dump, added INIT handler.
  39  *
  40  * 2003-12-08 Keith Owens <kaos@sgi.com>
  41  *            smp_call_function() must not be called from interrupt context (can
  42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
  43  *
  44  * 2004-02-01 Keith Owens <kaos@sgi.com>
  45  *            Avoid deadlock when using printk() for MCA and INIT records.
  46  *            Delete all record printing code, moved to salinfo_decode in user space.
  47  *            Mark variables and functions static where possible.
  48  *            Delete dead variables and functions.
  49  *            Reorder to remove the need for forward declarations and to consolidate
  50  *            related code.
  51  */
  52 #include <linux/config.h>
  53 #include <linux/types.h>
  54 #include <linux/init.h>
  55 #include <linux/sched.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/irq.h>
  58 #include <linux/kallsyms.h>
  59 #include <linux/smp_lock.h>
  60 #include <linux/bootmem.h>
  61 #include <linux/acpi.h>
  62 #include <linux/timer.h>
  63 #include <linux/module.h>
  64 #include <linux/kernel.h>
  65 #include <linux/smp.h>
  66 #include <linux/workqueue.h>
  67
  68 #include <asm/delay.h>
  69 #include <asm/machvec.h>
  70 #include <asm/page.h>
  71 #include <asm/ptrace.h>
  72 #include <asm/system.h>
  73 #include <asm/sal.h>
  74 #include <asm/mca.h>
  75
  76 #include <asm/irq.h>
  77 #include <asm/hw_irq.h>
  78
  79 #if defined(IA64_MCA_DEBUG_INFO)
  80 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
  81 #else
  82 # define IA64_MCA_DEBUG(fmt...)
  83 #endif
  84
  85 typedef struct ia64_fptr {
  86         unsigned long fp;
  87         unsigned long gp;
  88 } ia64_fptr_t;
  89
  90 /* Used by mca_asm.S */
  91 ia64_mca_sal_to_os_state_t      ia64_sal_to_os_handoff_state;
  92 ia64_mca_os_to_sal_state_t      ia64_os_to_sal_handoff_state;
  93 u64                             ia64_mca_proc_state_dump[512];
  94 u64                             ia64_mca_stack[1024] __attribute__((aligned(16)));
  95 u64                             ia64_mca_stackframe[32];
  96 u64                             ia64_mca_bspstore[1024];
  97 u64                             ia64_init_stack[KERNEL_STACK_SIZE/8] __attribute__((aligned(16)));
  98 u64                             ia64_mca_serialize;
  99
 100 /* In mca_asm.S */
 101 extern void                     ia64_monarch_init_handler (void);
 102 extern void                     ia64_slave_init_handler (void);
 103
 104 static ia64_mc_info_t           ia64_mc_info;
 105
 106 struct ia64_mca_tlb_info ia64_mca_tlb_list[NR_CPUS];
 107
 108 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 109 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 110 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 111 #define CPE_HISTORY_LENGTH    5
 112 #define CMC_HISTORY_LENGTH    5
 113
 114 static struct timer_list cpe_poll_timer;
 115 static struct timer_list cmc_poll_timer;
 116 /*
 117  * This variable tells whether we are currently in polling mode.
 118  * Start with this in the wrong state so we won't play w/ timers
 119  * before the system is ready.
 120  */
 121 static int cmc_polling_enabled = 1;
 122
 123 /*
 124  * Clearing this variable prevents CPE polling from getting activated
 125  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 126  * but encounters problems retrieving CPE logs.  This should only be
 127  * necessary for debugging.
 128  */
 129 static int cpe_poll_enabled = 1;
 130
 131 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 132
 133 static int mca_init;
 134
 135 /*
 136  * IA64_MCA log support
 137  */
 138 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 139 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 140
 141 typedef struct ia64_state_log_s
 142 {
 143         spinlock_t      isl_lock;
 144         int             isl_index;
 145         unsigned long   isl_count;
 146         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 147 } ia64_state_log_t;
 148
 149 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 150
 151 #define IA64_LOG_ALLOCATE(it, size) \
 152         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 153                 (ia64_err_rec_t *)alloc_bootmem(size); \
 154         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 155                 (ia64_err_rec_t *)alloc_bootmem(size);}
 156 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 157 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 158 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 159 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 160 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 161 #define IA64_LOG_INDEX_INC(it) \
 162     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 163     ia64_state_log[it].isl_count++;}
 164 #define IA64_LOG_INDEX_DEC(it) \
 165     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 166 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 167 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 168 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 169
 170 /*
 171  * ia64_log_init
 172  *      Reset the OS ia64 log buffer
 173  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 174  * Outputs      :       None
 175  */
 176 static void
 177 ia64_log_init(int sal_info_type)
 178 {
 179         u64     max_size = 0;
 180
 181         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 182         IA64_LOG_LOCK_INIT(sal_info_type);
 183
 184         // SAL will tell us the maximum size of any error record of this type
 185         max_size = ia64_sal_get_state_info_size(sal_info_type);
 186         if (!max_size)
 187                 /* alloc_bootmem() doesn't like zero-sized allocations! */
 188                 return;
 189
 190         // set up OS data structures to hold error info
 191         IA64_LOG_ALLOCATE(sal_info_type, max_size);
 192         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 193         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 194 }
 195
 196 /*
 197  * ia64_log_get
 198  *
 199  *      Get the current MCA log from SAL and copy it into the OS log buffer.
 200  *
 201  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 202  *              irq_safe    whether you can use printk at this point
 203  *  Outputs :   size        (total record length)
 204  *              *buffer     (ptr to error record)
 205  *
 206  */
 207 static u64
 208 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 209 {
 210         sal_log_record_header_t     *log_buffer;
 211         u64                         total_len = 0;
 212         int                         s;
 213
 214         IA64_LOG_LOCK(sal_info_type);
 215
 216         /* Get the process state information */
 217         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 218
 219         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 220
 221         if (total_len) {
 222                 IA64_LOG_INDEX_INC(sal_info_type);
 223                 IA64_LOG_UNLOCK(sal_info_type);
 224                 if (irq_safe) {
 225                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
 226                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
 227                 }
 228                 *buffer = (u8 *) log_buffer;
 229                 return total_len;
 230         } else {
 231                 IA64_LOG_UNLOCK(sal_info_type);
 232                 return 0;
 233         }
 234 }
 235
 236 /*
 237  *  ia64_mca_log_sal_error_record
 238  *
 239  *  This function retrieves a specified error record type from SAL
 240  *  and wakes up any processes waiting for error records.
 241  *
 242  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE/INIT)
 243  */
 244 static void
 245 ia64_mca_log_sal_error_record(int sal_info_type)
 246 {
 247         u8 *buffer;
 248         u64 size;
 249         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA && sal_info_type != SAL_INFO_TYPE_INIT;
 250 #ifdef IA64_MCA_DEBUG_INFO
 251         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 252 #endif
 253
 254         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 255         if (!size)
 256                 return;
 257
 258         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 259
 260         if (irq_safe)
 261                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 262                         smp_processor_id(),
 263                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 264
 265         /* Clear logs from corrected errors in case there's no user-level logger */
 266         if (sal_info_type == SAL_INFO_TYPE_CPE || sal_info_type == SAL_INFO_TYPE_CMC)
 267                 ia64_sal_clear_state_info(sal_info_type);
 268 }
 269
 270 /*
 271  * platform dependent error handling
 272  */
 273 #ifndef PLATFORM_MCA_HANDLERS
 274
 275 #ifdef CONFIG_ACPI
 276
 277 static int cpe_vector = -1;
 278
 279 static irqreturn_t
 280 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
 281 {
 282         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 283         static int              index;
 284         static spinlock_t       cpe_history_lock = SPIN_LOCK_UNLOCKED;
 285
 286         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 287                        __FUNCTION__, cpe_irq, smp_processor_id());
 288
 289         /* SAL spec states this should run w/ interrupts enabled */
 290         local_irq_enable();
 291
 292         /* Get the CPE error record and log it */
 293         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 294
 295         spin_lock(&cpe_history_lock);
 296         if (!cpe_poll_enabled && cpe_vector >= 0) {
 297
 298                 int i, count = 1; /* we know 1 happened now */
 299                 unsigned long now = jiffies;
 300
 301                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 302                         if (now - cpe_history[i] <= HZ)
 303                                 count++;
 304                 }
 305
 306                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 307                 if (count >= CPE_HISTORY_LENGTH) {
 308
 309                         cpe_poll_enabled = 1;
 310                         spin_unlock(&cpe_history_lock);
 311                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 312
 313                         /*
 314                          * Corrected errors will still be corrected, but
 315                          * make sure there's a log somewhere that indicates
 316                          * something is generating more than we can handle.
 317                          */
 318                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 319
 320                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 321
 322                         /* lock already released, get out now */
 323                         return IRQ_HANDLED;
 324                 } else {
 325                         cpe_history[index++] = now;
 326                         if (index == CPE_HISTORY_LENGTH)
 327                                 index = 0;
 328                 }
 329         }
 330         spin_unlock(&cpe_history_lock);
 331         return IRQ_HANDLED;
 332 }
 333
 334 #endif /* CONFIG_ACPI */
 335
 336 static void
 337 show_min_state (pal_min_state_area_t *minstate)
 338 {
 339         u64 iip = minstate->pmsa_iip + ((struct ia64_psr *)(&minstate->pmsa_ipsr))->ri;
 340         u64 xip = minstate->pmsa_xip + ((struct ia64_psr *)(&minstate->pmsa_xpsr))->ri;
 341
 342         printk("NaT bits\t%016lx\n", minstate->pmsa_nat_bits);
 343         printk("pr\t\t%016lx\n", minstate->pmsa_pr);
 344         printk("b0\t\t%016lx ", minstate->pmsa_br0); print_symbol("%s\n", minstate->pmsa_br0);
 345         printk("ar.rsc\t\t%016lx\n", minstate->pmsa_rsc);
 346         printk("cr.iip\t\t%016lx ", iip); print_symbol("%s\n", iip);
 347         printk("cr.ipsr\t\t%016lx\n", minstate->pmsa_ipsr);
 348         printk("cr.ifs\t\t%016lx\n", minstate->pmsa_ifs);
 349         printk("xip\t\t%016lx ", xip); print_symbol("%s\n", xip);
 350         printk("xpsr\t\t%016lx\n", minstate->pmsa_xpsr);
 351         printk("xfs\t\t%016lx\n", minstate->pmsa_xfs);
 352         printk("b1\t\t%016lx ", minstate->pmsa_br1);
 353         print_symbol("%s\n", minstate->pmsa_br1);
 354
 355         printk("\nstatic registers r0-r15:\n");
 356         printk(" r0- 3 %016lx %016lx %016lx %016lx\n",
 357                0UL, minstate->pmsa_gr[0], minstate->pmsa_gr[1], minstate->pmsa_gr[2]);
 358         printk(" r4- 7 %016lx %016lx %016lx %016lx\n",
 359                minstate->pmsa_gr[3], minstate->pmsa_gr[4],
 360                minstate->pmsa_gr[5], minstate->pmsa_gr[6]);
 361         printk(" r8-11 %016lx %016lx %016lx %016lx\n",
 362                minstate->pmsa_gr[7], minstate->pmsa_gr[8],
 363                minstate->pmsa_gr[9], minstate->pmsa_gr[10]);
 364         printk("r12-15 %016lx %016lx %016lx %016lx\n",
 365                minstate->pmsa_gr[11], minstate->pmsa_gr[12],
 366                minstate->pmsa_gr[13], minstate->pmsa_gr[14]);
 367
 368         printk("\nbank 0:\n");
 369         printk("r16-19 %016lx %016lx %016lx %016lx\n",
 370                minstate->pmsa_bank0_gr[0], minstate->pmsa_bank0_gr[1],
 371                minstate->pmsa_bank0_gr[2], minstate->pmsa_bank0_gr[3]);
 372         printk("r20-23 %016lx %016lx %016lx %016lx\n",
 373                minstate->pmsa_bank0_gr[4], minstate->pmsa_bank0_gr[5],
 374                minstate->pmsa_bank0_gr[6], minstate->pmsa_bank0_gr[7]);
 375         printk("r24-27 %016lx %016lx %016lx %016lx\n",
 376                minstate->pmsa_bank0_gr[8], minstate->pmsa_bank0_gr[9],
 377                minstate->pmsa_bank0_gr[10], minstate->pmsa_bank0_gr[11]);
 378         printk("r28-31 %016lx %016lx %016lx %016lx\n",
 379                minstate->pmsa_bank0_gr[12], minstate->pmsa_bank0_gr[13],
 380                minstate->pmsa_bank0_gr[14], minstate->pmsa_bank0_gr[15]);
 381
 382         printk("\nbank 1:\n");
 383         printk("r16-19 %016lx %016lx %016lx %016lx\n",
 384                minstate->pmsa_bank1_gr[0], minstate->pmsa_bank1_gr[1],
 385                minstate->pmsa_bank1_gr[2], minstate->pmsa_bank1_gr[3]);
 386         printk("r20-23 %016lx %016lx %016lx %016lx\n",
 387                minstate->pmsa_bank1_gr[4], minstate->pmsa_bank1_gr[5],
 388                minstate->pmsa_bank1_gr[6], minstate->pmsa_bank1_gr[7]);
 389         printk("r24-27 %016lx %016lx %016lx %016lx\n",
 390                minstate->pmsa_bank1_gr[8], minstate->pmsa_bank1_gr[9],
 391                minstate->pmsa_bank1_gr[10], minstate->pmsa_bank1_gr[11]);
 392         printk("r28-31 %016lx %016lx %016lx %016lx\n",
 393                minstate->pmsa_bank1_gr[12], minstate->pmsa_bank1_gr[13],
 394                minstate->pmsa_bank1_gr[14], minstate->pmsa_bank1_gr[15]);
 395 }
 396
 397 static void
 398 fetch_min_state (pal_min_state_area_t *ms, struct pt_regs *pt, struct switch_stack *sw)
 399 {
 400         u64 *dst_banked, *src_banked, bit, shift, nat_bits;
 401         int i;
 402
 403         /*
 404          * First, update the pt-regs and switch-stack structures with the contents stored
 405          * in the min-state area:
 406          */
 407         if (((struct ia64_psr *) &ms->pmsa_ipsr)->ic == 0) {
 408                 pt->cr_ipsr = ms->pmsa_xpsr;
 409                 pt->cr_iip = ms->pmsa_xip;
 410                 pt->cr_ifs = ms->pmsa_xfs;
 411         } else {
 412                 pt->cr_ipsr = ms->pmsa_ipsr;
 413                 pt->cr_iip = ms->pmsa_iip;
 414                 pt->cr_ifs = ms->pmsa_ifs;
 415         }
 416         pt->ar_rsc = ms->pmsa_rsc;
 417         pt->pr = ms->pmsa_pr;
 418         pt->r1 = ms->pmsa_gr[0];
 419         pt->r2 = ms->pmsa_gr[1];
 420         pt->r3 = ms->pmsa_gr[2];
 421         sw->r4 = ms->pmsa_gr[3];
 422         sw->r5 = ms->pmsa_gr[4];
 423         sw->r6 = ms->pmsa_gr[5];
 424         sw->r7 = ms->pmsa_gr[6];
 425         pt->r8 = ms->pmsa_gr[7];
 426         pt->r9 = ms->pmsa_gr[8];
 427         pt->r10 = ms->pmsa_gr[9];
 428         pt->r11 = ms->pmsa_gr[10];
 429         pt->r12 = ms->pmsa_gr[11];
 430         pt->r13 = ms->pmsa_gr[12];
 431         pt->r14 = ms->pmsa_gr[13];
 432         pt->r15 = ms->pmsa_gr[14];
 433         dst_banked = &pt->r16;          /* r16-r31 are contiguous in struct pt_regs */
 434         src_banked = ms->pmsa_bank1_gr;
 435         for (i = 0; i < 16; ++i)
 436                 dst_banked[i] = src_banked[i];
 437         pt->b0 = ms->pmsa_br0;
 438         sw->b1 = ms->pmsa_br1;
 439
 440         /* construct the NaT bits for the pt-regs structure: */
 441 #       define PUT_NAT_BIT(dst, addr)                                   \
 442         do {                                                            \
 443                 bit = nat_bits & 1; nat_bits >>= 1;                     \
 444                 shift = ((unsigned long) addr >> 3) & 0x3f;             \
 445                 dst = ((dst) & ~(1UL << shift)) | (bit << shift);       \
 446         } while (0)
 447
 448         /* Rotate the saved NaT bits such that bit 0 corresponds to pmsa_gr[0]: */
 449         shift = ((unsigned long) &ms->pmsa_gr[0] >> 3) & 0x3f;
 450         nat_bits = (ms->pmsa_nat_bits >> shift) | (ms->pmsa_nat_bits << (64 - shift));
 451
 452         PUT_NAT_BIT(sw->caller_unat, &pt->r1);
 453         PUT_NAT_BIT(sw->caller_unat, &pt->r2);
 454         PUT_NAT_BIT(sw->caller_unat, &pt->r3);
 455         PUT_NAT_BIT(sw->ar_unat, &sw->r4);
 456         PUT_NAT_BIT(sw->ar_unat, &sw->r5);
 457         PUT_NAT_BIT(sw->ar_unat, &sw->r6);
 458         PUT_NAT_BIT(sw->ar_unat, &sw->r7);
 459         PUT_NAT_BIT(sw->caller_unat, &pt->r8);  PUT_NAT_BIT(sw->caller_unat, &pt->r9);
 460         PUT_NAT_BIT(sw->caller_unat, &pt->r10); PUT_NAT_BIT(sw->caller_unat, &pt->r11);
 461         PUT_NAT_BIT(sw->caller_unat, &pt->r12); PUT_NAT_BIT(sw->caller_unat, &pt->r13);
 462         PUT_NAT_BIT(sw->caller_unat, &pt->r14); PUT_NAT_BIT(sw->caller_unat, &pt->r15);
 463         nat_bits >>= 16;        /* skip over bank0 NaT bits */
 464         PUT_NAT_BIT(sw->caller_unat, &pt->r16); PUT_NAT_BIT(sw->caller_unat, &pt->r17);
 465         PUT_NAT_BIT(sw->caller_unat, &pt->r18); PUT_NAT_BIT(sw->caller_unat, &pt->r19);
 466         PUT_NAT_BIT(sw->caller_unat, &pt->r20); PUT_NAT_BIT(sw->caller_unat, &pt->r21);
 467         PUT_NAT_BIT(sw->caller_unat, &pt->r22); PUT_NAT_BIT(sw->caller_unat, &pt->r23);
 468         PUT_NAT_BIT(sw->caller_unat, &pt->r24); PUT_NAT_BIT(sw->caller_unat, &pt->r25);
 469         PUT_NAT_BIT(sw->caller_unat, &pt->r26); PUT_NAT_BIT(sw->caller_unat, &pt->r27);
 470         PUT_NAT_BIT(sw->caller_unat, &pt->r28); PUT_NAT_BIT(sw->caller_unat, &pt->r29);
 471         PUT_NAT_BIT(sw->caller_unat, &pt->r30); PUT_NAT_BIT(sw->caller_unat, &pt->r31);
 472 }
 473
 474 static void
 475 init_handler_platform (pal_min_state_area_t *ms,
 476                        struct pt_regs *pt, struct switch_stack *sw)
 477 {
 478         struct unw_frame_info info;
 479
 480         /* if a kernel debugger is available call it here else just dump the registers */
 481
 482         /*
 483          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
 484          * generated via the BMC's command-line interface, but since the console is on the
 485          * same serial line, the user will need some time to switch out of the BMC before
 486          * the dump begins.
 487          */
 488         printk("Delaying for 5 seconds...\n");
 489         udelay(5*1000000);
 490         show_min_state(ms);
 491
 492         printk("Backtrace of current task (pid %d, %s)\n", current->pid, current->comm);
 493         fetch_min_state(ms, pt, sw);
 494         unw_init_from_interruption(&info, current, pt, sw);
 495         ia64_do_show_stack(&info, NULL);
 496
 497 #ifdef CONFIG_SMP
 498         /* read_trylock() would be handy... */
 499         if (!tasklist_lock.write_lock)
 500                 read_lock(&tasklist_lock);
 501 #endif
 502         {
 503                 struct task_struct *g, *t;
 504                 do_each_thread (g, t) {
 505                         if (t == current)
 506                                 continue;
 507
 508                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
 509                         show_stack(t, NULL);
 510                 } while_each_thread (g, t);
 511         }
 512 #ifdef CONFIG_SMP
 513         if (!tasklist_lock.write_lock)
 514                 read_unlock(&tasklist_lock);
 515 #endif
 516
 517         printk("\nINIT dump complete.  Please reboot now.\n");
 518         while (1);                      /* hang city if no debugger */
 519 }
 520
 521 #ifdef CONFIG_ACPI
 522 /*
 523  * ia64_mca_register_cpev
 524  *
 525  *  Register the corrected platform error vector with SAL.
 526  *
 527  *  Inputs
 528  *      cpev        Corrected Platform Error Vector number
 529  *
 530  *  Outputs
 531  *      None
 532  */
 533 static void
 534 ia64_mca_register_cpev (int cpev)
 535 {
 536         /* Register the CPE interrupt vector with SAL */
 537         struct ia64_sal_retval isrv;
 538
 539         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 540         if (isrv.status) {
 541                 printk(KERN_ERR "Failed to register Corrected Platform "
 542                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 543                 return;
 544         }
 545
 546         IA64_MCA_DEBUG("%s: corrected platform error "
 547                        "vector %#x registered\n", __FUNCTION__, cpev);
 548 }
 549 #endif /* CONFIG_ACPI */
 550
 551 #endif /* PLATFORM_MCA_HANDLERS */
 552
 553 /*
 554  * ia64_mca_cmc_vector_setup
 555  *
 556  *  Setup the corrected machine check vector register in the processor.
 557  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
 558  *  This function is invoked on a per-processor basis.
 559  *
 560  * Inputs
 561  *      None
 562  *
 563  * Outputs
 564  *      None
 565  */
 566 void
 567 ia64_mca_cmc_vector_setup (void)
 568 {
 569         cmcv_reg_t      cmcv;
 570
 571         cmcv.cmcv_regval        = 0;
 572         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
 573         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 574         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 575
 576         IA64_MCA_DEBUG("%s: CPU %d corrected "
 577                        "machine check vector %#x registered.\n",
 578                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
 579
 580         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 581                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 582 }
 583
 584 /*
 585  * ia64_mca_cmc_vector_disable
 586  *
 587  *  Mask the corrected machine check vector register in the processor.
 588  *  This function is invoked on a per-processor basis.
 589  *
 590  * Inputs
 591  *      dummy(unused)
 592  *
 593  * Outputs
 594  *      None
 595  */
 596 static void
 597 ia64_mca_cmc_vector_disable (void *dummy)
 598 {
 599         cmcv_reg_t      cmcv;
 600
 601         cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV);
 602
 603         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 604         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 605
 606         IA64_MCA_DEBUG("%s: CPU %d corrected "
 607                        "machine check vector %#x disabled.\n",
 608                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 609 }
 610
 611 /*
 612  * ia64_mca_cmc_vector_enable
 613  *
 614  *  Unmask the corrected machine check vector register in the processor.
 615  *  This function is invoked on a per-processor basis.
 616  *
 617  * Inputs
 618  *      dummy(unused)
 619  *
 620  * Outputs
 621  *      None
 622  */
 623 static void
 624 ia64_mca_cmc_vector_enable (void *dummy)
 625 {
 626         cmcv_reg_t      cmcv;
 627
 628         cmcv = (cmcv_reg_t)ia64_getreg(_IA64_REG_CR_CMCV);
 629
 630         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 631         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 632
 633         IA64_MCA_DEBUG("%s: CPU %d corrected "
 634                        "machine check vector %#x enabled.\n",
 635                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
 636 }
 637
 638 /*
 639  * ia64_mca_cmc_vector_disable_keventd
 640  *
 641  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 642  * disable the cmc interrupt vector.
 643  */
 644 static void
 645 ia64_mca_cmc_vector_disable_keventd(void *unused)
 646 {
 647         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
 648 }
 649
 650 /*
 651  * ia64_mca_cmc_vector_enable_keventd
 652  *
 653  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 654  * enable the cmc interrupt vector.
 655  */
 656 static void
 657 ia64_mca_cmc_vector_enable_keventd(void *unused)
 658 {
 659         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
 660 }
 661
 662 /*
 663  * ia64_mca_wakeup_ipi_wait
 664  *
 665  *      Wait for the inter-cpu interrupt to be sent by the
 666  *      monarch processor once it is done with handling the
 667  *      MCA.
 668  *
 669  *  Inputs  :   None
 670  *  Outputs :   None
 671  */
 672 static void
 673 ia64_mca_wakeup_ipi_wait(void)
 674 {
 675         int     irr_num = (IA64_MCA_WAKEUP_VECTOR >> 6);
 676         int     irr_bit = (IA64_MCA_WAKEUP_VECTOR & 0x3f);
 677         u64     irr = 0;
 678
 679         do {
 680                 switch(irr_num) {
 681                       case 0:
 682                         irr = ia64_getreg(_IA64_REG_CR_IRR0);
 683                         break;
 684                       case 1:
 685                         irr = ia64_getreg(_IA64_REG_CR_IRR1);
 686                         break;
 687                       case 2:
 688                         irr = ia64_getreg(_IA64_REG_CR_IRR2);
 689                         break;
 690                       case 3:
 691                         irr = ia64_getreg(_IA64_REG_CR_IRR3);
 692                         break;
 693                 }
 694         } while (!(irr & (1UL << irr_bit))) ;
 695 }
 696
 697 /*
 698  * ia64_mca_wakeup
 699  *
 700  *      Send an inter-cpu interrupt to wake-up a particular cpu
 701  *      and mark that cpu to be out of rendez.
 702  *
 703  *  Inputs  :   cpuid
 704  *  Outputs :   None
 705  */
 706 static void
 707 ia64_mca_wakeup(int cpu)
 708 {
 709         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 710         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 711
 712 }
 713
 714 /*
 715  * ia64_mca_wakeup_all
 716  *
 717  *      Wakeup all the cpus which have rendez'ed previously.
 718  *
 719  *  Inputs  :   None
 720  *  Outputs :   None
 721  */
 722 static void
 723 ia64_mca_wakeup_all(void)
 724 {
 725         int cpu;
 726
 727         /* Clear the Rendez checkin flag for all cpus */
 728         for(cpu = 0; cpu < NR_CPUS; cpu++) {
 729                 if (!cpu_online(cpu))
 730                         continue;
 731                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 732                         ia64_mca_wakeup(cpu);
 733         }
 734
 735 }
 736
 737 /*
 738  * ia64_mca_rendez_interrupt_handler
 739  *
 740  *      This is handler used to put slave processors into spinloop
 741  *      while the monarch processor does the mca handling and later
 742  *      wake each slave up once the monarch is done.
 743  *
 744  *  Inputs  :   None
 745  *  Outputs :   None
 746  */
 747 static irqreturn_t
 748 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs)
 749 {
 750         unsigned long flags;
 751         int cpu = smp_processor_id();
 752
 753         /* Mask all interrupts */
 754         local_irq_save(flags);
 755
 756         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 757         /* Register with the SAL monarch that the slave has
 758          * reached SAL
 759          */
 760         ia64_sal_mc_rendez();
 761
 762         /* Wait for the wakeup IPI from the monarch
 763          * This waiting is done by polling on the wakeup-interrupt
 764          * vector bit in the processor's IRRs
 765          */
 766         ia64_mca_wakeup_ipi_wait();
 767
 768         /* Enable all interrupts */
 769         local_irq_restore(flags);
 770         return IRQ_HANDLED;
 771 }
 772
 773 /*
 774  * ia64_mca_wakeup_int_handler
 775  *
 776  *      The interrupt handler for processing the inter-cpu interrupt to the
 777  *      slave cpu which was spinning in the rendez loop.
 778  *      Since this spinning is done by turning off the interrupts and
 779  *      polling on the wakeup-interrupt bit in the IRR, there is
 780  *      nothing useful to be done in the handler.
 781  *
 782  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 783  *      arg             (Interrupt handler specific argument)
 784  *      ptregs          (Exception frame at the time of the interrupt)
 785  *  Outputs :   None
 786  *
 787  */
 788 static irqreturn_t
 789 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
 790 {
 791         return IRQ_HANDLED;
 792 }
 793
 794 /*
 795  * ia64_return_to_sal_check
 796  *
 797  *      This is function called before going back from the OS_MCA handler
 798  *      to the OS_MCA dispatch code which finally takes the control back
 799  *      to the SAL.
 800  *      The main purpose of this routine is to setup the OS_MCA to SAL
 801  *      return state which can be used by the OS_MCA dispatch code
 802  *      just before going back to SAL.
 803  *
 804  *  Inputs  :   None
 805  *  Outputs :   None
 806  */
 807
 808 static void
 809 ia64_return_to_sal_check(int recover)
 810 {
 811
 812         /* Copy over some relevant stuff from the sal_to_os_mca_handoff
 813          * so that it can be used at the time of os_mca_to_sal_handoff
 814          */
 815         ia64_os_to_sal_handoff_state.imots_sal_gp =
 816                 ia64_sal_to_os_handoff_state.imsto_sal_gp;
 817
 818         ia64_os_to_sal_handoff_state.imots_sal_check_ra =
 819                 ia64_sal_to_os_handoff_state.imsto_sal_check_ra;
 820
 821         if (recover)
 822                 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_CORRECTED;
 823         else
 824                 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
 825
 826         /* Default = tell SAL to return to same context */
 827         ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
 828
 829         ia64_os_to_sal_handoff_state.imots_new_min_state =
 830                 (u64 *)ia64_sal_to_os_handoff_state.pal_min_state;
 831
 832 }
 833
 834 /*
 835  * ia64_mca_ucmc_handler
 836  *
 837  *      This is uncorrectable machine check handler called from OS_MCA
 838  *      dispatch code which is in turn called from SAL_CHECK().
 839  *      This is the place where the core of OS MCA handling is done.
 840  *      Right now the logs are extracted and displayed in a well-defined
 841  *      format. This handler code is supposed to be run only on the
 842  *      monarch processor. Once the monarch is done with MCA handling
 843  *      further MCA logging is enabled by clearing logs.
 844  *      Monarch also has the duty of sending wakeup-IPIs to pull the
 845  *      slave processors out of rendezvous spinloop.
 846  *
 847  *  Inputs  :   None
 848  *  Outputs :   None
 849  */
 850 void
 851 ia64_mca_ucmc_handler(void)
 852 {
 853         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
 854                 &ia64_sal_to_os_handoff_state.proc_state_param;
 855         int recover = psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc);
 856
 857         /* Get the MCA error record and log it */
 858         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
 859
 860         /*
 861          *  Wakeup all the processors which are spinning in the rendezvous
 862          *  loop.
 863          */
 864         ia64_mca_wakeup_all();
 865
 866         /* Return to SAL */
 867         ia64_return_to_sal_check(recover);
 868 }
 869
 870 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
 871 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
 872
 873 /*
 874  * ia64_mca_cmc_int_handler
 875  *
 876  *  This is corrected machine check interrupt handler.
 877  *      Right now the logs are extracted and displayed in a well-defined
 878  *      format.
 879  *
 880  * Inputs
 881  *      interrupt number
 882  *      client data arg ptr
 883  *      saved registers ptr
 884  *
 885  * Outputs
 886  *      None
 887  */
 888 static irqreturn_t
 889 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
 890 {
 891         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
 892         static int              index;
 893         static spinlock_t       cmc_history_lock = SPIN_LOCK_UNLOCKED;
 894
 895         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 896                        __FUNCTION__, cmc_irq, smp_processor_id());
 897
 898         /* SAL spec states this should run w/ interrupts enabled */
 899         local_irq_enable();
 900
 901         /* Get the CMC error record and log it */
 902         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
 903
 904         spin_lock(&cmc_history_lock);
 905         if (!cmc_polling_enabled) {
 906                 int i, count = 1; /* we know 1 happened now */
 907                 unsigned long now = jiffies;
 908
 909                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
 910                         if (now - cmc_history[i] <= HZ)
 911                                 count++;
 912                 }
 913
 914                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
 915                 if (count >= CMC_HISTORY_LENGTH) {
 916
 917                         cmc_polling_enabled = 1;
 918                         spin_unlock(&cmc_history_lock);
 919                         schedule_work(&cmc_disable_work);
 920
 921                         /*
 922                          * Corrected errors will still be corrected, but
 923                          * make sure there's a log somewhere that indicates
 924                          * something is generating more than we can handle.
 925                          */
 926                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
 927
 928                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
 929
 930                         /* lock already released, get out now */
 931                         return IRQ_HANDLED;
 932                 } else {
 933                         cmc_history[index++] = now;
 934                         if (index == CMC_HISTORY_LENGTH)
 935                                 index = 0;
 936                 }
 937         }
 938         spin_unlock(&cmc_history_lock);
 939         return IRQ_HANDLED;
 940 }
 941
 942 /*
 943  *  ia64_mca_cmc_int_caller
 944  *
 945  *      Triggered by sw interrupt from CMC polling routine.  Calls
 946  *      real interrupt handler and either triggers a sw interrupt
 947  *      on the next cpu or does cleanup at the end.
 948  *
 949  * Inputs
 950  *      interrupt number
 951  *      client data arg ptr
 952  *      saved registers ptr
 953  * Outputs
 954  *      handled
 955  */
 956 static irqreturn_t
 957 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
 958 {
 959         static int start_count = -1;
 960         unsigned int cpuid;
 961
 962         cpuid = smp_processor_id();
 963
 964         /* If first cpu, update count */
 965         if (start_count == -1)
 966                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
 967
 968         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
 969
 970         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
 971
 972         if (cpuid < NR_CPUS) {
 973                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
 974         } else {
 975                 /* If no log record, switch out of polling mode */
 976                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
 977
 978                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
 979                         schedule_work(&cmc_enable_work);
 980                         cmc_polling_enabled = 0;
 981
 982                 } else {
 983
 984                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
 985                 }
 986
 987                 start_count = -1;
 988         }
 989
 990         return IRQ_HANDLED;
 991 }
 992
 993 /*
 994  *  ia64_mca_cmc_poll
 995  *
 996  *      Poll for Corrected Machine Checks (CMCs)
 997  *
 998  * Inputs   :   dummy(unused)
 999  * Outputs  :   None
1000  *
1001  */
1002 static void
1003 ia64_mca_cmc_poll (unsigned long dummy)
1004 {
1005         /* Trigger a CMC interrupt cascade  */
1006         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1007 }
1008
1009 /*
1010  *  ia64_mca_cpe_int_caller
1011  *
1012  *      Triggered by sw interrupt from CPE polling routine.  Calls
1013  *      real interrupt handler and either triggers a sw interrupt
1014  *      on the next cpu or does cleanup at the end.
1015  *
1016  * Inputs
1017  *      interrupt number
1018  *      client data arg ptr
1019  *      saved registers ptr
1020  * Outputs
1021  *      handled
1022  */
1023 #ifdef CONFIG_ACPI
1024
1025 static irqreturn_t
1026 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1027 {
1028         static int start_count = -1;
1029         static int poll_time = MIN_CPE_POLL_INTERVAL;
1030         unsigned int cpuid;
1031
1032         cpuid = smp_processor_id();
1033
1034         /* If first cpu, update count */
1035         if (start_count == -1)
1036                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1037
1038         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1039
1040         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1041
1042         if (cpuid < NR_CPUS) {
1043                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1044         } else {
1045                 /*
1046                  * If a log was recorded, increase our polling frequency,
1047                  * otherwise, backoff or return to interrupt mode.
1048                  */
1049                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1050                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1051                 } else if (cpe_vector < 0) {
1052                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1053                 } else {
1054                         poll_time = MIN_CPE_POLL_INTERVAL;
1055
1056                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1057                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1058                         cpe_poll_enabled = 0;
1059                 }
1060
1061                 if (cpe_poll_enabled)
1062                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1063                 start_count = -1;
1064         }
1065
1066         return IRQ_HANDLED;
1067 }
1068
1069 #endif /* CONFIG_ACPI */
1070
1071 /*
1072  *  ia64_mca_cpe_poll
1073  *
1074  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1075  *      on first cpu, from there it will trickle through all the cpus.
1076  *
1077  * Inputs   :   dummy(unused)
1078  * Outputs  :   None
1079  *
1080  */
1081 static void
1082 ia64_mca_cpe_poll (unsigned long dummy)
1083 {
1084         /* Trigger a CPE interrupt cascade  */
1085         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1086 }
1087
1088 /*
1089  * C portion of the OS INIT handler
1090  *
1091  * Called from ia64_monarch_init_handler
1092  *
1093  * Inputs: pointer to pt_regs where processor info was saved.
1094  *
1095  * Returns:
1096  *   0 if SAL must warm boot the System
1097  *   1 if SAL must return to interrupted context using PAL_MC_RESUME
1098  *
1099  */
1100 void
1101 ia64_init_handler (struct pt_regs *pt, struct switch_stack *sw)
1102 {
1103         pal_min_state_area_t *ms;
1104
1105         oops_in_progress = 1;   /* avoid deadlock in printk, but it makes recovery dodgy */
1106
1107         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx\n",
1108                 ia64_sal_to_os_handoff_state.proc_state_param);
1109
1110         /*
1111          * Address of minstate area provided by PAL is physical,
1112          * uncacheable (bit 63 set). Convert to Linux virtual
1113          * address in region 6.
1114          */
1115         ms = (pal_min_state_area_t *)(ia64_sal_to_os_handoff_state.pal_min_state | (6ul<<61));
1116
1117         init_handler_platform(ms, pt, sw);      /* call platform specific routines */
1118 }
1119
1120 static int __init
1121 ia64_mca_disable_cpe_polling(char *str)
1122 {
1123         cpe_poll_enabled = 0;
1124         return 1;
1125 }
1126
1127 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1128
1129 static struct irqaction cmci_irqaction = {
1130         .handler =      ia64_mca_cmc_int_handler,
1131         .flags =        SA_INTERRUPT,
1132         .name =         "cmc_hndlr"
1133 };
1134
1135 static struct irqaction cmcp_irqaction = {
1136         .handler =      ia64_mca_cmc_int_caller,
1137         .flags =        SA_INTERRUPT,
1138         .name =         "cmc_poll"
1139 };
1140
1141 static struct irqaction mca_rdzv_irqaction = {
1142         .handler =      ia64_mca_rendez_int_handler,
1143         .flags =        SA_INTERRUPT,
1144         .name =         "mca_rdzv"
1145 };
1146
1147 static struct irqaction mca_wkup_irqaction = {
1148         .handler =      ia64_mca_wakeup_int_handler,
1149         .flags =        SA_INTERRUPT,
1150         .name =         "mca_wkup"
1151 };
1152
1153 #ifdef CONFIG_ACPI
1154 static struct irqaction mca_cpe_irqaction = {
1155         .handler =      ia64_mca_cpe_int_handler,
1156         .flags =        SA_INTERRUPT,
1157         .name =         "cpe_hndlr"
1158 };
1159
1160 static struct irqaction mca_cpep_irqaction = {
1161         .handler =      ia64_mca_cpe_int_caller,
1162         .flags =        SA_INTERRUPT,
1163         .name =         "cpe_poll"
1164 };
1165 #endif /* CONFIG_ACPI */
1166
1167 /*
1168  * ia64_mca_init
1169  *
1170  *  Do all the system level mca specific initialization.
1171  *
1172  *      1. Register spinloop and wakeup request interrupt vectors
1173  *
1174  *      2. Register OS_MCA handler entry point
1175  *
1176  *      3. Register OS_INIT handler entry point
1177  *
1178  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1179  *
1180  *  Note that this initialization is done very early before some kernel
1181  *  services are available.
1182  *
1183  *  Inputs  :   None
1184  *
1185  *  Outputs :   None
1186  */
1187 void __init
1188 ia64_mca_init(void)
1189 {
1190         ia64_fptr_t *mon_init_ptr = (ia64_fptr_t *)ia64_monarch_init_handler;
1191         ia64_fptr_t *slave_init_ptr = (ia64_fptr_t *)ia64_slave_init_handler;
1192         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1193         int i;
1194         s64 rc;
1195         struct ia64_sal_retval isrv;
1196         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1197
1198         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1199
1200         /* Clear the Rendez checkin flag for all cpus */
1201         for(i = 0 ; i < NR_CPUS; i++)
1202                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1203
1204         /*
1205          * Register the rendezvous spinloop and wakeup mechanism with SAL
1206          */
1207
1208         /* Register the rendezvous interrupt vector with SAL */
1209         while (1) {
1210                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1211                                               SAL_MC_PARAM_MECHANISM_INT,
1212                                               IA64_MCA_RENDEZ_VECTOR,
1213                                               timeout,
1214                                               SAL_MC_PARAM_RZ_ALWAYS);
1215                 rc = isrv.status;
1216                 if (rc == 0)
1217                         break;
1218                 if (rc == -2) {
1219                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1220                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1221                         timeout = isrv.v0;
1222                         continue;
1223                 }
1224                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1225                        "with SAL (status %ld)\n", rc);
1226                 return;
1227         }
1228
1229         /* Register the wakeup interrupt vector with SAL */
1230         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1231                                       SAL_MC_PARAM_MECHANISM_INT,
1232                                       IA64_MCA_WAKEUP_VECTOR,
1233                                       0, 0);
1234         rc = isrv.status;
1235         if (rc) {
1236                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1237                        "(status %ld)\n", rc);
1238                 return;
1239         }
1240
1241         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1242
1243         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1244         /*
1245          * XXX - disable SAL checksum by setting size to 0; should be
1246          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1247          */
1248         ia64_mc_info.imi_mca_handler_size       = 0;
1249
1250         /* Register the os mca handler with SAL */
1251         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1252                                        ia64_mc_info.imi_mca_handler,
1253                                        ia64_tpa(mca_hldlr_ptr->gp),
1254                                        ia64_mc_info.imi_mca_handler_size,
1255                                        0, 0, 0)))
1256         {
1257                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1258                        "(status %ld)\n", rc);
1259                 return;
1260         }
1261
1262         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1263                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1264
1265         /*
1266          * XXX - disable SAL checksum by setting size to 0, should be
1267          * size of the actual init handler in mca_asm.S.
1268          */
1269         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(mon_init_ptr->fp);
1270         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1271         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(slave_init_ptr->fp);
1272         ia64_mc_info.imi_slave_init_handler_size        = 0;
1273
1274         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1275                        ia64_mc_info.imi_monarch_init_handler);
1276
1277         /* Register the os init handler with SAL */
1278         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1279                                        ia64_mc_info.imi_monarch_init_handler,
1280                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1281                                        ia64_mc_info.imi_monarch_init_handler_size,
1282                                        ia64_mc_info.imi_slave_init_handler,
1283                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1284                                        ia64_mc_info.imi_slave_init_handler_size)))
1285         {
1286                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1287                        "(status %ld)\n", rc);
1288                 return;
1289         }
1290
1291         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1292
1293         /*
1294          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1295          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1296          */
1297         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1298         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1299         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1300
1301         /* Setup the MCA rendezvous interrupt vector */
1302         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1303
1304         /* Setup the MCA wakeup interrupt vector */
1305         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1306
1307 #ifdef CONFIG_ACPI
1308         /* Setup the CPEI/P vector and handler */
1309         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1310         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1311 #endif
1312
1313         /* Initialize the areas set aside by the OS to buffer the
1314          * platform/processor error states for MCA/INIT/CMC
1315          * handling.
1316          */
1317         ia64_log_init(SAL_INFO_TYPE_MCA);
1318         ia64_log_init(SAL_INFO_TYPE_INIT);
1319         ia64_log_init(SAL_INFO_TYPE_CMC);
1320         ia64_log_init(SAL_INFO_TYPE_CPE);
1321
1322         mca_init = 1;
1323         printk(KERN_INFO "MCA related initialization done\n");
1324 }
1325
1326 /*
1327  * ia64_mca_late_init
1328  *
1329  *      Opportunity to setup things that require initialization later
1330  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1331  *      platform doesn't support an interrupt driven mechanism.
1332  *
1333  *  Inputs  :   None
1334  *  Outputs :   Status
1335  */
1336 static int __init
1337 ia64_mca_late_init(void)
1338 {
1339         if (!mca_init)
1340                 return 0;
1341
1342         /* Setup the CMCI/P vector and handler */
1343         init_timer(&cmc_poll_timer);
1344         cmc_poll_timer.function = ia64_mca_cmc_poll;
1345
1346         /* Unmask/enable the vector */
1347         cmc_polling_enabled = 0;
1348         schedule_work(&cmc_enable_work);
1349
1350         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1351
1352 #ifdef CONFIG_ACPI
1353         /* Setup the CPEI/P vector and handler */
1354         init_timer(&cpe_poll_timer);
1355         cpe_poll_timer.function = ia64_mca_cpe_poll;
1356
1357         {
1358                 irq_desc_t *desc;
1359                 unsigned int irq;
1360
1361                 if (cpe_vector >= 0) {
1362                         /* If platform supports CPEI, enable the irq. */
1363                         cpe_poll_enabled = 0;
1364                         for (irq = 0; irq < NR_IRQS; ++irq)
1365                                 if (irq_to_vector(irq) == cpe_vector) {
1366                                         desc = irq_descp(irq);
1367                                         desc->status |= IRQ_PER_CPU;
1368                                         setup_irq(irq, &mca_cpe_irqaction);
1369                                 }
1370                         ia64_mca_register_cpev(cpe_vector);
1371                         IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1372                 } else {
1373                         /* If platform doesn't support CPEI, get the timer going. */
1374                         if (cpe_poll_enabled) {
1375                                 ia64_mca_cpe_poll(0UL);
1376                                 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1377                         }
1378                 }
1379         }
1380 #endif
1381
1382         return 0;
1383 }
1384
1385 device_initcall(ia64_mca_late_init);