arch/ia64/kernel/minstate.h

   1 #include <linux/config.h>
   2
   3 #include <asm/cache.h>
   4
   5 #include "entry.h"
   6
   7 /*
   8  * For ivt.s we want to access the stack virtually so we don't have to disable translation
   9  * on interrupts.
  10  *
  11  *  On entry:
  12  *      r1:     pointer to current task (ar.k6)
  13  */
  14 #define MINSTATE_START_SAVE_MIN_VIRT                                                            \
  15 (pUStk) mov ar.rsc=0;           /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */     \
  16         ;;                                                                                      \
  17 (pUStk) mov.m r24=ar.rnat;                                                                      \
  18 (pUStk) addl r22=IA64_RBS_OFFSET,r1;                    /* compute base of RBS */               \
  19 (pKStk) mov r1=sp;                                      /* get sp  */                           \
  20         ;;                                                                                      \
  21 (pUStk) lfetch.fault.excl.nt1 [r22];                                                            \
  22 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1;   /* compute base of memory stack */      \
  23 (pUStk) mov r23=ar.bspstore;                            /* save ar.bspstore */                  \
  24         ;;                                                                                      \
  25 (pUStk) mov ar.bspstore=r22;                            /* switch to kernel RBS */              \
  26 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1;                  /* if in kernel mode, use sp (r12) */   \
  27         ;;                                                                                      \
  28 (pUStk) mov r18=ar.bsp;                                                                         \
  29 (pUStk) mov ar.rsc=0x3;         /* set eager mode, pl 0, little-endian, loadrs=0 */             \
  30
  31 #define MINSTATE_END_SAVE_MIN_VIRT                                                              \
  32         bsw.1;                  /* switch back to bank 1 (must be last in insn group) */        \
  33         ;;
  34
  35 /*
  36  * For mca_asm.S we want to access the stack physically since the state is saved before we
  37  * go virtual and don't want to destroy the iip or ipsr.
  38  */
  39 #define MINSTATE_START_SAVE_MIN_PHYS                                                            \
  40 (pKStk) movl sp=ia64_init_stack+IA64_STK_OFFSET-IA64_PT_REGS_SIZE;                              \
  41 (pUStk) mov ar.rsc=0;           /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */     \
  42 (pUStk) addl r22=IA64_RBS_OFFSET,r1;            /* compute base of register backing store */    \
  43         ;;                                                                                      \
  44 (pUStk) mov r24=ar.rnat;                                                                        \
  45 (pKStk) tpa r1=sp;                              /* compute physical addr of sp  */              \
  46 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1;   /* compute base of memory stack */      \
  47 (pUStk) mov r23=ar.bspstore;                            /* save ar.bspstore */                  \
  48 (pUStk) dep r22=-1,r22,61,3;                    /* compute kernel virtual addr of RBS */        \
  49         ;;                                                                                      \
  50 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1;          /* if in kernel mode, use sp (r12) */           \
  51 (pUStk) mov ar.bspstore=r22;                    /* switch to kernel RBS */                      \
  52         ;;                                                                                      \
  53 (pUStk) mov r18=ar.bsp;                                                                         \
  54 (pUStk) mov ar.rsc=0x3;         /* set eager mode, pl 0, little-endian, loadrs=0 */             \
  55
  56 #define MINSTATE_END_SAVE_MIN_PHYS                                                              \
  57         dep r12=-1,r12,61,3;            /* make sp a kernel virtual address */                  \
  58         ;;
  59
  60 #ifdef MINSTATE_VIRT
  61 # define MINSTATE_GET_CURRENT(reg)      mov reg=IA64_KR(CURRENT)
  62 # define MINSTATE_START_SAVE_MIN        MINSTATE_START_SAVE_MIN_VIRT
  63 # define MINSTATE_END_SAVE_MIN          MINSTATE_END_SAVE_MIN_VIRT
  64 #endif
  65
  66 #ifdef MINSTATE_PHYS
  67 # define MINSTATE_GET_CURRENT(reg)      mov reg=IA64_KR(CURRENT);; tpa reg=reg
  68 # define MINSTATE_START_SAVE_MIN        MINSTATE_START_SAVE_MIN_PHYS
  69 # define MINSTATE_END_SAVE_MIN          MINSTATE_END_SAVE_MIN_PHYS
  70 #endif
  71
  72 /*
  73  * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
  74  * the minimum state necessary that allows us to turn psr.ic back
  75  * on.
  76  *
  77  * Assumed state upon entry:
  78  *      psr.ic: off
  79  *      r31:    contains saved predicates (pr)
  80  *
  81  * Upon exit, the state is as follows:
  82  *      psr.ic: off
  83  *       r2 = points to &pt_regs.r16
  84  *       r8 = contents of ar.ccv
  85  *       r9 = contents of ar.csd
  86  *      r10 = contents of ar.ssd
  87  *      r11 = FPSR_DEFAULT
  88  *      r12 = kernel sp (kernel virtual address)
  89  *      r13 = points to current task_struct (kernel virtual address)
  90  *      p15 = TRUE if psr.i is set in cr.ipsr
  91  *      predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
  92  *              preserved
  93  *
  94  * Note that psr.ic is NOT turned on by this macro.  This is so that
  95  * we can pass interruption state as arguments to a handler.
  96  */
  97 #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA)                                                       \
  98         MINSTATE_GET_CURRENT(r16);      /* M (or M;;I) */                                       \
  99         mov r27=ar.rsc;                 /* M */                                                 \
 100         mov r20=r1;                     /* A */                                                 \
 101         mov r25=ar.unat;                /* M */                                                 \
 102         mov r29=cr.ipsr;                /* M */                                                 \
 103         mov r26=ar.pfs;                 /* I */                                                 \
 104         mov r28=cr.iip;                 /* M */                                                 \
 105         mov r21=ar.fpsr;                /* M */                                                 \
 106         COVER;                          /* B;; (or nothing) */                                  \
 107         ;;                                                                                      \
 108         adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16;                                         \
 109         ;;                                                                                      \
 110         ld1 r17=[r16];                          /* load current->thread.on_ustack flag */       \
 111         st1 [r16]=r0;                           /* clear current->thread.on_ustack flag */      \
 112         adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16                                          \
 113         /* switch from user to kernel RBS: */                                                   \
 114         ;;                                                                                      \
 115         invala;                         /* M */                                                 \
 116         SAVE_IFS;                                                                               \
 117         cmp.eq pKStk,pUStk=r0,r17;              /* are we in kernel mode already? */            \
 118         ;;                                                                                      \
 119         MINSTATE_START_SAVE_MIN                                                                 \
 120         adds r17=2*L1_CACHE_BYTES,r1;           /* really: biggest cache-line size */           \
 121         adds r16=PT(CR_IPSR),r1;                                                                \
 122         ;;                                                                                      \
 123         lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES;                                             \
 124         st8 [r16]=r29;          /* save cr.ipsr */                                              \
 125         ;;                                                                                      \
 126         lfetch.fault.excl.nt1 [r17];                                                            \
 127         tbit.nz p15,p0=r29,IA64_PSR_I_BIT;                                                      \
 128         mov r29=b0                                                                              \
 129         ;;                                                                                      \
 130         adds r16=PT(R8),r1;     /* initialize first base pointer */                             \
 131         adds r17=PT(R9),r1;     /* initialize second base pointer */                            \
 132 (pKStk) mov r18=r0;             /* make sure r18 isn't NaT */                                   \
 133         ;;                                                                                      \
 134 .mem.offset 0,0; st8.spill [r16]=r8,16;                                                         \
 135 .mem.offset 8,0; st8.spill [r17]=r9,16;                                                         \
 136         ;;                                                                                      \
 137 .mem.offset 0,0; st8.spill [r16]=r10,24;                                                        \
 138 .mem.offset 8,0; st8.spill [r17]=r11,24;                                                        \
 139         ;;                                                                                      \
 140         st8 [r16]=r28,16;       /* save cr.iip */                                               \
 141         st8 [r17]=r30,16;       /* save cr.ifs */                                               \
 142 (pUStk) sub r18=r18,r22;        /* r18=RSE.ndirty*8 */                                          \
 143         mov r8=ar.ccv;                                                                          \
 144         mov r9=ar.csd;                                                                          \
 145         mov r10=ar.ssd;                                                                         \
 146         movl r11=FPSR_DEFAULT;   /* L-unit */                                                   \
 147         ;;                                                                                      \
 148         st8 [r16]=r25,16;       /* save ar.unat */                                              \
 149         st8 [r17]=r26,16;       /* save ar.pfs */                                               \
 150         shl r18=r18,16;         /* compute ar.rsc to be used for "loadrs" */                    \
 151         ;;                                                                                      \
 152         st8 [r16]=r27,16;       /* save ar.rsc */                                               \
 153 (pUStk) st8 [r17]=r24,16;       /* save ar.rnat */                                              \
 154 (pKStk) adds r17=16,r17;        /* skip over ar_rnat field */                                   \
 155         ;;                      /* avoid RAW on r16 & r17 */                                    \
 156 (pUStk) st8 [r16]=r23,16;       /* save ar.bspstore */                                          \
 157         st8 [r17]=r31,16;       /* save predicates */                                           \
 158 (pKStk) adds r16=16,r16;        /* skip over ar_bspstore field */                               \
 159         ;;                                                                                      \
 160         st8 [r16]=r29,16;       /* save b0 */                                                   \
 161         st8 [r17]=r18,16;       /* save ar.rsc value for "loadrs" */                            \
 162         cmp.eq pNonSys,pSys=r0,r0       /* initialize pSys=0, pNonSys=1 */                      \
 163         ;;                                                                                      \
 164 .mem.offset 0,0; st8.spill [r16]=r20,16;        /* save original r1 */                          \
 165 .mem.offset 8,0; st8.spill [r17]=r12,16;                                                        \
 166         adds r12=-16,r1;        /* switch to kernel memory stack (with 16 bytes of scratch) */  \
 167         ;;                                                                                      \
 168 .mem.offset 0,0; st8.spill [r16]=r13,16;                                                        \
 169 .mem.offset 8,0; st8.spill [r17]=r21,16;        /* save ar.fpsr */                              \
 170         mov r13=IA64_KR(CURRENT);       /* establish `current' */                               \
 171         ;;                                                                                      \
 172 .mem.offset 0,0; st8.spill [r16]=r15,16;                                                        \
 173 .mem.offset 8,0; st8.spill [r17]=r14,16;                                                        \
 174         ;;                                                                                      \
 175 .mem.offset 0,0; st8.spill [r16]=r2,16;                                                         \
 176 .mem.offset 8,0; st8.spill [r17]=r3,16;                                                         \
 177         adds r2=IA64_PT_REGS_R16_OFFSET,r1;                                                     \
 178         ;;                                                                                      \
 179         EXTRA;                                                                                  \
 180         movl r1=__gp;           /* establish kernel global pointer */                           \
 181         ;;                                                                                      \
 182         MINSTATE_END_SAVE_MIN
 183
 184 /*
 185  * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
 186  *
 187  * Assumed state upon entry:
 188  *      psr.ic: on
 189  *      r2:     points to &pt_regs.r16
 190  *      r3:     points to &pt_regs.r17
 191  *      r8:     contents of ar.ccv
 192  *      r9:     contents of ar.csd
 193  *      r10:    contents of ar.ssd
 194  *      r11:    FPSR_DEFAULT
 195  *
 196  * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
 197  */
 198 #define SAVE_REST                               \
 199 .mem.offset 0,0; st8.spill [r2]=r16,16;         \
 200 .mem.offset 8,0; st8.spill [r3]=r17,16;         \
 201         ;;                                      \
 202 .mem.offset 0,0; st8.spill [r2]=r18,16;         \
 203 .mem.offset 8,0; st8.spill [r3]=r19,16;         \
 204         ;;                                      \
 205 .mem.offset 0,0; st8.spill [r2]=r20,16;         \
 206 .mem.offset 8,0; st8.spill [r3]=r21,16;         \
 207         mov r18=b6;                             \
 208         ;;                                      \
 209 .mem.offset 0,0; st8.spill [r2]=r22,16;         \
 210 .mem.offset 8,0; st8.spill [r3]=r23,16;         \
 211         mov r19=b7;                             \
 212         ;;                                      \
 213 .mem.offset 0,0; st8.spill [r2]=r24,16;         \
 214 .mem.offset 8,0; st8.spill [r3]=r25,16;         \
 215         ;;                                      \
 216 .mem.offset 0,0; st8.spill [r2]=r26,16;         \
 217 .mem.offset 8,0; st8.spill [r3]=r27,16;         \
 218         ;;                                      \
 219 .mem.offset 0,0; st8.spill [r2]=r28,16;         \
 220 .mem.offset 8,0; st8.spill [r3]=r29,16;         \
 221         ;;                                      \
 222 .mem.offset 0,0; st8.spill [r2]=r30,16;         \
 223 .mem.offset 8,0; st8.spill [r3]=r31,32;         \
 224         ;;                                      \
 225         mov ar.fpsr=r11;        /* M-unit */    \
 226         st8 [r2]=r8,8;          /* ar.ccv */    \
 227         adds r24=PT(B6)-PT(F7),r3;              \
 228         ;;                                      \
 229         stf.spill [r2]=f6,32;                   \
 230         stf.spill [r3]=f7,32;                   \
 231         ;;                                      \
 232         stf.spill [r2]=f8,32;                   \
 233         stf.spill [r3]=f9,32;                   \
 234         ;;                                      \
 235         stf.spill [r2]=f10;                     \
 236         stf.spill [r3]=f11;                     \
 237         adds r25=PT(B7)-PT(F11),r3;             \
 238         ;;                                      \
 239         st8 [r24]=r18,16;       /* b6 */        \
 240         st8 [r25]=r19,16;       /* b7 */        \
 241         ;;                                      \
 242         st8 [r24]=r9;           /* ar.csd */    \
 243         st8 [r25]=r10;          /* ar.ssd */    \
 244         ;;
 245
 246 #define SAVE_MIN_WITH_COVER     DO_SAVE_MIN(cover, mov r30=cr.ifs,)
 247 #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19)
 248 #define SAVE_MIN                DO_SAVE_MIN(     , mov r30=r0, )