4 * Copyright (C) 2005 Hewlett-Packard Co
5 * Dan Magenheimer <dan.magenheimer@hp.com>
8 * This file defines the interruption vector table used by the CPU.
9 * It does not include one entry per possible cause of interruption.
11 * The first 20 entries of the table contain 64 bundles each while the
12 * remaining 48 entries contain only 16 bundles each.
14 * The 64 bundles are used to allow inlining the whole handler for critical
15 * interruptions like TLB misses.
17 * For each entry, the comment is as follows:
19 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
20 * entry offset ----/ / / / /
21 * entry number ---------/ / / /
22 * size of the entry -------------/ / /
23 * vector name -------------------------------------/ /
24 * interruptions triggering this vector ----------------------/
26 * The table is 32KB in size and must be aligned on 32KB boundary.
27 * (The CPU ignores the 15 lower bits of the address)
29 * Table is based upon EAS2.6 (Oct 1999)
32 #include <asm/asmmacro.h>
33 #include <asm/break.h>
35 #include <asm/kregs.h>
36 #include <asm/asm-offsets.h>
37 #include <asm/pgtable.h>
38 #include <asm/processor.h>
39 #include <asm/ptrace.h>
40 #include <asm/system.h>
41 #include <asm/thread_info.h>
42 #include <asm/unistd.h>
43 #include <asm/errno.h>
46 #define ia64_ivt xen_ivt
50 # define PSR_DEFAULT_BITS psr.ac
52 # define PSR_DEFAULT_BITS 0
57 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
58 * needed for something else before enabling this...
60 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
65 #define MINSTATE_VIRT /* needed by minstate.h */
66 #include "xenminstate.h"
70 mov r19=n;; /* prepare to save predicates */ \
71 br.sptk.many dispatch_to_fault_handler
73 .section .text.ivt,"ax"
75 .align 32768 // align on 32KB boundary
78 /////////////////////////////////////////////////////////////////////////////////////////
79 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
83 * The VHPT vector is invoked when the TLB entry for the virtual page table
84 * is missing. This happens only as a result of a previous
85 * (the "original") TLB miss, which may either be caused by an instruction
86 * fetch or a data access (or non-access).
88 * What we do here is normal TLB miss handing for the _original_ miss,
89 * followed by inserting the TLB entry for the virtual page table page
90 * that the VHPT walker was attempting to access. The latter gets
91 * inserted as long as page table entry above pte level have valid
92 * mappings for the faulting address. The TLB entry for the original
93 * miss gets inserted only if the pte entry indicates that the page is
96 * do_page_fault gets invoked in the following cases:
97 * - the faulting virtual address uses unimplemented address bits
98 * - the faulting virtual address has no valid page table mapping
104 #ifdef CONFIG_HUGETLB_PAGE
112 mov r16=cr.ifa // get address that caused the TLB miss
113 #ifdef CONFIG_HUGETLB_PAGE
120 XEN_HYPER_RSM_PSR_DT;
122 rsm psr.dt // use physical addressing for data
124 mov r31=pr // save the predicate registers
125 mov r19=IA64_KR(PT_BASE) // get page table base address
126 shl r21=r16,3 // shift bit 60 into sign bit
127 shr.u r17=r16,61 // get the region number into r17
130 #ifdef CONFIG_HUGETLB_PAGE
136 (p8) dep r25=r18,r25,2,6
140 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
141 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
143 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
146 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
148 .pred.rel "mutex", p6, p7
149 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
150 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
152 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
153 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
154 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
155 #ifdef CONFIG_PGTABLE_4
156 shr.u r28=r22,PUD_SHIFT // shift pud index into position
158 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
161 ld8 r17=[r17] // get *pgd (may be 0)
163 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
164 #ifdef CONFIG_PGTABLE_4
165 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
167 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
168 (p7) ld8 r29=[r28] // get *pud (may be 0)
170 (p7) cmp.eq.or.andcm p6,p7=r29,r0 // was pud_present(*pud) == NULL?
171 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
173 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
176 (p7) ld8 r20=[r17] // get *pmd (may be 0)
177 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
179 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL?
180 dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr)
182 (p7) ld8 r18=[r21] // read *pte
188 mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss
191 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
197 mov r22=cr.iha // get the VHPT address that caused the TLB miss
199 ;; // avoid RAW on p7
200 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
201 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
207 (p10) XEN_HYPER_ITC_I
209 (p11) XEN_HYPER_ITC_D
214 (p10) itc.i r18 // insert the instruction TLB entry
215 (p11) itc.d r18 // insert the data TLB entry
217 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
227 #ifdef CONFIG_HUGETLB_PAGE
228 (p8) mov cr.itir=r25 // change to default page-size for VHPT
232 * Now compute and insert the TLB entry for the virtual page table. We never
233 * execute in a page table page so there is no need to set the exception deferral
236 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
252 * Tell the assemblers dependency-violation checker that the above "itc" instructions
253 * cannot possibly affect the following loads:
258 * Re-check pagetable entry. If they changed, we may have received a ptc.g
259 * between reading the pagetable and the "itc". If so, flush the entry we
260 * inserted and retry. At this point, we have:
262 * r28 = equivalent of pud_offset(pgd, ifa)
263 * r17 = equivalent of pmd_offset(pud, ifa)
264 * r21 = equivalent of pte_offset(pmd, ifa)
270 ld8 r25=[r21] // read *pte again
271 ld8 r26=[r17] // read *pmd again
272 #ifdef CONFIG_PGTABLE_4
273 ld8 r19=[r28] // read *pud again
277 cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change
278 #ifdef CONFIG_PGTABLE_4
279 cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change
281 mov r27=PAGE_SHIFT<<2
283 (p6) ptc.l r22,r27 // purge PTE page translation
284 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
286 (p6) ptc.l r16,r27 // purge translation
289 mov pr=r31,-1 // restore predicate registers
299 /////////////////////////////////////////////////////////////////////////////////////////
300 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
304 * The ITLB handler accesses the PTE via the virtually mapped linear
305 * page table. If a nested TLB miss occurs, we switch into physical
306 * mode, walk the page table, and then re-execute the PTE read and
307 * go on normally after that.
314 mov r16=cr.ifa // get virtual address
316 mov r29=b0 // save b0
317 mov r31=pr // save predicates
322 ld8 r17=[r17] // get virtual address of L3 PTE
324 mov r17=cr.iha // get virtual address of PTE
326 movl r30=1f // load nested fault continuation point
328 1: ld8 r18=[r17] // read *pte
331 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
332 (p6) br.cond.spnt page_fault
347 * Tell the assemblers dependency-violation checker that the above "itc" instructions
348 * cannot possibly affect the following loads:
352 ld8 r19=[r17] // read *pte again and see if same
353 mov r20=PAGE_SHIFT<<2 // setup page size for purge
369 /////////////////////////////////////////////////////////////////////////////////////////
370 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
374 * The DTLB handler accesses the PTE via the virtually mapped linear
375 * page table. If a nested TLB miss occurs, we switch into physical
376 * mode, walk the page table, and then re-execute the PTE read and
377 * go on normally after that.
384 mov r16=cr.ifa // get virtual address
386 mov r29=b0 // save b0
387 mov r31=pr // save predicates
392 ld8 r17=[r17] // get virtual address of L3 PTE
394 mov r17=cr.iha // get virtual address of PTE
396 movl r30=1f // load nested fault continuation point
398 1: ld8 r18=[r17] // read *pte
401 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
402 (p6) br.cond.spnt page_fault
418 * Tell the assemblers dependency-violation checker that the above "itc" instructions
419 * cannot possibly affect the following loads:
423 ld8 r19=[r17] // read *pte again and see if same
424 mov r20=PAGE_SHIFT<<2 // setup page size for purge
440 /////////////////////////////////////////////////////////////////////////////////////////
441 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
447 ld8 r21=[r31],XSI_IFA_OFS-XSI_IPSR_OFS // get ipsr, point to ifa
450 ld8 r16=[r31] // get ifa
452 mov r16=cr.ifa // get address that caused the TLB miss
456 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
459 #ifdef CONFIG_DISABLE_VHPT
460 shr.u r22=r16,61 // get the region number into r21
462 cmp.gt p8,p0=6,r22 // user mode
469 (p8) mov r29=b0 // save b0
470 (p8) br.cond.dptk .itlb_fault
472 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
473 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
474 shr.u r18=r16,57 // move address bit 61 to bit 4
476 andcm r18=0x10,r18 // bit 4=~address-bit(61)
477 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
478 or r19=r17,r19 // insert PTE control bits into r19
480 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
481 (p8) br.cond.spnt page_fault
495 itc.i r19 // insert the TLB entry
502 /////////////////////////////////////////////////////////////////////////////////////////
503 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
509 ld8 r21=[r31],XSI_ISR_OFS-XSI_IPSR_OFS // get ipsr, point to isr
512 ld8 r20=[r31],XSI_IFA_OFS-XSI_ISR_OFS // get isr, point to ifa
513 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
515 ld8 r16=[r31] // get ifa
517 mov r16=cr.ifa // get address that caused the TLB miss
520 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
525 #ifdef CONFIG_DISABLE_VHPT
526 shr.u r22=r16,61 // get the region number into r21
528 cmp.gt p8,p0=6,r22 // access to region 0-5
535 (p8) mov r29=b0 // save b0
536 (p8) br.cond.dptk dtlb_fault
538 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
539 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
540 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
541 shr.u r18=r16,57 // move address bit 61 to bit 4
542 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
543 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
545 andcm r18=0x10,r18 // bit 4=~address-bit(61)
547 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
548 (p8) br.cond.spnt page_fault
550 dep r21=-1,r21,IA64_PSR_ED_BIT,1
551 or r19=r19,r17 // insert PTE control bits into r19
553 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
568 (p7) itc.d r19 // insert the TLB entry
575 /////////////////////////////////////////////////////////////////////////////////////////
576 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
577 ENTRY(nested_dtlb_miss)
579 * In the absence of kernel bugs, we get here when the virtually mapped linear
580 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
581 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
582 * table is missing, a nested TLB miss fault is triggered and control is
583 * transferred to this point. When this happens, we lookup the pte for the
584 * faulting address by walking the page table in physical mode and return to the
585 * continuation point passed in register r30 (or call page_fault if the address is
588 * Input: r16: faulting address
590 * r30: continuation address
593 * Output: r17: physical address of PTE of faulting address
595 * r30: continuation address
598 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared)
601 XEN_HYPER_RSM_PSR_DT;
603 rsm psr.dt // switch to using physical data addressing
605 mov r19=IA64_KR(PT_BASE) // get the page table base address
606 shl r21=r16,3 // shift bit 60 into sign bit
615 shr.u r17=r16,61 // get the region number into r17
616 extr.u r18=r18,2,6 // get the faulting page size
618 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
619 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
620 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
624 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
627 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
629 .pred.rel "mutex", p6, p7
630 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
631 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
633 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
634 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
635 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
636 #ifdef CONFIG_PGTABLE_4
637 shr.u r18=r22,PUD_SHIFT // shift pud index into position
639 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
642 ld8 r17=[r17] // get *pgd (may be 0)
644 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
645 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
647 #ifdef CONFIG_PGTABLE_4
648 (p7) ld8 r17=[r17] // get *pud (may be 0)
649 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
651 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL?
652 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
655 (p7) ld8 r17=[r17] // get *pmd (may be 0)
656 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
658 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL?
659 dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr);
660 (p6) br.cond.spnt page_fault
662 br.sptk.many b0 // return to continuation point
663 END(nested_dtlb_miss)
666 /////////////////////////////////////////////////////////////////////////////////////////
667 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
673 //-----------------------------------------------------------------------------------
674 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
685 alloc r15=ar.pfs,0,0,3,0
689 ld8 out1=[r3],XSI_IFA_OFS-XSI_ISR_OFS // get vcr.isr, point to ifa
691 ld8 out0=[r3] // get vcr.ifa
694 add r3=XSI_PSR_IC_OFS-XSI_IFA_OFS, r3 // point to vpsr.ic
696 st4 [r3]=r14 // vpsr.ic = 1
697 adds r3=8,r2 // set up second base pointer
702 adds r3=8,r2 // set up second base pointer
704 ssm psr.ic | PSR_DEFAULT_BITS
706 srlz.i // guarantee that interruption collectin is on
710 br.cond.sptk.many xen_page_fault
714 (p15) ssm psr.i // restore psr.i
715 movl r14=ia64_leave_kernel
720 adds out2=16,r12 // out2 = pointer to pt_regs
721 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
725 /////////////////////////////////////////////////////////////////////////////////////////
726 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
731 // Leaving this code inline above results in an IVT section overflow
732 // There is no particular reason for this code to be here...
734 (p15) movl r3=XSI_PSR_I_ADDR
738 (p15) st1 [r3]=r0,XSI_PEND_OFS-XSI_PSR_I_ADDR_OFS // if (p15) vpsr.i = 1
741 (p15) ld4 r14=[r3] // if (pending_interrupts)
742 adds r3=8,r2 // re-set up second base pointer
744 (p15) cmp.ne p15,p0=r14,r0
746 br.cond.sptk.many done_xen_page_fault
752 /////////////////////////////////////////////////////////////////////////////////////////
753 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
757 * What we do here is to simply turn on the dirty bit in the PTE. We need to
758 * update both the page-table and the TLB entry. To efficiently access the PTE,
759 * we address it through the virtual page table. Most likely, the TLB entry for
760 * the relevant virtual page table page is still present in the TLB so we can
761 * normally do this without additional TLB misses. In case the necessary virtual
762 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
763 * up the physical address of the L3 PTE and then continue at label 1 below.
771 mov r16=cr.ifa // get the address that caused the fault
773 movl r30=1f // load continuation point in case of nested fault
782 thash r17=r16 // compute virtual address of L3 PTE
784 mov r29=b0 // save b0 in case of nested fault
785 mov r31=pr // save pr
787 mov r28=ar.ccv // save ar.ccv
790 ;; // avoid RAW on r18
791 mov ar.ccv=r18 // set compare value for cmpxchg
792 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
793 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
795 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only update if page is present
796 mov r24=PAGE_SHIFT<<2
798 (p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present
808 (p6) itc.d r25 // install updated PTE
812 * Tell the assemblers dependency-violation checker that the above "itc" instructions
813 * cannot possibly affect the following loads:
817 ld8 r18=[r17] // read PTE again
819 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
822 mov b0=r29 // restore b0
827 ;; // avoid RAW on r18
828 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
829 mov b0=r29 // restore b0
831 st8 [r17]=r18 // store back updated PTE
832 itc.d r18 // install updated PTE
834 mov pr=r31,-1 // restore pr
844 /////////////////////////////////////////////////////////////////////////////////////////
845 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
848 // Like Entry 8, except for instruction access
855 mov r16=cr.ifa // get the address that caused the fault
857 movl r30=1f // load continuation point in case of nested fault
858 mov r31=pr // save predicates
859 #ifdef CONFIG_ITANIUM
861 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
866 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
868 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
869 #endif /* CONFIG_ITANIUM */
878 thash r17=r16 // compute virtual address of L3 PTE
880 mov r29=b0 // save b0 in case of nested fault)
882 mov r28=ar.ccv // save ar.ccv
886 mov ar.ccv=r18 // set compare value for cmpxchg
887 or r25=_PAGE_A,r18 // set the accessed bit
888 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
890 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page present
891 mov r24=PAGE_SHIFT<<2
893 (p6) cmp.eq p6,p7=r26,r18 // Only if page present
904 (p6) itc.i r25 // install updated PTE
908 * Tell the assemblers dependency-violation checker that the above "itc" instructions
909 * cannot possibly affect the following loads:
913 ld8 r18=[r17] // read PTE again
915 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
918 mov b0=r29 // restore b0
920 #else /* !CONFIG_SMP */
924 or r18=_PAGE_A,r18 // set the accessed bit
925 mov b0=r29 // restore b0
927 st8 [r17]=r18 // store back updated PTE
928 itc.i r18 // install updated PTE
929 #endif /* !CONFIG_SMP */
940 /////////////////////////////////////////////////////////////////////////////////////////
941 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
944 // Like Entry 8, except for data access
951 mov r16=cr.ifa // get the address that caused the fault
953 movl r30=1f // load continuation point in case of nested fault
964 thash r17=r16 // compute virtual address of L3 PTE
967 mov r29=b0 // save b0 in case of nested fault)
969 mov r28=ar.ccv // save ar.ccv
972 ;; // avoid RAW on r18
973 mov ar.ccv=r18 // set compare value for cmpxchg
974 or r25=_PAGE_A,r18 // set the dirty bit
975 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
977 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page is present
978 mov r24=PAGE_SHIFT<<2
980 (p6) cmp.eq p6,p7=r26,r18 // Only if page is present
991 (p6) itc.d r25 // install updated PTE
994 * Tell the assemblers dependency-violation checker that the above "itc" instructions
995 * cannot possibly affect the following loads:
999 ld8 r18=[r17] // read PTE again
1001 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
1008 ;; // avoid RAW on r18
1009 or r18=_PAGE_A,r18 // set the accessed bit
1011 st8 [r17]=r18 // store back updated PTE
1012 itc.d r18 // install updated PTE
1014 mov b0=r29 // restore b0
1024 .org ia64_ivt+0x2c00
1025 /////////////////////////////////////////////////////////////////////////////////////////
1026 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
1029 * The streamlined system call entry/exit paths only save/restore the initial part
1030 * of pt_regs. This implies that the callers of system-calls must adhere to the
1031 * normal procedure calling conventions.
1033 * Registers to be saved & restored:
1034 * CR registers: cr.ipsr, cr.iip, cr.ifs
1035 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
1036 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
1037 * Registers to be restored only:
1038 * r8-r11: output value from the system call.
1040 * During system call exit, scratch registers (including r15) are modified/cleared
1041 * to prevent leaking bits from kernel to user level.
1044 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
1048 ld8 r29=[r22],XSI_IIM_OFS-XSI_IPSR_OFS // get ipsr, point to iip
1050 mov r29=cr.ipsr // M2 (12 cyc)
1052 mov r31=pr // I0 (2 cyc)
1056 ld8 r17=[r22],XSI_IIP_OFS-XSI_IIM_OFS
1058 mov r17=cr.iim // M2 (2 cyc)
1060 mov.m r27=ar.rsc // M2 (12 cyc)
1061 mov r18=__IA64_BREAK_SYSCALL // A
1063 mov.m ar.rsc=0 // M2
1064 mov.m r21=ar.fpsr // M2 (12 cyc)
1065 mov r19=b6 // I0 (2 cyc)
1067 mov.m r23=ar.bspstore // M2 (12 cyc)
1068 mov.m r24=ar.rnat // M2 (5 cyc)
1069 mov.i r26=ar.pfs // I0 (2 cyc)
1073 mov r20=r1 // A save r1
1076 movl r30=sys_call_table // X
1081 mov r28=cr.iip // M2 (2 cyc)
1083 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
1084 (p7) br.cond.spnt non_syscall // B no ->
1086 // From this point on, we are definitely on the syscall-path
1087 // and we can use (non-banked) scratch registers.
1089 ///////////////////////////////////////////////////////////////////////
1090 mov r1=r16 // A move task-pointer to "addl"-addressable reg
1091 mov r2=r16 // A setup r2 for ia64_syscall_setup
1092 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags
1094 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
1095 adds r15=-1024,r15 // A subtract 1024 from syscall number
1096 mov r3=NR_syscalls - 1
1098 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
1099 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
1100 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
1102 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
1103 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
1104 cmp.leu p6,p7=r15,r3 // A syscall number in range?
1107 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
1108 (p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
1109 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
1111 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
1112 cmp.eq p8,p9=2,r8 // A isr.ei==2?
1115 (p8) mov r8=0 // A clear ei to 0
1116 (p7) movl r30=sys_ni_syscall // X
1118 (p8) adds r28=16,r28 // A switch cr.iip to next bundle
1119 (p9) adds r8=1,r8 // A increment ei to next slot
1123 mov.m r25=ar.unat // M2 (5 cyc)
1124 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
1125 adds r15=1024,r15 // A restore original syscall number
1127 // If any of the above loads miss in L1D, we'll stall here until
1128 // the data arrives.
1130 ///////////////////////////////////////////////////////////////////////
1131 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
1132 mov b6=r30 // I0 setup syscall handler branch reg early
1133 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
1135 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
1136 mov r18=ar.bsp // M2 (12 cyc)
1137 (pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS
1139 .back_from_break_fixup:
1140 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
1141 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
1142 br.call.sptk.many b7=ia64_syscall_setup // B
1144 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
1147 mov r2=b0; br.call.sptk b0=xen_bsw1;; mov b0=r2;;
1149 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
1157 st4 [r16]=r3,XSI_PSR_I_ADDR_OFS-XSI_PSR_IC_OFS // vpsr.ic = 1
1159 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
1161 movl r3=ia64_ret_from_syscall // X
1164 srlz.i // M0 ensure interruption collection is on
1165 mov rp=r3 // I0 set the real return addr
1166 (p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
1169 (p15) ld8 r16=[r16] // vpsr.i
1171 (p15) st1 [r16]=r0,XSI_PEND_OFS-XSI_PSR_I_ADDR_OFS // if (p15) vpsr.i = 1
1174 (p15) ld4 r2=[r16] // if (pending_interrupts)
1178 (p6) ssm psr.i // do a real ssm psr.i
1180 (p15) ssm psr.i // M2 restore psr.i
1182 (p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
1183 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
1185 ///////////////////////////////////////////////////////////////////////
1186 // On entry, we optimistically assumed that we're coming from user-space.
1187 // For the rare cases where a system-call is done from within the kernel,
1188 // we fix things up at this point:
1190 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure
1191 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
1193 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
1194 br.cond.sptk .back_from_break_fixup
1197 .org ia64_ivt+0x3000
1198 /////////////////////////////////////////////////////////////////////////////////////////
1199 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
1202 mov r31=pr // prepare to save predicates
1204 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
1211 ssm psr.ic | PSR_DEFAULT_BITS
1214 adds r3=8,r2 // set up second base pointer for SAVE_REST
1215 srlz.i // ensure everybody knows psr.ic is back on
1219 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
1222 br.call.sptk.many rp=xen_get_ivr
1224 mov out0=r8 // pass cr.ivr as first arg
1226 mov out0=cr.ivr // pass cr.ivr as first arg
1228 add out1=16,sp // pass pointer to pt_regs as second arg
1230 srlz.d // make sure we see the effect of cr.ivr
1231 movl r14=ia64_leave_kernel
1234 br.call.sptk.many b6=ia64_handle_irq
1237 .org ia64_ivt+0x3400
1238 /////////////////////////////////////////////////////////////////////////////////////////
1239 // 0x3400 Entry 13 (size 64 bundles) Reserved
1243 .org ia64_ivt+0x3800
1244 /////////////////////////////////////////////////////////////////////////////////////////
1245 // 0x3800 Entry 14 (size 64 bundles) Reserved
1250 * There is no particular reason for this code to be here, other than that
1251 * there happens to be space here that would go unused otherwise. If this
1252 * fault ever gets "unreserved", simply moved the following code to a more
1255 * ia64_syscall_setup() is a separate subroutine so that it can
1256 * allocate stacked registers so it can safely demine any
1257 * potential NaT values from the input registers.
1260 * - executing on bank 0 or bank 1 register set (doesn't matter)
1261 * - r1: stack pointer
1262 * - r2: current task pointer
1264 * - r11: original contents (saved ar.pfs to be saved)
1265 * - r12: original contents (sp to be saved)
1266 * - r13: original contents (tp to be saved)
1267 * - r15: original contents (syscall # to be saved)
1268 * - r18: saved bsp (after switching to kernel stack)
1270 * - r20: saved r1 (gp)
1271 * - r21: saved ar.fpsr
1272 * - r22: kernel's register backing store base (krbs_base)
1273 * - r23: saved ar.bspstore
1274 * - r24: saved ar.rnat
1275 * - r25: saved ar.unat
1276 * - r26: saved ar.pfs
1277 * - r27: saved ar.rsc
1278 * - r28: saved cr.iip
1279 * - r29: saved cr.ipsr
1281 * - b0: original contents (to be saved)
1283 * - p10: TRUE if syscall is invoked with more than 8 out
1284 * registers or r15's Nat is true
1286 * - r3: preserved (same as on entry)
1287 * - r8: -EINVAL if p10 is true
1288 * - r12: points to kernel stack
1289 * - r13: points to current task
1290 * - r14: preserved (same as on entry)
1292 * - p15: TRUE if interrupts need to be re-enabled
1293 * - ar.fpsr: set to kernel settings
1294 * - b6: preserved (same as on entry)
1297 GLOBAL_ENTRY(ia64_syscall_setup)
1299 # error This code assumes that b6 is the first field in pt_regs.
1301 st8 [r1]=r19 // save b6
1302 add r16=PT(CR_IPSR),r1 // initialize first base pointer
1303 add r17=PT(R11),r1 // initialize second base pointer
1305 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
1306 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
1309 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
1311 (pKStk) mov r18=r0 // make sure r18 isn't NaT
1314 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
1315 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
1316 mov r28=b0 // save b0 (2 cyc)
1319 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
1320 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
1324 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
1325 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
1326 and r8=0x7f,r19 // A // get sof of ar.pfs
1328 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
1329 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
1333 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
1337 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
1338 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
1342 tnat.nz p12,p0=in4 // [I0]
1345 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
1346 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
1347 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
1349 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
1350 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
1351 tnat.nz p13,p0=in5 // [I0]
1353 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1354 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
1358 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
1359 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1362 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
1364 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
1367 (p9) tnat.nz p10,p0=r15
1368 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
1370 st8.spill [r17]=r15 // save r15
1374 mov r13=r2 // establish `current'
1375 movl r1=__gp // establish kernel global pointer
1377 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
1381 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1382 movl r17=FPSR_DEFAULT
1384 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1385 (p10) mov r8=-EINVAL
1387 END(ia64_syscall_setup)
1390 .org ia64_ivt+0x3c00
1391 /////////////////////////////////////////////////////////////////////////////////////////
1392 // 0x3c00 Entry 15 (size 64 bundles) Reserved
1397 * Squatting in this space ...
1399 * This special case dispatcher for illegal operation faults allows preserved
1400 * registers to be modified through a callback function (asm only) that is handed
1401 * back from the fault handler in r8. Up to three arguments can be passed to the
1402 * callback function by returning an aggregate with the callback as its first
1403 * element, followed by the arguments.
1405 ENTRY(dispatch_illegal_op_fault)
1409 ssm psr.ic | PSR_DEFAULT_BITS
1411 srlz.i // guarantee that interruption collection is on
1413 (p15) ssm psr.i // restore psr.i
1414 adds r3=8,r2 // set up second base pointer for SAVE_REST
1416 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1420 PT_REGS_UNWIND_INFO(0)
1422 br.call.sptk.many rp=ia64_illegal_op_fault
1424 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1428 movl r15=ia64_leave_kernel
1434 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
1435 br.sptk.many ia64_leave_kernel
1436 END(dispatch_illegal_op_fault)
1438 .org ia64_ivt+0x4000
1439 /////////////////////////////////////////////////////////////////////////////////////////
1440 // 0x4000 Entry 16 (size 64 bundles) Reserved
1444 .org ia64_ivt+0x4400
1445 /////////////////////////////////////////////////////////////////////////////////////////
1446 // 0x4400 Entry 17 (size 64 bundles) Reserved
1451 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER
1455 // There is no particular reason for this code to be here, other than that
1456 // there happens to be space here that would go unused otherwise. If this
1457 // fault ever gets "unreserved", simply moved the following code to a more
1460 alloc r14=ar.pfs,0,0,2,0
1463 adds r3=8,r2 // set up second base pointer for SAVE_REST
1465 ssm psr.ic | PSR_DEFAULT_BITS
1467 srlz.i // guarantee that interruption collection is on
1469 (p15) ssm psr.i // restore psr.i
1470 movl r15=ia64_leave_kernel
1475 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1478 .org ia64_ivt+0x4800
1479 /////////////////////////////////////////////////////////////////////////////////////////
1480 // 0x4800 Entry 18 (size 64 bundles) Reserved
1485 * There is no particular reason for this code to be here, other than that
1486 * there happens to be space here that would go unused otherwise. If this
1487 * fault ever gets "unreserved", simply moved the following code to a more
1491 ENTRY(dispatch_unaligned_handler)
1494 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1498 ssm psr.ic | PSR_DEFAULT_BITS
1500 srlz.i // guarantee that interruption collection is on
1502 (p15) ssm psr.i // restore psr.i
1503 adds r3=8,r2 // set up second base pointer
1506 movl r14=ia64_leave_kernel
1509 br.sptk.many ia64_prepare_handle_unaligned
1510 END(dispatch_unaligned_handler)
1512 .org ia64_ivt+0x4c00
1513 /////////////////////////////////////////////////////////////////////////////////////////
1514 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1519 * There is no particular reason for this code to be here, other than that
1520 * there happens to be space here that would go unused otherwise. If this
1521 * fault ever gets "unreserved", simply moved the following code to a more
1525 ENTRY(dispatch_to_fault_handler)
1529 * r19: fault vector number (e.g., 24 for General Exception)
1530 * r31: contains saved predicates (pr)
1532 SAVE_MIN_WITH_COVER_R19
1533 alloc r14=ar.pfs,0,0,5,0
1538 adds out2=XSI_IFA-XSI_ISR,out1
1539 adds out3=XSI_IIM-XSI_ISR,out1
1540 adds out4=XSI_ITIR-XSI_ISR,out1
1554 ssm psr.ic | PSR_DEFAULT_BITS
1556 srlz.i // guarantee that interruption collection is on
1558 (p15) ssm psr.i // restore psr.i
1559 adds r3=8,r2 // set up second base pointer for SAVE_REST
1562 movl r14=ia64_leave_kernel
1565 br.call.sptk.many b6=ia64_fault
1566 END(dispatch_to_fault_handler)
1569 // --- End of long entries, Beginning of short entries
1572 .org ia64_ivt+0x5000
1573 /////////////////////////////////////////////////////////////////////////////////////////
1574 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1575 ENTRY(page_not_present)
1580 * The Linux page fault handler doesn't expect non-present pages to be in
1581 * the TLB. Flush the existing entry now, so we meet that expectation.
1583 mov r17=PAGE_SHIFT<<2
1589 br.sptk.many page_fault
1590 END(page_not_present)
1592 .org ia64_ivt+0x5100
1593 /////////////////////////////////////////////////////////////////////////////////////////
1594 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1595 ENTRY(key_permission)
1602 br.sptk.many page_fault
1605 .org ia64_ivt+0x5200
1606 /////////////////////////////////////////////////////////////////////////////////////////
1607 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1608 ENTRY(iaccess_rights)
1615 br.sptk.many page_fault
1618 .org ia64_ivt+0x5300
1619 /////////////////////////////////////////////////////////////////////////////////////////
1620 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1621 ENTRY(daccess_rights)
1628 XEN_HYPER_RSM_PSR_DT
1636 br.sptk.many page_fault
1639 .org ia64_ivt+0x5400
1640 /////////////////////////////////////////////////////////////////////////////////////////
1641 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1642 ENTRY(general_exception)
1648 (p6) br.sptk.many dispatch_illegal_op_fault
1650 mov r19=24 // fault number
1651 br.sptk.many dispatch_to_fault_handler
1652 END(general_exception)
1654 .org ia64_ivt+0x5500
1655 /////////////////////////////////////////////////////////////////////////////////////////
1656 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1657 ENTRY(disabled_fp_reg)
1659 rsm psr.dfh // ensure we can access fph
1664 br.sptk.many dispatch_to_fault_handler
1665 END(disabled_fp_reg)
1667 .org ia64_ivt+0x5600
1668 /////////////////////////////////////////////////////////////////////////////////////////
1669 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1670 ENTRY(nat_consumption)
1675 mov r31=pr // save PR
1677 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1678 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1680 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1681 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1682 (p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1684 mov cr.ipsr=r16 // set cr.ipsr.na
1692 END(nat_consumption)
1694 .org ia64_ivt+0x5700
1695 /////////////////////////////////////////////////////////////////////////////////////////
1696 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1697 ENTRY(speculation_vector)
1700 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1701 * this part of the architecture is not implemented in hardware on some CPUs, such
1702 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1703 * the relative target (not yet sign extended). So after sign extending it we
1704 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1705 * i.e., the slot to restart into.
1707 * cr.imm contains zero_ext(imm21)
1712 shl r18=r18,43 // put sign bit in position (43=64-21)
1716 shr r18=r18,39 // sign extend (39=43-4)
1719 add r17=r17,r18 // now add the offset
1722 dep r16=0,r16,41,2 // clear EI
1733 END(speculation_vector)
1735 .org ia64_ivt+0x5800
1736 /////////////////////////////////////////////////////////////////////////////////////////
1737 // 0x5800 Entry 28 (size 16 bundles) Reserved
1741 .org ia64_ivt+0x5900
1742 /////////////////////////////////////////////////////////////////////////////////////////
1743 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1749 .org ia64_ivt+0x5a00
1750 /////////////////////////////////////////////////////////////////////////////////////////
1751 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1752 ENTRY(unaligned_access)
1754 mov r31=pr // prepare to save predicates
1756 br.sptk.many dispatch_unaligned_handler
1757 END(unaligned_access)
1759 .org ia64_ivt+0x5b00
1760 /////////////////////////////////////////////////////////////////////////////////////////
1761 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1762 ENTRY(unsupported_data_reference)
1765 END(unsupported_data_reference)
1767 .org ia64_ivt+0x5c00
1768 /////////////////////////////////////////////////////////////////////////////////////////
1769 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1770 ENTRY(floating_point_fault)
1773 END(floating_point_fault)
1775 .org ia64_ivt+0x5d00
1776 /////////////////////////////////////////////////////////////////////////////////////////
1777 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1778 ENTRY(floating_point_trap)
1781 END(floating_point_trap)
1783 .org ia64_ivt+0x5e00
1784 /////////////////////////////////////////////////////////////////////////////////////////
1785 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1786 ENTRY(lower_privilege_trap)
1789 END(lower_privilege_trap)
1791 .org ia64_ivt+0x5f00
1792 /////////////////////////////////////////////////////////////////////////////////////////
1793 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1794 ENTRY(taken_branch_trap)
1797 END(taken_branch_trap)
1799 .org ia64_ivt+0x6000
1800 /////////////////////////////////////////////////////////////////////////////////////////
1801 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1802 ENTRY(single_step_trap)
1805 END(single_step_trap)
1807 .org ia64_ivt+0x6100
1808 /////////////////////////////////////////////////////////////////////////////////////////
1809 // 0x6100 Entry 37 (size 16 bundles) Reserved
1813 .org ia64_ivt+0x6200
1814 /////////////////////////////////////////////////////////////////////////////////////////
1815 // 0x6200 Entry 38 (size 16 bundles) Reserved
1819 .org ia64_ivt+0x6300
1820 /////////////////////////////////////////////////////////////////////////////////////////
1821 // 0x6300 Entry 39 (size 16 bundles) Reserved
1825 .org ia64_ivt+0x6400
1826 /////////////////////////////////////////////////////////////////////////////////////////
1827 // 0x6400 Entry 40 (size 16 bundles) Reserved
1831 .org ia64_ivt+0x6500
1832 /////////////////////////////////////////////////////////////////////////////////////////
1833 // 0x6500 Entry 41 (size 16 bundles) Reserved
1837 .org ia64_ivt+0x6600
1838 /////////////////////////////////////////////////////////////////////////////////////////
1839 // 0x6600 Entry 42 (size 16 bundles) Reserved
1843 .org ia64_ivt+0x6700
1844 /////////////////////////////////////////////////////////////////////////////////////////
1845 // 0x6700 Entry 43 (size 16 bundles) Reserved
1849 .org ia64_ivt+0x6800
1850 /////////////////////////////////////////////////////////////////////////////////////////
1851 // 0x6800 Entry 44 (size 16 bundles) Reserved
1855 .org ia64_ivt+0x6900
1856 /////////////////////////////////////////////////////////////////////////////////////////
1857 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1858 ENTRY(ia32_exception)
1863 .org ia64_ivt+0x6a00
1864 /////////////////////////////////////////////////////////////////////////////////////////
1865 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1866 ENTRY(ia32_intercept)
1868 #ifdef CONFIG_IA32_SUPPORT
1872 extr.u r17=r16,16,8 // get ISR.code
1874 mov r19=cr.iim // old eflag value
1877 (p6) br.cond.spnt 1f // not a system flag fault
1880 extr.u r17=r16,18,1 // get the eflags.ac bit
1883 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1885 mov pr=r31,-1 // restore predicate registers
1893 #endif // CONFIG_IA32_SUPPORT
1897 .org ia64_ivt+0x6b00
1898 /////////////////////////////////////////////////////////////////////////////////////////
1899 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1900 ENTRY(ia32_interrupt)
1902 #ifdef CONFIG_IA32_SUPPORT
1904 br.sptk.many dispatch_to_ia32_handler
1910 .org ia64_ivt+0x6c00
1911 /////////////////////////////////////////////////////////////////////////////////////////
1912 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1916 .org ia64_ivt+0x6d00
1917 /////////////////////////////////////////////////////////////////////////////////////////
1918 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1922 .org ia64_ivt+0x6e00
1923 /////////////////////////////////////////////////////////////////////////////////////////
1924 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1928 .org ia64_ivt+0x6f00
1929 /////////////////////////////////////////////////////////////////////////////////////////
1930 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1934 .org ia64_ivt+0x7000
1935 /////////////////////////////////////////////////////////////////////////////////////////
1936 // 0x7000 Entry 52 (size 16 bundles) Reserved
1940 .org ia64_ivt+0x7100
1941 /////////////////////////////////////////////////////////////////////////////////////////
1942 // 0x7100 Entry 53 (size 16 bundles) Reserved
1946 .org ia64_ivt+0x7200
1947 /////////////////////////////////////////////////////////////////////////////////////////
1948 // 0x7200 Entry 54 (size 16 bundles) Reserved
1952 .org ia64_ivt+0x7300
1953 /////////////////////////////////////////////////////////////////////////////////////////
1954 // 0x7300 Entry 55 (size 16 bundles) Reserved
1958 .org ia64_ivt+0x7400
1959 /////////////////////////////////////////////////////////////////////////////////////////
1960 // 0x7400 Entry 56 (size 16 bundles) Reserved
1964 .org ia64_ivt+0x7500
1965 /////////////////////////////////////////////////////////////////////////////////////////
1966 // 0x7500 Entry 57 (size 16 bundles) Reserved
1970 .org ia64_ivt+0x7600
1971 /////////////////////////////////////////////////////////////////////////////////////////
1972 // 0x7600 Entry 58 (size 16 bundles) Reserved
1976 .org ia64_ivt+0x7700
1977 /////////////////////////////////////////////////////////////////////////////////////////
1978 // 0x7700 Entry 59 (size 16 bundles) Reserved
1982 .org ia64_ivt+0x7800
1983 /////////////////////////////////////////////////////////////////////////////////////////
1984 // 0x7800 Entry 60 (size 16 bundles) Reserved
1988 .org ia64_ivt+0x7900
1989 /////////////////////////////////////////////////////////////////////////////////////////
1990 // 0x7900 Entry 61 (size 16 bundles) Reserved
1994 .org ia64_ivt+0x7a00
1995 /////////////////////////////////////////////////////////////////////////////////////////
1996 // 0x7a00 Entry 62 (size 16 bundles) Reserved
2000 .org ia64_ivt+0x7b00
2001 /////////////////////////////////////////////////////////////////////////////////////////
2002 // 0x7b00 Entry 63 (size 16 bundles) Reserved
2006 .org ia64_ivt+0x7c00
2007 /////////////////////////////////////////////////////////////////////////////////////////
2008 // 0x7c00 Entry 64 (size 16 bundles) Reserved
2012 .org ia64_ivt+0x7d00
2013 /////////////////////////////////////////////////////////////////////////////////////////
2014 // 0x7d00 Entry 65 (size 16 bundles) Reserved
2018 .org ia64_ivt+0x7e00
2019 /////////////////////////////////////////////////////////////////////////////////////////
2020 // 0x7e00 Entry 66 (size 16 bundles) Reserved
2026 * There is no particular reason for this code to be here, other than that
2027 * there happens to be space here that would go unused otherwise. If this
2028 * fault ever gets "unreserved", simply moved the following code to a more
2032 GLOBAL_ENTRY(xen_bsw1)
2033 /* FIXME: THIS CODE IS NOT NaT SAFE! */
2034 movl r30=XSI_BANKNUM;
2037 movl r30=XSI_BANK1_R16;
2038 movl r31=XSI_BANK1_R16+8;;
2039 ld8 r16=[r30],16; ld8 r17=[r31],16;;
2040 ld8 r18=[r30],16; ld8 r19=[r31],16;;
2041 ld8 r20=[r30],16; ld8 r21=[r31],16;;
2042 ld8 r22=[r30],16; ld8 r23=[r31],16;;
2043 ld8 r24=[r30],16; ld8 r25=[r31],16;;
2044 ld8 r26=[r30],16; ld8 r27=[r31],16;;
2045 ld8 r28=[r30],16; ld8 r29=[r31],16;;
2046 ld8 r30=[r30]; ld8 r31=[r31];;
2051 .org ia64_ivt+0x7f00
2052 /////////////////////////////////////////////////////////////////////////////////////////
2053 // 0x7f00 Entry 67 (size 16 bundles) Reserved
2057 #ifdef CONFIG_IA32_SUPPORT
2060 * There is no particular reason for this code to be here, other than that
2061 * there happens to be space here that would go unused otherwise. If this
2062 * fault ever gets "unreserved", simply moved the following code to a more
2066 // IA32 interrupt entry point
2068 ENTRY(dispatch_to_ia32_handler)
2072 ssm psr.ic | PSR_DEFAULT_BITS
2074 srlz.i // guarantee that interruption collection is on
2077 adds r3=8,r2 // Base pointer for SAVE_REST
2082 shr r14=r14,16 // Get interrupt number
2084 cmp.ne p6,p0=r14,r15
2085 (p6) br.call.dpnt.many b6=non_ia32_syscall
2087 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
2088 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
2090 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
2091 ld8 r8=[r14] // get r8
2093 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
2095 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
2097 ld4 r8=[r14],8 // r8 == eax (syscall number)
2098 mov r15=IA32_NR_syscalls
2100 cmp.ltu.unc p6,p7=r8,r15
2101 ld4 out1=[r14],8 // r9 == ecx
2103 ld4 out2=[r14],8 // r10 == edx
2105 ld4 out0=[r14] // r11 == ebx
2106 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
2108 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
2110 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
2111 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
2113 ld4 out4=[r14] // r15 == edi
2114 movl r16=ia32_syscall_table
2116 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
2117 ld4 r2=[r2] // r2 = current_thread_info()->flags
2120 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
2123 movl r15=ia32_ret_from_syscall
2127 (p8) br.call.sptk.many b6=b6
2128 br.cond.sptk ia32_trace_syscall
2131 alloc r15=ar.pfs,0,0,2,0
2132 mov out0=r14 // interrupt #
2133 add out1=16,sp // pointer to pt_regs
2134 ;; // avoid WAW on CFM
2135 br.call.sptk.many rp=ia32_bad_interrupt
2136 .ret1: movl r15=ia64_leave_kernel
2140 END(dispatch_to_ia32_handler)
2141 #endif /* CONFIG_IA32_SUPPORT */
2145 GLOBAL_ENTRY(xen_event_callback)
2146 mov r31=pr // prepare to save predicates
2148 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
2155 adds r3=8,r2 // set up second base pointer for SAVE_REST
2156 srlz.i // ensure everybody knows psr.ic is back on
2160 alloc r14=ar.pfs,0,0,1,0 // must be first in an insn group
2161 add out0=16,sp // pass pointer to pt_regs as first arg
2163 srlz.d // make sure we see the effect of cr.ivr
2164 movl r14=ia64_leave_kernel
2167 br.call.sptk.many b6=evtchn_do_upcall
2168 END(xen_event_callback)