arch/m32r/boot/setup.S

   1 /*
   2  *  linux/arch/m32r/boot/setup.S -- A setup code.
   3  *
   4  *  Copyright (C) 2001, 2002  Hiroyuki Kondo, Hirokazu Takata,
   5  *  and Hitoshi Yamamoto
   6  *
   7  */
   8 /* $Id$ */
   9
  10 #include <linux/linkage.h>
  11 #include <asm/segment.h>
  12 #include <asm/page.h>
  13 #include <asm/pgtable.h>
  14
  15 #include <linux/config.h>
  16 #include <asm/assembler.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/m32r.h>
  19
  20 /*
  21  * References to members of the boot_cpu_data structure.
  22  */
  23
  24 #define CPU_PARAMS      boot_cpu_data
  25 #define M32R_MCICAR      0xfffffff0
  26 #define M32R_MCDCAR      0xfffffff4
  27 #define M32R_MCCR        0xfffffffc
  28 #define M32R_BSCR0       0xffffffd2
  29
  30 ;BSEL
  31 #define BSEL0CR0         0x00ef5000
  32 #define BSEL0CR1         0x00ef5004
  33 #define BSEL1CR0         0x00ef5100
  34 #define BSEL1CR1         0x00ef5104
  35 #define BSEL0CR0_VAL     0x00000000
  36 #define BSEL0CR1_VAL     0x01200100
  37 #define BSEL1CR0_VAL     0x01018000
  38 #define BSEL1CR1_VAL     0x00200001
  39
  40 ;SDRAMC
  41 #define SDRAMC_SDRF0     0x00ef6000
  42 #define SDRAMC_SDRF1     0x00ef6004
  43 #define SDRAMC_SDIR0     0x00ef6008
  44 #define SDRAMC_SDIR1     0x00ef600c
  45 #define SDRAMC_SD0ADR    0x00ef6020
  46 #define SDRAMC_SD0ER     0x00ef6024
  47 #define SDRAMC_SD0TR     0x00ef6028
  48 #define SDRAMC_SD0MOD    0x00ef602c
  49 #define SDRAMC_SD1ADR    0x00ef6040
  50 #define SDRAMC_SD1ER     0x00ef6044
  51 #define SDRAMC_SD1TR     0x00ef6048
  52 #define SDRAMC_SD1MOD    0x00ef604c
  53 #define SDRAM0           0x18000000
  54 #define SDRAM1           0x1c000000
  55
  56 /*------------------------------------------------------------------------
  57  * start up
  58  */
  59
  60 /*------------------------------------------------------------------------
  61  * Kernel entry
  62  */
  63         .section .boot, "ax"
  64 ENTRY(boot)
  65
  66 /* Set cache mode */
  67 #if defined(CONFIG_CHIP_XNUX2)
  68         ldi     r0, #-2              ;LDIMM     (r0, M32R_MCCR)
  69         ldi     r1, #0x0101             ; cache on (with invalidation)
  70 ;       ldi     r1, #0x00               ; cache off
  71         sth     r1, @r0
  72 #elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
  73     || defined(CONFIG_CHIP_OPSP)
  74         ldi     r0, #-4              ;LDIMM     (r0, M32R_MCCR)
  75         ldi     r1, #0x73               ; cache on (with invalidation)
  76 ;       ldi     r1, #0x00               ; cache off
  77         st      r1, @r0
  78 #else
  79 #error unknown chip configuration
  80 #endif
  81
  82 #ifdef CONFIG_SMP
  83         ;; if not BSP (CPU#0) goto AP_loop
  84         seth    r5, #shigh(M32R_CPUID_PORTL)
  85         ld      r5, @(low(M32R_CPUID_PORTL), r5)
  86         bnez    r5, AP_loop
  87 #if !defined(CONFIG_PLAT_USRV)
  88         ;; boot AP
  89         ld24    r5, #0xeff2f8           ; IPICR7
  90         ldi     r6, #0x2                ; IPI to CPU1
  91         st      r6, @r5
  92 #endif
  93 #endif
  94
  95 /*
  96  *  Now, Jump to stext
  97  *        if with MMU,    TLB on.
  98  *        if with no MMU, only jump.
  99  */
 100         .global eit_vector
 101 mmu_on:
 102         LDIMM   (r13, stext)
 103 #ifdef CONFIG_MMU
 104         bl      init_tlb
 105         LDIMM   (r2, eit_vector)                ; set EVB(cr5)
 106         mvtc    r2, cr5
 107         seth    r0, #high(MMU_REG_BASE)         ; Set MMU_REG_BASE higher
 108         or3     r0, r0, #low(MMU_REG_BASE)      ; Set MMU_REG_BASE lower
 109         ldi     r1, #0x01
 110         st      r1, @(MATM_offset,r0)           ; Set MATM (T bit ON)
 111         ld      r0, @(MATM_offset,r0)           ; Check
 112 #else
 113         seth    r0,#high(M32R_MCDCAR)
 114         or3     r0,r0,#low(M32R_MCDCAR)
 115         ld24    r1,#0x8080
 116         st      r1,@r0
 117 #endif  /* CONFIG_MMU */
 118         jmp     r13
 119         nop
 120         nop
 121
 122 #ifdef CONFIG_SMP
 123 /*
 124  * AP wait loop
 125  */
 126 ENTRY(AP_loop)
 127         ;; disable interrupt
 128         clrpsw  #0x40
 129         ;; reset EVB
 130         LDIMM   (r4, _AP_RE)
 131         seth    r5, #high(__PAGE_OFFSET)
 132         or3     r5, r5, #low(__PAGE_OFFSET)
 133         not     r5, r5
 134         and     r4, r5
 135         mvtc    r4, cr5
 136         ;; disable maskable interrupt
 137         seth    r4, #high(M32R_ICU_IMASK_PORTL)
 138         or3     r4, r4, #low(M32R_ICU_IMASK_PORTL)
 139         ldi     r5, #0
 140         st      r5, @r4
 141         ld      r5, @r4
 142         ;; enable only IPI
 143         setpsw  #0x40
 144         ;; LOOOOOOOOOOOOOOP!!!
 145         .fillinsn
 146 2:
 147         nop
 148         nop
 149         bra     2b
 150         nop
 151         nop
 152
 153 #ifdef CONFIG_CHIP_M32700_TS1
 154         .global dcache_dummy
 155         .balign 16, 0
 156 dcache_dummy:
 157         .byte   16
 158 #endif  /* CONFIG_CHIP_M32700_TS1 */
 159 #endif  /* CONFIG_SMP */
 160
 161         .end
 162