1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5206 ColdFire Arnewsh board.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
8 * 1999/02/24 Modified for the 5307 processor David W. Miller
11 /*****************************************************************************/
13 #include "linux/autoconf.h"
14 #include "asm/coldfire.h"
15 #include "asm/mcfsim.h"
17 /*****************************************************************************/
20 * Arnewsh m5206 ColdFire eval board, chip select and memory setup.
23 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
24 #define VBR_BASE MEM_BASE /* Vector address */
27 * The following define the limits within which to search for
30 #define MEM_MIN 0x00100000 /* Search from 1Mb */
31 #define MEM_MAX 0x02000000 /* Max DRAM 32Mb! */
32 #define MEM_LUMP 0x00010000 /* 64 Kb chunks */
34 #define MEM_TMPSTACK 0x00010000 /* At 64k - for exceptions */
39 #define CS0_ADDR 0x0000f000 /* CS0 connected to Flash ROM */
40 #define CS0_MASK 0xf0000000 /* is 1Mbyte */
41 #define CS0_CTRL 0x00000000 /* read-only */
42 #define CS1_ADDR 0x00000000 /* CS1 not connected */
43 #define CS1_MASK 0x00000000
44 #define CS1_CTRL 0x00000000
45 #define CS2_ADDR 0x00003000 /* CS2 connected to SRAM */
46 #define CS2_MASK 0x0000f000 /* is 1Mbyte */
47 #define CS2_CTRL 0x00001903 /* read-write */
48 #define CS3_ADDR 0x00004000 /* CS3 connected to LED, par port */
49 #define CS3_MASK 0x0000f000 /* is 1Mbyte */
50 #define CS3_CTRL 0x00000083 /* read-write */
51 #define CS4_ADDR 0x00000000 /* CS4 not connected */
52 #define CS4_MASK 0x00000000
53 #define CS4_CTRL 0x00000123
54 #define CS5_ADDR 0x00000000 /* CS5 not connected */
55 #define CS5_MASK 0x00000000
56 #define CS5_CTRL 0x00000000
57 #define CS6_ADDR 0x00000000 /* CS6 not connected */
58 #define CS6_MASK 0x00000000
59 #define CS6_CTRL 0x00000000
60 #define CS7_ADDR 0x00000000 /* CS7 not connected */
61 #define CS7_MASK 0x00000000
62 #define CS7_CTRL 0x00000000
63 #define DMC_CTRL 0x00000000 /* default memory control */
65 /*****************************************************************************/
73 /*****************************************************************************/
78 * Set up the usable of RAM stuff. Size of RAM is determined then
79 * an initial stack set up at the end.
90 /*****************************************************************************/
95 * This is the codes first entry point. This is where it all
101 move.w #0x2700, %sr /* No interrupts */
105 * Setup VBR here, otherwise buserror remap will not work.
106 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
108 * bkr@cut.de 19990306
110 * Note: this is because dBUG points VBR to ROM, making vectors read
111 * only, so the bus trap can't be changed. (RS)
113 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
115 move.l %a7, _ramvec /* Set up vector addr */
116 move.l %a7, _rambase /* Set up base RAM addr */
120 * Determine size of RAM, then set up initial stack.
122 * On the Arnewsh 5206 board we can probe for the amount
125 move.l #MEM_MIN, %a0 /* Start at bottom */
126 move.l #MEM_MAX, %a1 /* Set stop point */
127 lea.l MEM_TMPSTACK, %sp /* Set up tmp stack ptr */
129 move.l #VBR_BASE+8, %a2 /* Address of bus trap */
130 lea.l _ram_buserr, %a3 /* Get RAM trap address */
131 move.l %a3, (%a2) /* Set trap to local ptr */
134 move.l (%a0), %d0 /* Attempt read */
135 add.l #MEM_LUMP, %a0 /* Try next bank */
136 cmp.l %a1, %a0 /* Check more? */
140 * BUS error trap handler - used for RAM probing.
145 _found_ram: /* Vectored here on bus err */
146 move.l %a0, %d0 /* Mem end addr is in a0 */
147 move.l %d0, %sp /* Set up initial stack ptr */
148 move.l %d0, _ramend /* Set end ram addr */
152 * Enable CPU internal cache.
154 move.l #0x01000000, %d0 /* Invalidate cache cmd */
155 movec %d0, %CACR /* Invalidate cache */
156 move.l #0x80000100, %d0 /* Setup cache mask */
157 movec %d0, %CACR /* Enable cache */
160 #ifdef CONFIG_ROMFS_FS
162 * Move ROM filesystem above bss :-)
164 lea.l _sbss, %a0 /* Get start of bss */
165 lea.l _ebss, %a1 /* Set up destination */
166 move.l %a0, %a2 /* Copy of bss start */
168 move.l 8(%a0), %d0 /* Get size of ROMFS */
169 addq.l #8, %d0 /* Allow for rounding */
170 and.l #0xfffffffc, %d0 /* Whole words */
172 add.l %d0, %a0 /* Copy from end */
173 add.l %d0, %a1 /* Copy from end */
174 move.l %a1, _ramstart /* Set start of ram */
177 move.l -(%a0), %d0 /* Copy dword */
179 cmp.l %a0, %a2 /* Check if at end */
182 #else /* CONFIG_ROMFS_FS */
184 move.l %a1, _ramstart
185 #endif /* CONFIG_ROMFS_FS */
189 * Zero out the bss region.
191 lea.l _sbss, %a0 /* Get start of bss */
192 lea.l _ebss, %a1 /* Get end of bss */
193 clr.l %d0 /* Set value */
195 move.l %d0, (%a0)+ /* Clear each word */
196 cmp.l %a0, %a1 /* Check if at end */
200 * Load the current task pointer and stack.
202 lea init_thread_union, %a0
206 * Assember start up done, start code proper.
208 jsr start_kernel /* Start Linux kernel */
211 jmp _exit /* Should never get here */
213 /*****************************************************************************/