1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF527x ColdFire based Freescale boards.
6 * (C) Copyright 2003-2004, Greg Ungerer (gerg@snapgear.com).
9 /*****************************************************************************/
11 #include <linux/config.h>
12 #include <linux/threads.h>
13 #include <linux/linkage.h>
14 #include <asm/segment.h>
15 #include <asm/coldfire.h>
16 #include <asm/mcfsim.h>
18 /*****************************************************************************/
21 * Freescale M5271EVB ColdFire eval board, chip select and memory setup.
24 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
25 #define VBR_BASE MEM_BASE /* Vector address */
27 #if defined(CONFIG_RAM4MB)
28 #define MEM_SIZE 0x00400000 /* Memory size 4Mb */
29 #elif defined(CONFIG_RAM8MB)
30 #define MEM_SIZE 0x00800000 /* Memory size 8Mb */
32 #define MEM_SIZE 0x01000000 /* Memory size 16Mb */
35 /*****************************************************************************/
43 /*****************************************************************************/
48 * Set up the usable of RAM stuff. Size of RAM is determined then
49 * an initial stack set up at the end.
60 /*****************************************************************************/
65 * This is the codes first entry point. This is where it all
71 move.w #0x2700, %sr /* No interrupts */
74 * Setup VBR here, otherwise buserror remap will not work.
75 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
79 * Note: this is because dBUG points VBR to ROM, making vectors read
80 * only, so the bus trap can't be changed. (RS)
82 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
84 move.l %a7, _ramvec /* Set up vector addr */
85 move.l %a7, _rambase /* Set up base RAM addr */
93 move.l %a0, %d0 /* Mem end addr is in a0 */
94 move.l %d0, %sp /* Set up initial stack ptr */
95 move.l %d0, _ramend /* Set end ram addr */
98 * Enable CPU internal cache.
100 move.l #0x01400000, %d0
101 movec %d0, %CACR /* Invalidate cache */
104 move.l #0x0000c000, %d0 /* Set SDRAM cached only */
106 move.l #0x00000000, %d0 /* No other regions cached */
109 move.l #0x80400100, %d0 /* Configure cache */
110 movec %d0, %CACR /* Enable cache */
114 #ifdef CONFIG_ROMFS_FS
116 * Move ROM filesystem above bss :-)
118 lea.l _sbss, %a0 /* Get start of bss */
119 lea.l _ebss, %a1 /* Set up destination */
120 move.l %a0, %a2 /* Copy of bss start */
122 move.l 8(%a0), %d0 /* Get size of ROMFS */
123 addq.l #8, %d0 /* Allow for rounding */
124 and.l #0xfffffffc, %d0 /* Whole words */
126 add.l %d0, %a0 /* Copy from end */
127 add.l %d0, %a1 /* Copy from end */
128 move.l %a1, _ramstart /* Set start of ram */
131 move.l -(%a0), %d0 /* Copy dword */
133 cmp.l %a0, %a2 /* Check if at end */
135 #else /* CONFIG_ROMFS_FS */
137 move.l %a1, _ramstart
138 #endif /* CONFIG_ROMFS_FS */
142 * Zero out the bss region.
144 lea.l _sbss, %a0 /* Get start of bss */
145 lea.l _ebss, %a1 /* Get end of bss */
146 clr.l %d0 /* Set value */
148 move.l %d0, (%a0)+ /* Clear each word */
149 cmp.l %a0, %a1 /* Check if at end */
153 * Load the current thread pointer and stack.
155 lea init_thread_union, %a0
159 * Assember start up done, start code proper.
161 jsr start_kernel /* Start Linux kernel */
164 jmp _exit /* Should never get here */
166 /*****************************************************************************/