1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for Feith CLEOPATRA board.
6 * (C) Copyright 2001, Roman Wagner.
8 * 1999/02/24 Modified for the 5307 processor David W. Miller
11 /*****************************************************************************/
13 #include "linux/autoconf.h"
14 #include "asm/coldfire.h"
15 #include "asm/mcfsim.h"
17 /*****************************************************************************/
20 * Feith CLEOPATRA board, chip select and memory setup.
23 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
24 #define VBR_BASE MEM_BASE /* Vector address */
26 #if defined(CONFIG_RAM16MB)
27 #define MEM_SIZE 0x01000000 /* Memory size 16Mb */
29 #define MEM_SIZE 0x00800000 /* Memory size 8Mb */
32 /*****************************************************************************/
40 /*****************************************************************************/
45 * Set up the usable of RAM stuff. Size of RAM is determined then
46 * an initial stack set up at the end.
57 /*****************************************************************************/
62 * This is the codes first entry point. This is where it all
68 move.w #0x2700, %sr /* No interrupts */
72 * Setup VBR here, otherwise buserror remap will not work.
73 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
77 * Note: this is because dBUG points VBR to ROM, making vectors read
78 * only, so the bus trap can't be changed. (RS)
80 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
82 move.l %a7, _ramvec /* Set up vector addr */
83 move.l %a7, _rambase /* Set up base RAM addr */
87 * Determine size of RAM, then set up initial stack.
90 * The current version of the 5307 processor
91 * SWT does not work. Probing invalid addresses
92 * will hang the system.
94 * For now, set the memory size to 8 meg
98 move.l %a0, %d0 /* Mem end addr is in a0 */
99 move.l %d0, %sp /* Set up initial stack ptr */
100 move.l %d0, _ramend /* Set end ram addr */
103 /* now fire off the cache, remember to invalidate it first */
107 movc %d0,%CACR /* cache is off */
109 movl #CACR_CINVA,%d0 /* invalidate whole cache */
115 /* make region ROM cachable (turn off for flash programming?) */
116 /* 0xff000000 - 0xffffffff */
117 movl #(0xff<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_WBACK+ACR_WPROTECT,%d0
120 /* make region RAM cachable *
121 /* 0x00000000 - 0x00ffffffff */
122 movl #(0x00<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_WBACK,%d0
125 /* make the default cache mode precise */
126 movl #CACR_EC+CACR_ESB+CACR_DCM_OFF_PRE,%d0 /* enable cache */
130 #ifdef CONFIG_ROMFS_FS
132 * Move ROM filesystem above bss :-)
134 lea.l _sbss, %a0 /* Get start of bss */
135 lea.l _ebss, %a1 /* Set up destination */
136 move.l %a0, %a2 /* Copy of bss start */
138 move.l 8(%a0), %d0 /* Get size of ROMFS */
139 addq.l #8, %d0 /* Allow for rounding */
140 and.l #0xfffffffc, %d0 /* Whole words */
142 add.l %d0, %a0 /* Copy from end */
143 add.l %d0, %a1 /* Copy from end */
144 move.l %a1, _ramstart /* Set start of ram */
147 move.l -(%a0), %d0 /* Copy dword */
149 cmp.l %a0, %a2 /* Check if at end */
152 #else /* CONFIG_ROMFS_FS */
154 move.l %a1, _ramstart
155 #endif /* CONFIG_ROMFS_FS */
159 * Zero out the bss region.
161 lea.l _sbss, %a0 /* Get start of bss */
162 lea.l _ebss, %a1 /* Get end of bss */
163 clr.l %d0 /* Set value */
165 move.l %d0, (%a0)+ /* Clear each word */
166 cmp.l %a0, %a1 /* Check if at end */
170 * load the current task pointer and stack
172 lea init_thread_union, %a0
176 * Assember start up done, start code proper.
178 jsr start_kernel /* Start Linux kernel */
181 jmp _exit /* Should never get here */
183 /*****************************************************************************/