2 * Copyright 2000 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ppopov@mvista.com or source@mvista.com
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/init.h>
28 #include <linux/sched.h>
29 #include <linux/ioport.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
35 #include <asm/bootinfo.h>
37 #include <asm/mipsregs.h>
38 #include <asm/reboot.h>
39 #include <asm/pgtable.h>
40 #include <asm/au1000.h>
41 #include <asm/pb1000.h>
43 #ifdef CONFIG_USB_OHCI
44 // Enable the workaround for the OHCI DoneHead
45 // register corruption problem.
46 #define CONFIG_AU1000_OHCI_FIX
47 ^^^^^^^^^^^^^^^^^^^^^^
48 !!! I shall not define symbols starting with CONFIG_ !!!
51 void __init board_setup(void)
53 u32 pin_func, static_cfg0;
54 u32 sys_freqctrl, sys_clksrc;
55 u32 prid = read_c0_prid();
57 // set AUX clock to 12MHz * 8 = 96 MHz
58 au_writel(8, SYS_AUXPLL);
59 au_writel(0, SYS_PINSTATERD);
62 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
63 /* zero and disable FREQ2 */
64 sys_freqctrl = au_readl(SYS_FREQCTRL0);
65 sys_freqctrl &= ~0xFFF00000;
66 au_writel(sys_freqctrl, SYS_FREQCTRL0);
68 /* zero and disable USBH/USBD clocks */
69 sys_clksrc = au_readl(SYS_CLKSRC);
70 sys_clksrc &= ~0x00007FE0;
71 au_writel(sys_clksrc, SYS_CLKSRC);
73 sys_freqctrl = au_readl(SYS_FREQCTRL0);
74 sys_freqctrl &= ~0xFFF00000;
76 sys_clksrc = au_readl(SYS_CLKSRC);
77 sys_clksrc &= ~0x00007FE0;
79 switch (prid & 0x000000FF)
84 /* CPU core freq to 48MHz to slow it way down... */
85 au_writel(4, SYS_CPUPLL);
88 * Setup 48MHz FREQ2 from CPUPLL for USB Host
90 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
91 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
92 au_writel(sys_freqctrl, SYS_FREQCTRL0);
94 /* CPU core freq to 384MHz */
95 au_writel(0x20, SYS_CPUPLL);
97 printk("Au1000: 48MHz OHCI workaround enabled\n");
100 default: /* HC and newer */
101 // FREQ2 = aux/2 = 48 MHz
102 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
103 au_writel(sys_freqctrl, SYS_FREQCTRL0);
108 * Route 48MHz FREQ2 into USB Host and/or Device
110 #ifdef CONFIG_USB_OHCI
111 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
113 #ifdef CONFIG_AU1X00_USB_DEVICE
114 sys_clksrc |= ((4<<7) | (0<<6) | (0<<5));
116 au_writel(sys_clksrc, SYS_CLKSRC);
118 // configure pins GPIO[14:9] as GPIO
119 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
121 #ifndef CONFIG_AU1X00_USB_DEVICE
122 // 2nd USB port is USB host
125 au_writel(pin_func, SYS_PINFUNC);
126 au_writel(0x2800, SYS_TRIOUTCLR);
127 au_writel(0x0030, SYS_OUTPUTCLR);
128 #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
130 // make gpio 15 an input (for interrupt line)
131 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
132 // we don't need I2S, so make it available for GPIO[31:29]
134 au_writel(pin_func, SYS_PINFUNC);
136 au_writel(0x8000, SYS_TRIOUTCLR);
138 static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
139 au_writel(static_cfg0, MEM_STCFG0);
141 // configure RCE2* for LCD
142 au_writel(0x00000004, MEM_STCFG2);
145 au_writel(0x09000000, MEM_STTIME2);
147 // Set 32-bit base address decoding for RCE2*
148 au_writel(0x10003ff0, MEM_STADDR2);
151 // expand CE0 to cover PCI
152 au_writel(0x11803e40, MEM_STADDR1);
154 // burst visibility on
155 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
157 au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
158 au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
160 /* setup the static bus controller */
161 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
162 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
163 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
166 au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
167 au_writel(0, SDRAM_MBAR); // set mbar to 0
168 au_writel(0x2, SDRAM_CMD); // enable memory accesses
172 /* Enable Au1000 BCLK switching - note: sed1356 must not use
173 * its BCLK (Au1000 LCLK) for any timings */
174 switch (prid & 0x000000FF)
180 default: /* HC and newer */
181 /* Enable sys bus clock divider when IDLE state or no bus
183 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);