arch/mips/dec/setup.c

   1 /*
   2  * Setup the interrupt stuff.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1998 Harald Koerfgen
   9  * Copyright (C) 2000, 2001, 2002, 2003  Maciej W. Rozycki
  10  */
  11 #include <linux/config.h>
  12 #include <linux/sched.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/param.h>
  15 #include <linux/console.h>
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/types.h>
  20
  21 #include <asm/bootinfo.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/irq.h>
  25 #include <asm/irq_cpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/reboot.h>
  28 #include <asm/time.h>
  29 #include <asm/traps.h>
  30 #include <asm/wbflush.h>
  31
  32 #include <asm/dec/interrupts.h>
  33 #include <asm/dec/ioasic.h>
  34 #include <asm/dec/ioasic_addrs.h>
  35 #include <asm/dec/ioasic_ints.h>
  36 #include <asm/dec/kn01.h>
  37 #include <asm/dec/kn02.h>
  38 #include <asm/dec/kn02ba.h>
  39 #include <asm/dec/kn02ca.h>
  40 #include <asm/dec/kn03.h>
  41 #include <asm/dec/kn230.h>
  42
  43
  44 extern void dec_machine_restart(char *command);
  45 extern void dec_machine_halt(void);
  46 extern void dec_machine_power_off(void);
  47 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
  48
  49 extern asmlinkage void decstation_handle_int(void);
  50
  51 #ifdef CONFIG_BLK_DEV_INITRD
  52 extern unsigned long initrd_start, initrd_end;
  53 extern void * __rd_start, * __rd_end;
  54 #endif
  55
  56 spinlock_t ioasic_ssr_lock;
  57
  58 volatile u32 *ioasic_base;
  59 unsigned long dec_kn_slot_size;
  60
  61 /*
  62  * IRQ routing and priority tables.  Priorites are set as follows:
  63  *
  64  *              KN01    KN230   KN02    KN02-BA KN02-CA KN03
  65  *
  66  * MEMORY       CPU     CPU     CPU     ASIC    CPU     CPU
  67  * RTC          CPU     CPU     CPU     ASIC    CPU     CPU
  68  * DMA          -       -       -       ASIC    ASIC    ASIC
  69  * SERIAL0      CPU     CPU     CSR     ASIC    ASIC    ASIC
  70  * SERIAL1      -       -       -       ASIC    -       ASIC
  71  * SCSI         CPU     CPU     CSR     ASIC    ASIC    ASIC
  72  * ETHERNET     CPU     *       CSR     ASIC    ASIC    ASIC
  73  * other        -       -       -       ASIC    -       -
  74  * TC2          -       -       CSR     CPU     ASIC    ASIC
  75  * TC1          -       -       CSR     CPU     ASIC    ASIC
  76  * TC0          -       -       CSR     CPU     ASIC    ASIC
  77  * other        -       CPU     -       CPU     ASIC    ASIC
  78  * other        -       -       -       -       CPU     CPU
  79  *
  80  * * -- shared with SCSI
  81  */
  82
  83 int dec_interrupt[DEC_NR_INTS] = {
  84         [0 ... DEC_NR_INTS - 1] = -1
  85 };
  86 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
  87         { { .i = ~0 }, { .p = dec_intr_unimplemented } },
  88 };
  89 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
  90         { { .i = ~0 }, { .p = asic_intr_unimplemented } },
  91 };
  92 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
  93
  94 static struct irqaction ioirq = {
  95         .handler = no_action,
  96         .name = "cascade",
  97 };
  98 static struct irqaction fpuirq = {
  99         .handler = no_action,
 100         .name = "fpu",
 101 };
 102
 103 static struct irqaction busirq = {
 104         .flags = SA_INTERRUPT,
 105         .name = "bus error",
 106 };
 107
 108 static struct irqaction haltirq = {
 109         .handler = dec_intr_halt,
 110         .name = "halt",
 111 };
 112
 113
 114 /*
 115  * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
 116  */
 117 void __init dec_be_init(void)
 118 {
 119         switch (mips_machtype) {
 120         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 121                 busirq.flags |= SA_SHIRQ;
 122                 break;
 123         case MACH_DS5000_200:   /* DS5000/200 3max */
 124         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 125         case MACH_DS5900:       /* DS5900 bigmax */
 126                 board_be_handler = dec_ecc_be_handler;
 127                 busirq.handler = dec_ecc_be_interrupt;
 128                 dec_ecc_be_init();
 129                 break;
 130         }
 131 }
 132
 133
 134 extern void dec_time_init(void);
 135 extern void dec_timer_setup(struct irqaction *);
 136
 137 static void __init decstation_setup(void)
 138 {
 139 #ifdef CONFIG_BLK_DEV_INITRD
 140        ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
 141        initrd_start = (unsigned long)&__rd_start;
 142        initrd_end = (unsigned long)&__rd_end;
 143 #endif
 144         board_be_init = dec_be_init;
 145         board_time_init = dec_time_init;
 146         board_timer_setup = dec_timer_setup;
 147
 148         wbflush_setup();
 149
 150         _machine_restart = dec_machine_restart;
 151         _machine_halt = dec_machine_halt;
 152         _machine_power_off = dec_machine_power_off;
 153 }
 154
 155 early_initcall(decstation_setup);
 156
 157 /*
 158  * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
 159  * or DS3100 (aka Pmax).
 160  */
 161 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
 162         [DEC_IRQ_CASCADE]       = -1,
 163         [DEC_IRQ_AB_RECV]       = -1,
 164         [DEC_IRQ_AB_XMIT]       = -1,
 165         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
 166         [DEC_IRQ_ASC]           = -1,
 167         [DEC_IRQ_FLOPPY]        = -1,
 168         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 169         [DEC_IRQ_HALT]          = -1,
 170         [DEC_IRQ_ISDN]          = -1,
 171         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
 172         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
 173         [DEC_IRQ_PSU]           = -1,
 174         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
 175         [DEC_IRQ_SCC0]          = -1,
 176         [DEC_IRQ_SCC1]          = -1,
 177         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
 178         [DEC_IRQ_TC0]           = -1,
 179         [DEC_IRQ_TC1]           = -1,
 180         [DEC_IRQ_TC2]           = -1,
 181         [DEC_IRQ_TIMER]         = -1,
 182         [DEC_IRQ_VIDEO]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
 183         [DEC_IRQ_ASC_MERR]      = -1,
 184         [DEC_IRQ_ASC_ERR]       = -1,
 185         [DEC_IRQ_ASC_DMA]       = -1,
 186         [DEC_IRQ_FLOPPY_ERR]    = -1,
 187         [DEC_IRQ_ISDN_ERR]      = -1,
 188         [DEC_IRQ_ISDN_RXDMA]    = -1,
 189         [DEC_IRQ_ISDN_TXDMA]    = -1,
 190         [DEC_IRQ_LANCE_MERR]    = -1,
 191         [DEC_IRQ_SCC0A_RXERR]   = -1,
 192         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 193         [DEC_IRQ_SCC0A_TXERR]   = -1,
 194         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 195         [DEC_IRQ_AB_RXERR]      = -1,
 196         [DEC_IRQ_AB_RXDMA]      = -1,
 197         [DEC_IRQ_AB_TXERR]      = -1,
 198         [DEC_IRQ_AB_TXDMA]      = -1,
 199         [DEC_IRQ_SCC1A_RXERR]   = -1,
 200         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 201         [DEC_IRQ_SCC1A_TXERR]   = -1,
 202         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 203 };
 204
 205 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
 206         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
 207                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
 208         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
 209                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
 210         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
 211                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
 212         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
 213                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
 214         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
 215                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
 216         { { .i = DEC_CPU_IRQ_ALL },
 217                 { .p = cpu_all_int } },
 218 };
 219
 220 void __init dec_init_kn01(void)
 221 {
 222         /* IRQ routing. */
 223         memcpy(&dec_interrupt, &kn01_interrupt,
 224                 sizeof(kn01_interrupt));
 225
 226         /* CPU IRQ priorities. */
 227         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
 228                 sizeof(kn01_cpu_mask_nr_tbl));
 229
 230         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 231
 232 }                               /* dec_init_kn01 */
 233
 234
 235 /*
 236  * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
 237  */
 238 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
 239         [DEC_IRQ_CASCADE]       = -1,
 240         [DEC_IRQ_AB_RECV]       = -1,
 241         [DEC_IRQ_AB_XMIT]       = -1,
 242         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
 243         [DEC_IRQ_ASC]           = -1,
 244         [DEC_IRQ_FLOPPY]        = -1,
 245         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 246         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
 247         [DEC_IRQ_ISDN]          = -1,
 248         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
 249         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
 250         [DEC_IRQ_PSU]           = -1,
 251         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
 252         [DEC_IRQ_SCC0]          = -1,
 253         [DEC_IRQ_SCC1]          = -1,
 254         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
 255         [DEC_IRQ_TC0]           = -1,
 256         [DEC_IRQ_TC1]           = -1,
 257         [DEC_IRQ_TC2]           = -1,
 258         [DEC_IRQ_TIMER]         = -1,
 259         [DEC_IRQ_VIDEO]         = -1,
 260         [DEC_IRQ_ASC_MERR]      = -1,
 261         [DEC_IRQ_ASC_ERR]       = -1,
 262         [DEC_IRQ_ASC_DMA]       = -1,
 263         [DEC_IRQ_FLOPPY_ERR]    = -1,
 264         [DEC_IRQ_ISDN_ERR]      = -1,
 265         [DEC_IRQ_ISDN_RXDMA]    = -1,
 266         [DEC_IRQ_ISDN_TXDMA]    = -1,
 267         [DEC_IRQ_LANCE_MERR]    = -1,
 268         [DEC_IRQ_SCC0A_RXERR]   = -1,
 269         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 270         [DEC_IRQ_SCC0A_TXERR]   = -1,
 271         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 272         [DEC_IRQ_AB_RXERR]      = -1,
 273         [DEC_IRQ_AB_RXDMA]      = -1,
 274         [DEC_IRQ_AB_TXERR]      = -1,
 275         [DEC_IRQ_AB_TXDMA]      = -1,
 276         [DEC_IRQ_SCC1A_RXERR]   = -1,
 277         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 278         [DEC_IRQ_SCC1A_TXERR]   = -1,
 279         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 280 };
 281
 282 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
 283         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
 284                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
 285         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
 286                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
 287         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
 288                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
 289         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
 290                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
 291         { { .i = DEC_CPU_IRQ_ALL },
 292                 { .p = cpu_all_int } },
 293 };
 294
 295 void __init dec_init_kn230(void)
 296 {
 297         /* IRQ routing. */
 298         memcpy(&dec_interrupt, &kn230_interrupt,
 299                 sizeof(kn230_interrupt));
 300
 301         /* CPU IRQ priorities. */
 302         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
 303                 sizeof(kn230_cpu_mask_nr_tbl));
 304
 305         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 306
 307 }                               /* dec_init_kn230 */
 308
 309
 310 /*
 311  * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
 312  */
 313 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
 314         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
 315         [DEC_IRQ_AB_RECV]       = -1,
 316         [DEC_IRQ_AB_XMIT]       = -1,
 317         [DEC_IRQ_DZ11]          = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
 318         [DEC_IRQ_ASC]           = KN02_IRQ_NR(KN02_CSR_INR_ASC),
 319         [DEC_IRQ_FLOPPY]        = -1,
 320         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 321         [DEC_IRQ_HALT]          = -1,
 322         [DEC_IRQ_ISDN]          = -1,
 323         [DEC_IRQ_LANCE]         = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
 324         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
 325         [DEC_IRQ_PSU]           = -1,
 326         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
 327         [DEC_IRQ_SCC0]          = -1,
 328         [DEC_IRQ_SCC1]          = -1,
 329         [DEC_IRQ_SII]           = -1,
 330         [DEC_IRQ_TC0]           = KN02_IRQ_NR(KN02_CSR_INR_TC0),
 331         [DEC_IRQ_TC1]           = KN02_IRQ_NR(KN02_CSR_INR_TC1),
 332         [DEC_IRQ_TC2]           = KN02_IRQ_NR(KN02_CSR_INR_TC2),
 333         [DEC_IRQ_TIMER]         = -1,
 334         [DEC_IRQ_VIDEO]         = -1,
 335         [DEC_IRQ_ASC_MERR]      = -1,
 336         [DEC_IRQ_ASC_ERR]       = -1,
 337         [DEC_IRQ_ASC_DMA]       = -1,
 338         [DEC_IRQ_FLOPPY_ERR]    = -1,
 339         [DEC_IRQ_ISDN_ERR]      = -1,
 340         [DEC_IRQ_ISDN_RXDMA]    = -1,
 341         [DEC_IRQ_ISDN_TXDMA]    = -1,
 342         [DEC_IRQ_LANCE_MERR]    = -1,
 343         [DEC_IRQ_SCC0A_RXERR]   = -1,
 344         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 345         [DEC_IRQ_SCC0A_TXERR]   = -1,
 346         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 347         [DEC_IRQ_AB_RXERR]      = -1,
 348         [DEC_IRQ_AB_RXDMA]      = -1,
 349         [DEC_IRQ_AB_TXERR]      = -1,
 350         [DEC_IRQ_AB_TXDMA]      = -1,
 351         [DEC_IRQ_SCC1A_RXERR]   = -1,
 352         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 353         [DEC_IRQ_SCC1A_TXERR]   = -1,
 354         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 355 };
 356
 357 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
 358         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
 359                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
 360         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
 361                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
 362         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
 363                 { .p = kn02_io_int } },
 364         { { .i = DEC_CPU_IRQ_ALL },
 365                 { .p = cpu_all_int } },
 366 };
 367
 368 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
 369         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
 370                 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
 371         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
 372                 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
 373         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
 374                 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
 375         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
 376                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
 377         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
 378                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
 379         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
 380                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
 381         { { .i = KN02_IRQ_ALL },
 382                 { .p = kn02_all_int } },
 383 };
 384
 385 void __init dec_init_kn02(void)
 386 {
 387         /* IRQ routing. */
 388         memcpy(&dec_interrupt, &kn02_interrupt,
 389                 sizeof(kn02_interrupt));
 390
 391         /* CPU IRQ priorities. */
 392         memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
 393                 sizeof(kn02_cpu_mask_nr_tbl));
 394
 395         /* KN02 CSR IRQ priorities. */
 396         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
 397                 sizeof(kn02_asic_mask_nr_tbl));
 398
 399         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 400         init_kn02_irqs(KN02_IRQ_BASE);
 401
 402 }                               /* dec_init_kn02 */
 403
 404
 405 /*
 406  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 407  * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
 408  * DS5000/150, aka 4min.
 409  */
 410 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
 411         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
 412         [DEC_IRQ_AB_RECV]       = -1,
 413         [DEC_IRQ_AB_XMIT]       = -1,
 414         [DEC_IRQ_DZ11]          = -1,
 415         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02BA_IO_INR_ASC),
 416         [DEC_IRQ_FLOPPY]        = -1,
 417         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 418         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
 419         [DEC_IRQ_ISDN]          = -1,
 420         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
 421         [DEC_IRQ_BUS]           = IO_IRQ_NR(KN02BA_IO_INR_BUS),
 422         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN02BA_IO_INR_PSU),
 423         [DEC_IRQ_RTC]           = IO_IRQ_NR(KN02BA_IO_INR_RTC),
 424         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
 425         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
 426         [DEC_IRQ_SII]           = -1,
 427         [DEC_IRQ_TC0]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
 428         [DEC_IRQ_TC1]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
 429         [DEC_IRQ_TC2]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
 430         [DEC_IRQ_TIMER]         = -1,
 431         [DEC_IRQ_VIDEO]         = -1,
 432         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 433         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 434         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 435         [DEC_IRQ_FLOPPY_ERR]    = -1,
 436         [DEC_IRQ_ISDN_ERR]      = -1,
 437         [DEC_IRQ_ISDN_RXDMA]    = -1,
 438         [DEC_IRQ_ISDN_TXDMA]    = -1,
 439         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 440         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 441         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 442         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 443         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 444         [DEC_IRQ_AB_RXERR]      = -1,
 445         [DEC_IRQ_AB_RXDMA]      = -1,
 446         [DEC_IRQ_AB_TXERR]      = -1,
 447         [DEC_IRQ_AB_TXDMA]      = -1,
 448         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 449         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 450         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 451         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 452 };
 453
 454 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
 455         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
 456                 { .p = kn02xa_io_int } },
 457         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
 458                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
 459         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
 460                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
 461         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
 462                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
 463         { { .i = DEC_CPU_IRQ_ALL },
 464                 { .p = cpu_all_int } },
 465 };
 466
 467 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
 468         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
 469                 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
 470         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
 471                 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
 472         { { .i = IO_IRQ_DMA },
 473                 { .p = asic_dma_int } },
 474         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
 475                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
 476         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
 477                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
 478         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
 479                 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
 480         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
 481                 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
 482         { { .i = IO_IRQ_ALL },
 483                 { .p = asic_all_int } },
 484 };
 485
 486 void __init dec_init_kn02ba(void)
 487 {
 488         /* IRQ routing. */
 489         memcpy(&dec_interrupt, &kn02ba_interrupt,
 490                 sizeof(kn02ba_interrupt));
 491
 492         /* CPU IRQ priorities. */
 493         memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
 494                 sizeof(kn02ba_cpu_mask_nr_tbl));
 495
 496         /* I/O ASIC IRQ priorities. */
 497         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
 498                 sizeof(kn02ba_asic_mask_nr_tbl));
 499
 500         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 501         init_ioasic_irqs(IO_IRQ_BASE);
 502
 503 }                               /* dec_init_kn02ba */
 504
 505
 506 /*
 507  * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
 508  * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
 509  * DS5000/50, aka 4MAXine.
 510  */
 511 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
 512         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
 513         [DEC_IRQ_AB_RECV]       = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
 514         [DEC_IRQ_AB_XMIT]       = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
 515         [DEC_IRQ_DZ11]          = -1,
 516         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02CA_IO_INR_ASC),
 517         [DEC_IRQ_FLOPPY]        = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
 518         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 519         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
 520         [DEC_IRQ_ISDN]          = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
 521         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
 522         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
 523         [DEC_IRQ_PSU]           = -1,
 524         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
 525         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
 526         [DEC_IRQ_SCC1]          = -1,
 527         [DEC_IRQ_SII]           = -1,
 528         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN02CA_IO_INR_TC0),
 529         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN02CA_IO_INR_TC1),
 530         [DEC_IRQ_TC2]           = -1,
 531         [DEC_IRQ_TIMER]         = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
 532         [DEC_IRQ_VIDEO]         = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
 533         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 534         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 535         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 536         [DEC_IRQ_FLOPPY_ERR]    = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
 537         [DEC_IRQ_ISDN_ERR]      = IO_IRQ_NR(IO_INR_ISDN_ERR),
 538         [DEC_IRQ_ISDN_RXDMA]    = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
 539         [DEC_IRQ_ISDN_TXDMA]    = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
 540         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 541         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 542         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 543         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 544         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 545         [DEC_IRQ_AB_RXERR]      = IO_IRQ_NR(IO_INR_AB_RXERR),
 546         [DEC_IRQ_AB_RXDMA]      = IO_IRQ_NR(IO_INR_AB_RXDMA),
 547         [DEC_IRQ_AB_TXERR]      = IO_IRQ_NR(IO_INR_AB_TXERR),
 548         [DEC_IRQ_AB_TXDMA]      = IO_IRQ_NR(IO_INR_AB_TXDMA),
 549         [DEC_IRQ_SCC1A_RXERR]   = -1,
 550         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 551         [DEC_IRQ_SCC1A_TXERR]   = -1,
 552         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 553 };
 554
 555 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
 556         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
 557                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
 558         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
 559                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
 560         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
 561                 { .p = kn02xa_io_int } },
 562         { { .i = DEC_CPU_IRQ_ALL },
 563                 { .p = cpu_all_int } },
 564 };
 565
 566 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
 567         { { .i = IO_IRQ_DMA },
 568                 { .p = asic_dma_int } },
 569         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
 570                 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
 571         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
 572                 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
 573         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
 574                 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
 575         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
 576                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
 577         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
 578                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
 579         { { .i = IO_IRQ_ALL },
 580                 { .p = asic_all_int } },
 581 };
 582
 583 void __init dec_init_kn02ca(void)
 584 {
 585         /* IRQ routing. */
 586         memcpy(&dec_interrupt, &kn02ca_interrupt,
 587                 sizeof(kn02ca_interrupt));
 588
 589         /* CPU IRQ priorities. */
 590         memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
 591                 sizeof(kn02ca_cpu_mask_nr_tbl));
 592
 593         /* I/O ASIC IRQ priorities. */
 594         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
 595                 sizeof(kn02ca_asic_mask_nr_tbl));
 596
 597         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 598         init_ioasic_irqs(IO_IRQ_BASE);
 599
 600 }                               /* dec_init_kn02ca */
 601
 602
 603 /*
 604  * Machine-specific initialisation for KN03, aka DS5000/240,
 605  * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
 606  * DS5000/260, aka 4max+ and DS5900/260.
 607  */
 608 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
 609         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
 610         [DEC_IRQ_AB_RECV]       = -1,
 611         [DEC_IRQ_AB_XMIT]       = -1,
 612         [DEC_IRQ_DZ11]          = -1,
 613         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN03_IO_INR_ASC),
 614         [DEC_IRQ_FLOPPY]        = -1,
 615         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 616         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
 617         [DEC_IRQ_ISDN]          = -1,
 618         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN03_IO_INR_LANCE),
 619         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
 620         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN03_IO_INR_PSU),
 621         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
 622         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN03_IO_INR_SCC0),
 623         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN03_IO_INR_SCC1),
 624         [DEC_IRQ_SII]           = -1,
 625         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN03_IO_INR_TC0),
 626         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN03_IO_INR_TC1),
 627         [DEC_IRQ_TC2]           = IO_IRQ_NR(KN03_IO_INR_TC2),
 628         [DEC_IRQ_TIMER]         = -1,
 629         [DEC_IRQ_VIDEO]         = -1,
 630         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 631         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 632         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 633         [DEC_IRQ_FLOPPY_ERR]    = -1,
 634         [DEC_IRQ_ISDN_ERR]      = -1,
 635         [DEC_IRQ_ISDN_RXDMA]    = -1,
 636         [DEC_IRQ_ISDN_TXDMA]    = -1,
 637         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 638         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 639         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 640         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 641         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 642         [DEC_IRQ_AB_RXERR]      = -1,
 643         [DEC_IRQ_AB_RXDMA]      = -1,
 644         [DEC_IRQ_AB_TXERR]      = -1,
 645         [DEC_IRQ_AB_TXDMA]      = -1,
 646         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 647         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 648         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 649         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 650 };
 651
 652 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
 653         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
 654                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
 655         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
 656                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
 657         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
 658                 { .p = kn03_io_int } },
 659         { { .i = DEC_CPU_IRQ_ALL },
 660                 { .p = cpu_all_int } },
 661 };
 662
 663 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
 664         { { .i = IO_IRQ_DMA },
 665                 { .p = asic_dma_int } },
 666         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
 667                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
 668         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
 669                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
 670         { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
 671                 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
 672         { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
 673                 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
 674         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
 675                 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
 676         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
 677                 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
 678         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
 679                 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
 680         { { .i = IO_IRQ_ALL },
 681                 { .p = asic_all_int } },
 682 };
 683
 684 void __init dec_init_kn03(void)
 685 {
 686         /* IRQ routing. */
 687         memcpy(&dec_interrupt, &kn03_interrupt,
 688                 sizeof(kn03_interrupt));
 689
 690         /* CPU IRQ priorities. */
 691         memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
 692                 sizeof(kn03_cpu_mask_nr_tbl));
 693
 694         /* I/O ASIC IRQ priorities. */
 695         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
 696                 sizeof(kn03_asic_mask_nr_tbl));
 697
 698         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 699         init_ioasic_irqs(IO_IRQ_BASE);
 700
 701 }                               /* dec_init_kn03 */
 702
 703
 704 void __init init_IRQ(void)
 705 {
 706         switch (mips_machtype) {
 707         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 708                 dec_init_kn01();
 709                 break;
 710         case MACH_DS5100:       /* DS5100 MIPSmate */
 711                 dec_init_kn230();
 712                 break;
 713         case MACH_DS5000_200:   /* DS5000/200 3max */
 714                 dec_init_kn02();
 715                 break;
 716         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 717                 dec_init_kn02ba();
 718                 break;
 719         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 720         case MACH_DS5900:       /* DS5900 bigmax */
 721                 dec_init_kn03();
 722                 break;
 723         case MACH_DS5000_XX:    /* Personal DS5000/xx */
 724                 dec_init_kn02ca();
 725                 break;
 726         case MACH_DS5800:       /* DS5800 Isis */
 727                 panic("Don't know how to set this up!");
 728                 break;
 729         case MACH_DS5400:       /* DS5400 MIPSfair */
 730                 panic("Don't know how to set this up!");
 731                 break;
 732         case MACH_DS5500:       /* DS5500 MIPSfair-2 */
 733                 panic("Don't know how to set this up!");
 734                 break;
 735         }
 736         set_except_vector(0, decstation_handle_int);
 737
 738         /* Free the FPU interrupt if the exception is present. */
 739         if (!cpu_has_nofpuex) {
 740                 cpu_fpu_mask = 0;
 741                 dec_interrupt[DEC_IRQ_FPU] = -1;
 742         }
 743
 744         /* Register board interrupts: FPU and cascade. */
 745         if (dec_interrupt[DEC_IRQ_FPU] >= 0)
 746                 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
 747         if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
 748                 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
 749
 750         /* Register the bus error interrupt. */
 751         if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
 752                 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
 753
 754         /* Register the HALT interrupt. */
 755         if (dec_interrupt[DEC_IRQ_HALT] >= 0)
 756                 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
 757 }
 758
 759 EXPORT_SYMBOL(ioasic_base);
 760 EXPORT_SYMBOL(dec_kn_slot_size);
 761 EXPORT_SYMBOL(dec_interrupt);