2 * Processor capabilities determination functions.
4 * Copyright (C) 1994 - 2003 Ralf Baechle
5 * Copyright (C) 2001 MIPS Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
12 #include <linux/config.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/stddef.h>
21 #include <asm/mipsregs.h>
22 #include <asm/system.h>
25 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26 * the implementation of the "wait" feature differs between CPU families. This
27 * points to the function that implements CPU specific wait.
28 * The wait instruction stops the pipeline and reduces the power consumption of
31 void (*cpu_wait)(void) = NULL;
33 static void r3081_wait(void)
35 unsigned long cfg = read_c0_conf();
36 write_c0_conf(cfg | R30XX_CONF_HALT);
39 static void r39xx_wait(void)
41 unsigned long cfg = read_c0_conf();
42 write_c0_conf(cfg | TX39_CONF_HALT);
45 static void r4k_wait(void)
47 __asm__(".set\tmips3\n\t"
55 /* using the wait instruction makes CP0 counter unusable */
56 __asm__(".set\tmips3\n\t"
69 static inline void check_wait(void)
71 struct cpuinfo_mips *c = ¤t_cpu_data;
73 printk("Checking for 'wait' instruction... ");
77 cpu_wait = r3081_wait;
78 printk(" available.\n");
81 cpu_wait = r39xx_wait;
82 printk(" available.\n");
93 /* case CPU_RM9000: */
103 printk(" available.\n");
108 cpu_wait = au1k_wait;
109 printk(" available.\n");
112 printk(" unavailable.\n");
117 void __init check_bugs32(void)
123 * Probe whether cpu has config register by trying to play with
124 * alternate cache bit and see whether it matters.
125 * It's used by cpu_probe to distinguish between R3000A and R3081.
127 static inline int cpu_has_confreg(void)
129 #ifdef CONFIG_CPU_R3000
130 extern unsigned long r3k_cache_size(unsigned long);
131 unsigned long size1, size2;
132 unsigned long cfg = read_c0_conf();
134 size1 = r3k_cache_size(ST0_ISC);
135 write_c0_conf(cfg ^ R30XX_CONF_AC);
136 size2 = r3k_cache_size(ST0_ISC);
138 return size1 != size2;
145 * Get the FPU Implementation/Revision.
147 static inline unsigned long cpu_get_fpu_id(void)
149 unsigned long tmp, fpu_id;
151 tmp = read_c0_status();
153 fpu_id = read_32bit_cp1_register(CP1_REVISION);
154 write_c0_status(tmp);
159 * Check the CPU has an FPU the official way.
161 static inline int __cpu_has_fpu(void)
163 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
166 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
169 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
171 switch (c->processor_id & 0xff00) {
173 c->cputype = CPU_R2000;
174 c->isa_level = MIPS_CPU_ISA_I;
175 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
177 c->options |= MIPS_CPU_FPU;
181 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
182 if (cpu_has_confreg())
183 c->cputype = CPU_R3081E;
185 c->cputype = CPU_R3000A;
187 c->cputype = CPU_R3000;
188 c->isa_level = MIPS_CPU_ISA_I;
189 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
191 c->options |= MIPS_CPU_FPU;
195 if (read_c0_config() & CONF_SC) {
196 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
197 c->cputype = CPU_R4400PC;
199 c->cputype = CPU_R4000PC;
201 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
202 c->cputype = CPU_R4400SC;
204 c->cputype = CPU_R4000SC;
207 c->isa_level = MIPS_CPU_ISA_III;
208 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
209 MIPS_CPU_WATCH | MIPS_CPU_VCE |
213 case PRID_IMP_VR41XX:
214 switch (c->processor_id & 0xf0) {
215 #ifndef CONFIG_VR4181
216 case PRID_REV_VR4111:
217 c->cputype = CPU_VR4111;
220 case PRID_REV_VR4181:
221 c->cputype = CPU_VR4181;
224 case PRID_REV_VR4121:
225 c->cputype = CPU_VR4121;
227 case PRID_REV_VR4122:
228 if ((c->processor_id & 0xf) < 0x3)
229 c->cputype = CPU_VR4122;
231 c->cputype = CPU_VR4181A;
233 case PRID_REV_VR4130:
234 if ((c->processor_id & 0xf) < 0x4)
235 c->cputype = CPU_VR4131;
237 c->cputype = CPU_VR4133;
240 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
241 c->cputype = CPU_VR41XX;
244 c->isa_level = MIPS_CPU_ISA_III;
245 c->options = R4K_OPTS;
249 c->cputype = CPU_R4300;
250 c->isa_level = MIPS_CPU_ISA_III;
251 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
256 c->cputype = CPU_R4600;
257 c->isa_level = MIPS_CPU_ISA_III;
258 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
264 * This processor doesn't have an MMU, so it's not
265 * "real easy" to run Linux on it. It is left purely
266 * for documentation. Commented out because it shares
267 * it's c0_prid id number with the TX3900.
269 c->cputype = CPU_R4650;
270 c->isa_level = MIPS_CPU_ISA_III;
271 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
276 c->isa_level = MIPS_CPU_ISA_I;
277 c->options = MIPS_CPU_TLB;
279 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
280 c->cputype = CPU_TX3927;
283 switch (c->processor_id & 0xff) {
284 case PRID_REV_TX3912:
285 c->cputype = CPU_TX3912;
288 case PRID_REV_TX3922:
289 c->cputype = CPU_TX3922;
293 c->cputype = CPU_UNKNOWN;
299 c->cputype = CPU_R4700;
300 c->isa_level = MIPS_CPU_ISA_III;
301 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
306 c->cputype = CPU_TX49XX;
307 c->isa_level = MIPS_CPU_ISA_III;
308 c->options = R4K_OPTS | MIPS_CPU_LLSC;
309 if (!(c->processor_id & 0x08))
310 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
314 c->cputype = CPU_R5000;
315 c->isa_level = MIPS_CPU_ISA_IV;
316 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
321 c->cputype = CPU_R5432;
322 c->isa_level = MIPS_CPU_ISA_IV;
323 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
324 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
328 c->cputype = CPU_R5500;
329 c->isa_level = MIPS_CPU_ISA_IV;
330 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
331 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
334 case PRID_IMP_NEVADA:
335 c->cputype = CPU_NEVADA;
336 c->isa_level = MIPS_CPU_ISA_IV;
337 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
338 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
342 c->cputype = CPU_R6000;
343 c->isa_level = MIPS_CPU_ISA_II;
344 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
348 case PRID_IMP_R6000A:
349 c->cputype = CPU_R6000A;
350 c->isa_level = MIPS_CPU_ISA_II;
351 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
355 case PRID_IMP_RM7000:
356 c->cputype = CPU_RM7000;
357 c->isa_level = MIPS_CPU_ISA_IV;
358 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
361 * Undocumented RM7000: Bit 29 in the info register of
362 * the RM7000 v2.0 indicates if the TLB has 48 or 64
365 * 29 1 => 64 entry JTLB
368 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
370 case PRID_IMP_RM9000:
371 c->cputype = CPU_RM9000;
372 c->isa_level = MIPS_CPU_ISA_IV;
373 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
376 * Bit 29 in the info register of the RM9000
377 * indicates if the TLB has 48 or 64 entries.
379 * 29 1 => 64 entry JTLB
382 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
385 c->cputype = CPU_R8000;
386 c->isa_level = MIPS_CPU_ISA_IV;
387 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
388 MIPS_CPU_FPU | MIPS_CPU_32FPR |
390 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
392 case PRID_IMP_R10000:
393 c->cputype = CPU_R10000;
394 c->isa_level = MIPS_CPU_ISA_IV;
395 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
396 MIPS_CPU_FPU | MIPS_CPU_32FPR |
397 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
401 case PRID_IMP_R12000:
402 c->cputype = CPU_R12000;
403 c->isa_level = MIPS_CPU_ISA_IV;
404 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
405 MIPS_CPU_FPU | MIPS_CPU_32FPR |
406 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
411 c->cputype = CPU_UNKNOWN;
416 static inline void decode_config1(struct cpuinfo_mips *c)
418 unsigned long config0 = read_c0_config();
419 unsigned long config1;
421 if ((config0 & (1 << 31)) == 0)
422 return; /* actually wort a panic() */
424 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
425 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
426 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
427 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
428 config1 = read_c0_config1();
429 if (config1 & (1 << 3))
430 c->options |= MIPS_CPU_WATCH;
431 if (config1 & (1 << 2))
432 c->options |= MIPS_CPU_MIPS16;
433 if (config1 & (1 << 1))
434 c->options |= MIPS_CPU_EJTAG;
436 c->options |= MIPS_CPU_FPU;
437 c->options |= MIPS_CPU_32FPR;
439 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
441 c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
444 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
447 switch (c->processor_id & 0xff00) {
449 c->cputype = CPU_4KC;
450 c->isa_level = MIPS_CPU_ISA_M32;
453 c->cputype = CPU_4KEC;
454 c->isa_level = MIPS_CPU_ISA_M32;
457 c->cputype = CPU_4KSC;
458 c->isa_level = MIPS_CPU_ISA_M32;
461 c->cputype = CPU_5KC;
462 c->isa_level = MIPS_CPU_ISA_M64;
465 c->cputype = CPU_20KC;
466 c->isa_level = MIPS_CPU_ISA_M64;
469 c->cputype = CPU_24K;
470 c->isa_level = MIPS_CPU_ISA_M32;
473 c->cputype = CPU_25KF;
474 c->isa_level = MIPS_CPU_ISA_M64;
475 /* Probe for L2 cache */
476 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
479 c->cputype = CPU_UNKNOWN;
484 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
487 switch (c->processor_id & 0xff00) {
488 case PRID_IMP_AU1_REV1:
489 case PRID_IMP_AU1_REV2:
490 switch ((c->processor_id >> 24) & 0xff) {
492 c->cputype = CPU_AU1000;
495 c->cputype = CPU_AU1500;
498 c->cputype = CPU_AU1100;
501 c->cputype = CPU_AU1550;
504 panic("Unknown Au Core!");
507 c->isa_level = MIPS_CPU_ISA_M32;
510 c->cputype = CPU_UNKNOWN;
515 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
518 switch (c->processor_id & 0xff00) {
520 c->cputype = CPU_SB1;
521 c->isa_level = MIPS_CPU_ISA_M64;
522 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
523 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
524 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
525 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
526 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
527 /* FPU in pass1 is known to have issues. */
528 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
532 c->cputype = CPU_UNKNOWN;
537 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
540 switch (c->processor_id & 0xff00) {
541 case PRID_IMP_SR71000:
542 c->cputype = CPU_SR71000;
543 c->isa_level = MIPS_CPU_ISA_M64;
544 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
545 MIPS_CPU_4KTLB | MIPS_CPU_FPU |
546 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
551 c->cputype = CPU_UNKNOWN;
556 __init void cpu_probe(void)
558 struct cpuinfo_mips *c = ¤t_cpu_data;
560 c->processor_id = PRID_IMP_UNKNOWN;
561 c->fpu_id = FPIR_IMP_NONE;
562 c->cputype = CPU_UNKNOWN;
564 c->processor_id = read_c0_prid();
565 switch (c->processor_id & 0xff0000) {
567 case PRID_COMP_LEGACY:
573 case PRID_COMP_ALCHEMY:
574 cpu_probe_alchemy(c);
576 case PRID_COMP_SIBYTE:
580 case PRID_COMP_SANDCRAFT:
581 cpu_probe_sandcraft(c);
584 c->cputype = CPU_UNKNOWN;
586 if (c->options & MIPS_CPU_FPU)
587 c->fpu_id = cpu_get_fpu_id();
590 __init void cpu_report(void)
592 struct cpuinfo_mips *c = ¤t_cpu_data;
594 printk("CPU revision is: %08x\n", c->processor_id);
595 if (c->options & MIPS_CPU_FPU)
596 printk("FPU revision is: %08x\n", c->fpu_id);