arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) 1994 - 2003 Ralf Baechle
   5  * Copyright (C) 2001 MIPS Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/stddef.h>
  17
  18 #include <asm/bugs.h>
  19 #include <asm/cpu.h>
  20 #include <asm/fpu.h>
  21 #include <asm/mipsregs.h>
  22 #include <asm/system.h>
  23
  24 /*
  25  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  26  * the implementation of the "wait" feature differs between CPU families. This
  27  * points to the function that implements CPU specific wait.
  28  * The wait instruction stops the pipeline and reduces the power consumption of
  29  * the CPU very much.
  30  */
  31 void (*cpu_wait)(void) = NULL;
  32
  33 static void r3081_wait(void)
  34 {
  35         unsigned long cfg = read_c0_conf();
  36         write_c0_conf(cfg | R30XX_CONF_HALT);
  37 }
  38
  39 static void r39xx_wait(void)
  40 {
  41         unsigned long cfg = read_c0_conf();
  42         write_c0_conf(cfg | TX39_CONF_HALT);
  43 }
  44
  45 static void r4k_wait(void)
  46 {
  47         __asm__(".set\tmips3\n\t"
  48                 "wait\n\t"
  49                 ".set\tmips0");
  50 }
  51
  52 void au1k_wait(void)
  53 {
  54 #ifdef CONFIG_PM
  55         /* using the wait instruction makes CP0 counter unusable */
  56         __asm__(".set\tmips3\n\t"
  57                 "wait\n\t"
  58                 "nop\n\t"
  59                 "nop\n\t"
  60                 "nop\n\t"
  61                 "nop\n\t"
  62                 ".set\tmips0");
  63 #else
  64         __asm__("nop\n\t"
  65                 "nop");
  66 #endif
  67 }
  68
  69 static inline void check_wait(void)
  70 {
  71         struct cpuinfo_mips *c = &current_cpu_data;
  72
  73         printk("Checking for 'wait' instruction... ");
  74         switch (c->cputype) {
  75         case CPU_R3081:
  76         case CPU_R3081E:
  77                 cpu_wait = r3081_wait;
  78                 printk(" available.\n");
  79                 break;
  80         case CPU_TX3927:
  81                 cpu_wait = r39xx_wait;
  82                 printk(" available.\n");
  83                 break;
  84         case CPU_R4200:
  85 /*      case CPU_R4300: */
  86         case CPU_R4600:
  87         case CPU_R4640:
  88         case CPU_R4650:
  89         case CPU_R4700:
  90         case CPU_R5000:
  91         case CPU_NEVADA:
  92         case CPU_RM7000:
  93 /*      case CPU_RM9000: */
  94         case CPU_TX49XX:
  95         case CPU_4KC:
  96         case CPU_4KEC:
  97         case CPU_4KSC:
  98         case CPU_5KC:
  99 /*      case CPU_20KC:*/
 100         case CPU_24K:
 101         case CPU_25KF:
 102                 cpu_wait = r4k_wait;
 103                 printk(" available.\n");
 104                 break;
 105         case CPU_AU1000:
 106         case CPU_AU1100:
 107         case CPU_AU1500:
 108                 cpu_wait = au1k_wait;
 109                 printk(" available.\n");
 110                 break;
 111         default:
 112                 printk(" unavailable.\n");
 113                 break;
 114         }
 115 }
 116
 117 void __init check_bugs32(void)
 118 {
 119         check_wait();
 120 }
 121
 122 /*
 123  * Probe whether cpu has config register by trying to play with
 124  * alternate cache bit and see whether it matters.
 125  * It's used by cpu_probe to distinguish between R3000A and R3081.
 126  */
 127 static inline int cpu_has_confreg(void)
 128 {
 129 #ifdef CONFIG_CPU_R3000
 130         extern unsigned long r3k_cache_size(unsigned long);
 131         unsigned long size1, size2;
 132         unsigned long cfg = read_c0_conf();
 133
 134         size1 = r3k_cache_size(ST0_ISC);
 135         write_c0_conf(cfg ^ R30XX_CONF_AC);
 136         size2 = r3k_cache_size(ST0_ISC);
 137         write_c0_conf(cfg);
 138         return size1 != size2;
 139 #else
 140         return 0;
 141 #endif
 142 }
 143
 144 /*
 145  * Get the FPU Implementation/Revision.
 146  */
 147 static inline unsigned long cpu_get_fpu_id(void)
 148 {
 149         unsigned long tmp, fpu_id;
 150
 151         tmp = read_c0_status();
 152         __enable_fpu();
 153         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 154         write_c0_status(tmp);
 155         return fpu_id;
 156 }
 157
 158 /*
 159  * Check the CPU has an FPU the official way.
 160  */
 161 static inline int __cpu_has_fpu(void)
 162 {
 163         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 164 }
 165
 166 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
 167                 | MIPS_CPU_COUNTER)
 168
 169 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 170 {
 171         switch (c->processor_id & 0xff00) {
 172         case PRID_IMP_R2000:
 173                 c->cputype = CPU_R2000;
 174                 c->isa_level = MIPS_CPU_ISA_I;
 175                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 176                 if (__cpu_has_fpu())
 177                         c->options |= MIPS_CPU_FPU;
 178                 c->tlbsize = 64;
 179                 break;
 180         case PRID_IMP_R3000:
 181                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 182                         if (cpu_has_confreg())
 183                                 c->cputype = CPU_R3081E;
 184                         else
 185                                 c->cputype = CPU_R3000A;
 186                 else
 187                         c->cputype = CPU_R3000;
 188                 c->isa_level = MIPS_CPU_ISA_I;
 189                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 190                 if (__cpu_has_fpu())
 191                         c->options |= MIPS_CPU_FPU;
 192                 c->tlbsize = 64;
 193                 break;
 194         case PRID_IMP_R4000:
 195                 if (read_c0_config() & CONF_SC) {
 196                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 197                                 c->cputype = CPU_R4400PC;
 198                         else
 199                                 c->cputype = CPU_R4000PC;
 200                 } else {
 201                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 202                                 c->cputype = CPU_R4400SC;
 203                         else
 204                                 c->cputype = CPU_R4000SC;
 205                 }
 206
 207                 c->isa_level = MIPS_CPU_ISA_III;
 208                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 209                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 210                              MIPS_CPU_LLSC;
 211                 c->tlbsize = 48;
 212                 break;
 213         case PRID_IMP_VR41XX:
 214                 switch (c->processor_id & 0xf0) {
 215 #ifndef CONFIG_VR4181
 216                 case PRID_REV_VR4111:
 217                         c->cputype = CPU_VR4111;
 218                         break;
 219 #else
 220                 case PRID_REV_VR4181:
 221                         c->cputype = CPU_VR4181;
 222                         break;
 223 #endif
 224                 case PRID_REV_VR4121:
 225                         c->cputype = CPU_VR4121;
 226                         break;
 227                 case PRID_REV_VR4122:
 228                         if ((c->processor_id & 0xf) < 0x3)
 229                                 c->cputype = CPU_VR4122;
 230                         else
 231                                 c->cputype = CPU_VR4181A;
 232                         break;
 233                 case PRID_REV_VR4130:
 234                         if ((c->processor_id & 0xf) < 0x4)
 235                                 c->cputype = CPU_VR4131;
 236                         else
 237                                 c->cputype = CPU_VR4133;
 238                         break;
 239                 default:
 240                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 241                                 c->cputype = CPU_VR41XX;
 242                                 break;
 243                 }
 244                 c->isa_level = MIPS_CPU_ISA_III;
 245                 c->options = R4K_OPTS;
 246                 c->tlbsize = 32;
 247                 break;
 248         case PRID_IMP_R4300:
 249                 c->cputype = CPU_R4300;
 250                 c->isa_level = MIPS_CPU_ISA_III;
 251                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 252                              MIPS_CPU_LLSC;
 253                 c->tlbsize = 32;
 254                 break;
 255         case PRID_IMP_R4600:
 256                 c->cputype = CPU_R4600;
 257                 c->isa_level = MIPS_CPU_ISA_III;
 258                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 259                 c->tlbsize = 48;
 260                 break;
 261         #if 0
 262         case PRID_IMP_R4650:
 263                 /*
 264                  * This processor doesn't have an MMU, so it's not
 265                  * "real easy" to run Linux on it. It is left purely
 266                  * for documentation.  Commented out because it shares
 267                  * it's c0_prid id number with the TX3900.
 268                  */
 269                 c->cputype = CPU_R4650;
 270                 c->isa_level = MIPS_CPU_ISA_III;
 271                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 272                 c->tlbsize = 48;
 273                 break;
 274         #endif
 275         case PRID_IMP_TX39:
 276                 c->isa_level = MIPS_CPU_ISA_I;
 277                 c->options = MIPS_CPU_TLB;
 278
 279                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 280                         c->cputype = CPU_TX3927;
 281                         c->tlbsize = 64;
 282                 } else {
 283                         switch (c->processor_id & 0xff) {
 284                         case PRID_REV_TX3912:
 285                                 c->cputype = CPU_TX3912;
 286                                 c->tlbsize = 32;
 287                                 break;
 288                         case PRID_REV_TX3922:
 289                                 c->cputype = CPU_TX3922;
 290                                 c->tlbsize = 64;
 291                                 break;
 292                         default:
 293                                 c->cputype = CPU_UNKNOWN;
 294                                 break;
 295                         }
 296                 }
 297                 break;
 298         case PRID_IMP_R4700:
 299                 c->cputype = CPU_R4700;
 300                 c->isa_level = MIPS_CPU_ISA_III;
 301                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 302                              MIPS_CPU_LLSC;
 303                 c->tlbsize = 48;
 304                 break;
 305         case PRID_IMP_TX49:
 306                 c->cputype = CPU_TX49XX;
 307                 c->isa_level = MIPS_CPU_ISA_III;
 308                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 309                 if (!(c->processor_id & 0x08))
 310                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 311                 c->tlbsize = 48;
 312                 break;
 313         case PRID_IMP_R5000:
 314                 c->cputype = CPU_R5000;
 315                 c->isa_level = MIPS_CPU_ISA_IV;
 316                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 317                              MIPS_CPU_LLSC;
 318                 c->tlbsize = 48;
 319                 break;
 320         case PRID_IMP_R5432:
 321                 c->cputype = CPU_R5432;
 322                 c->isa_level = MIPS_CPU_ISA_IV;
 323                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 324                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 325                 c->tlbsize = 48;
 326                 break;
 327         case PRID_IMP_R5500:
 328                 c->cputype = CPU_R5500;
 329                 c->isa_level = MIPS_CPU_ISA_IV;
 330                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 331                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 332                 c->tlbsize = 48;
 333                 break;
 334         case PRID_IMP_NEVADA:
 335                 c->cputype = CPU_NEVADA;
 336                 c->isa_level = MIPS_CPU_ISA_IV;
 337                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 338                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 339                 c->tlbsize = 48;
 340                 break;
 341         case PRID_IMP_R6000:
 342                 c->cputype = CPU_R6000;
 343                 c->isa_level = MIPS_CPU_ISA_II;
 344                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 345                              MIPS_CPU_LLSC;
 346                 c->tlbsize = 32;
 347                 break;
 348         case PRID_IMP_R6000A:
 349                 c->cputype = CPU_R6000A;
 350                 c->isa_level = MIPS_CPU_ISA_II;
 351                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 352                              MIPS_CPU_LLSC;
 353                 c->tlbsize = 32;
 354                 break;
 355         case PRID_IMP_RM7000:
 356                 c->cputype = CPU_RM7000;
 357                 c->isa_level = MIPS_CPU_ISA_IV;
 358                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 359                              MIPS_CPU_LLSC;
 360                 /*
 361                  * Undocumented RM7000:  Bit 29 in the info register of
 362                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 363                  * entries.
 364                  *
 365                  * 29      1 =>    64 entry JTLB
 366                  *         0 =>    48 entry JTLB
 367                  */
 368                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 369                 break;
 370         case PRID_IMP_RM9000:
 371                 c->cputype = CPU_RM9000;
 372                 c->isa_level = MIPS_CPU_ISA_IV;
 373                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 374                              MIPS_CPU_LLSC;
 375                 /*
 376                  * Bit 29 in the info register of the RM9000
 377                  * indicates if the TLB has 48 or 64 entries.
 378                  *
 379                  * 29      1 =>    64 entry JTLB
 380                  *         0 =>    48 entry JTLB
 381                  */
 382                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 383                 break;
 384         case PRID_IMP_R8000:
 385                 c->cputype = CPU_R8000;
 386                 c->isa_level = MIPS_CPU_ISA_IV;
 387                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 388                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 389                              MIPS_CPU_LLSC;
 390                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 391                 break;
 392         case PRID_IMP_R10000:
 393                 c->cputype = CPU_R10000;
 394                 c->isa_level = MIPS_CPU_ISA_IV;
 395                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 396                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 397                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 398                              MIPS_CPU_LLSC;
 399                 c->tlbsize = 64;
 400                 break;
 401         case PRID_IMP_R12000:
 402                 c->cputype = CPU_R12000;
 403                 c->isa_level = MIPS_CPU_ISA_IV;
 404                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 405                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 406                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 407                              MIPS_CPU_LLSC;
 408                 c->tlbsize = 64;
 409                 break;
 410         default:
 411                 c->cputype = CPU_UNKNOWN;
 412                 break;
 413         }
 414 }
 415
 416 static inline void decode_config1(struct cpuinfo_mips *c)
 417 {
 418         unsigned long config0 = read_c0_config();
 419         unsigned long config1;
 420
 421         if ((config0 & (1 << 31)) == 0)
 422                 return;                 /* actually wort a panic() */
 423
 424         /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
 425         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 426                 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 427                 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 428         config1 = read_c0_config1();
 429         if (config1 & (1 << 3))
 430                 c->options |= MIPS_CPU_WATCH;
 431         if (config1 & (1 << 2))
 432                 c->options |= MIPS_CPU_MIPS16;
 433         if (config1 & (1 << 1))
 434                 c->options |= MIPS_CPU_EJTAG;
 435         if (config1 & 1) {
 436                 c->options |= MIPS_CPU_FPU;
 437                 c->options |= MIPS_CPU_32FPR;
 438         }
 439         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 440
 441         c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
 442 }
 443
 444 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 445 {
 446         decode_config1(c);
 447         switch (c->processor_id & 0xff00) {
 448         case PRID_IMP_4KC:
 449                 c->cputype = CPU_4KC;
 450                 c->isa_level = MIPS_CPU_ISA_M32;
 451                 break;
 452         case PRID_IMP_4KEC:
 453                 c->cputype = CPU_4KEC;
 454                 c->isa_level = MIPS_CPU_ISA_M32;
 455                 break;
 456         case PRID_IMP_4KSC:
 457                 c->cputype = CPU_4KSC;
 458                 c->isa_level = MIPS_CPU_ISA_M32;
 459                 break;
 460         case PRID_IMP_5KC:
 461                 c->cputype = CPU_5KC;
 462                 c->isa_level = MIPS_CPU_ISA_M64;
 463                 break;
 464         case PRID_IMP_20KC:
 465                 c->cputype = CPU_20KC;
 466                 c->isa_level = MIPS_CPU_ISA_M64;
 467                 break;
 468         case PRID_IMP_24K:
 469                 c->cputype = CPU_24K;
 470                 c->isa_level = MIPS_CPU_ISA_M32;
 471                 break;
 472         case PRID_IMP_25KF:
 473                 c->cputype = CPU_25KF;
 474                 c->isa_level = MIPS_CPU_ISA_M64;
 475                 /* Probe for L2 cache */
 476                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 477                 break;
 478         default:
 479                 c->cputype = CPU_UNKNOWN;
 480                 break;
 481         }
 482 }
 483
 484 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 485 {
 486         decode_config1(c);
 487         switch (c->processor_id & 0xff00) {
 488         case PRID_IMP_AU1_REV1:
 489         case PRID_IMP_AU1_REV2:
 490                 switch ((c->processor_id >> 24) & 0xff) {
 491                 case 0:
 492                         c->cputype = CPU_AU1000;
 493                         break;
 494                 case 1:
 495                         c->cputype = CPU_AU1500;
 496                         break;
 497                 case 2:
 498                         c->cputype = CPU_AU1100;
 499                         break;
 500                 case 3:
 501                         c->cputype = CPU_AU1550;
 502                         break;
 503                 default:
 504                         panic("Unknown Au Core!");
 505                         break;
 506                 }
 507                 c->isa_level = MIPS_CPU_ISA_M32;
 508                 break;
 509         default:
 510                 c->cputype = CPU_UNKNOWN;
 511                 break;
 512         }
 513 }
 514
 515 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 516 {
 517         decode_config1(c);
 518         switch (c->processor_id & 0xff00) {
 519         case PRID_IMP_SB1:
 520                 c->cputype = CPU_SB1;
 521                 c->isa_level = MIPS_CPU_ISA_M64;
 522                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 523                              MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 524                              MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
 525                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 526 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
 527                 /* FPU in pass1 is known to have issues. */
 528                 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 529 #endif
 530                 break;
 531         default:
 532                 c->cputype = CPU_UNKNOWN;
 533                 break;
 534         }
 535 }
 536
 537 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 538 {
 539         decode_config1(c);
 540         switch (c->processor_id & 0xff00) {
 541         case PRID_IMP_SR71000:
 542                 c->cputype = CPU_SR71000;
 543                 c->isa_level = MIPS_CPU_ISA_M64;
 544                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 545                                     MIPS_CPU_4KTLB | MIPS_CPU_FPU |
 546                              MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
 547                 c->scache.ways = 8;
 548                 c->tlbsize = 64;
 549                 break;
 550         default:
 551                 c->cputype = CPU_UNKNOWN;
 552                 break;
 553         }
 554 }
 555
 556 __init void cpu_probe(void)
 557 {
 558         struct cpuinfo_mips *c = &current_cpu_data;
 559
 560         c->processor_id = PRID_IMP_UNKNOWN;
 561         c->fpu_id       = FPIR_IMP_NONE;
 562         c->cputype      = CPU_UNKNOWN;
 563
 564         c->processor_id = read_c0_prid();
 565         switch (c->processor_id & 0xff0000) {
 566
 567         case PRID_COMP_LEGACY:
 568                 cpu_probe_legacy(c);
 569                 break;
 570         case PRID_COMP_MIPS:
 571                 cpu_probe_mips(c);
 572                 break;
 573         case PRID_COMP_ALCHEMY:
 574                 cpu_probe_alchemy(c);
 575                 break;
 576         case PRID_COMP_SIBYTE:
 577                 cpu_probe_sibyte(c);
 578                 break;
 579
 580         case PRID_COMP_SANDCRAFT:
 581                 cpu_probe_sandcraft(c);
 582                 break;
 583         default:
 584                 c->cputype = CPU_UNKNOWN;
 585         }
 586         if (c->options & MIPS_CPU_FPU)
 587                 c->fpu_id = cpu_get_fpu_id();
 588 }
 589
 590 __init void cpu_report(void)
 591 {
 592         struct cpuinfo_mips *c = &current_cpu_data;
 593
 594         printk("CPU revision is: %08x\n", c->processor_id);
 595         if (c->options & MIPS_CPU_FPU)
 596                 printk("FPU revision is: %08x\n", c->fpu_id);
 597 }