fedora core 6 1.2949 + vserver 2.2.0
[linux-2.6.git] / arch / mips / kernel / ptrace.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1992 Ross Biro
7  * Copyright (C) Linus Torvalds
8  * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
9  * Copyright (C) 1996 David S. Miller
10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11  * Copyright (C) 1999 MIPS Technologies, Inc.
12  * Copyright (C) 2000 Ulf Carlsson
13  *
14  * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
15  * binaries.
16  */
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/mm.h>
21 #include <linux/errno.h>
22 #include <linux/ptrace.h>
23 #include <linux/audit.h>
24 #include <linux/smp.h>
25 #include <linux/smp_lock.h>
26 #include <linux/user.h>
27 #include <linux/security.h>
28 #include <linux/signal.h>
29 #include <linux/vs_base.h>
30
31 #include <asm/byteorder.h>
32 #include <asm/cpu.h>
33 #include <asm/dsp.h>
34 #include <asm/fpu.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/pgtable.h>
38 #include <asm/page.h>
39 #include <asm/system.h>
40 #include <asm/uaccess.h>
41 #include <asm/bootinfo.h>
42 #include <asm/reg.h>
43
44 /*
45  * Called by kernel/ptrace.c when detaching..
46  *
47  * Make sure single step bits etc are not set.
48  */
49 void ptrace_disable(struct task_struct *child)
50 {
51         /* Nothing to do.. */
52 }
53
54 /*
55  * Read a general register set.  We always use the 64-bit format, even
56  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
57  * Registers are sign extended to fill the available space.
58  */
59 int ptrace_getregs (struct task_struct *child, __s64 __user *data)
60 {
61         struct pt_regs *regs;
62         int i;
63
64         if (!access_ok(VERIFY_WRITE, data, 38 * 8))
65                 return -EIO;
66
67         regs = task_pt_regs(child);
68
69         for (i = 0; i < 32; i++)
70                 __put_user (regs->regs[i], data + i);
71         __put_user (regs->lo, data + EF_LO - EF_R0);
72         __put_user (regs->hi, data + EF_HI - EF_R0);
73         __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
74         __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
75         __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
76         __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
77
78         return 0;
79 }
80
81 /*
82  * Write a general register set.  As for PTRACE_GETREGS, we always use
83  * the 64-bit format.  On a 32-bit kernel only the lower order half
84  * (according to endianness) will be used.
85  */
86 int ptrace_setregs (struct task_struct *child, __s64 __user *data)
87 {
88         struct pt_regs *regs;
89         int i;
90
91         if (!access_ok(VERIFY_READ, data, 38 * 8))
92                 return -EIO;
93
94         regs = task_pt_regs(child);
95
96         for (i = 0; i < 32; i++)
97                 __get_user (regs->regs[i], data + i);
98         __get_user (regs->lo, data + EF_LO - EF_R0);
99         __get_user (regs->hi, data + EF_HI - EF_R0);
100         __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
101
102         /* badvaddr, status, and cause may not be written.  */
103
104         return 0;
105 }
106
107 int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
108 {
109         int i;
110         unsigned int tmp;
111
112         if (!access_ok(VERIFY_WRITE, data, 33 * 8))
113                 return -EIO;
114
115         if (tsk_used_math(child)) {
116                 fpureg_t *fregs = get_fpu_regs(child);
117                 for (i = 0; i < 32; i++)
118                         __put_user (fregs[i], i + (__u64 __user *) data);
119         } else {
120                 for (i = 0; i < 32; i++)
121                         __put_user ((__u64) -1, i + (__u64 __user *) data);
122         }
123
124         __put_user (child->thread.fpu.fcr31, data + 64);
125
126         preempt_disable();
127         if (cpu_has_fpu) {
128                 unsigned int flags;
129
130                 if (cpu_has_mipsmt) {
131                         unsigned int vpflags = dvpe();
132                         flags = read_c0_status();
133                         __enable_fpu();
134                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
135                         write_c0_status(flags);
136                         evpe(vpflags);
137                 } else {
138                         flags = read_c0_status();
139                         __enable_fpu();
140                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
141                         write_c0_status(flags);
142                 }
143         } else {
144                 tmp = 0;
145         }
146         preempt_enable();
147         __put_user (tmp, data + 65);
148
149         return 0;
150 }
151
152 int ptrace_setfpregs (struct task_struct *child, __u32 __user *data)
153 {
154         fpureg_t *fregs;
155         int i;
156
157         if (!access_ok(VERIFY_READ, data, 33 * 8))
158                 return -EIO;
159
160         fregs = get_fpu_regs(child);
161
162         for (i = 0; i < 32; i++)
163                 __get_user (fregs[i], i + (__u64 __user *) data);
164
165         __get_user (child->thread.fpu.fcr31, data + 64);
166
167         /* FIR may not be written.  */
168
169         return 0;
170 }
171
172 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
173 {
174         int ret;
175
176         if (!vx_check(vx_task_xid(child), VS_WATCH_P|VS_IDENT))
177                 goto out;
178
179         switch (request) {
180         /* when I and D space are separate, these will need to be fixed. */
181         case PTRACE_PEEKTEXT: /* read word at location addr. */
182         case PTRACE_PEEKDATA: {
183                 unsigned long tmp;
184                 int copied;
185
186                 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
187                 ret = -EIO;
188                 if (copied != sizeof(tmp))
189                         break;
190                 ret = put_user(tmp,(unsigned long __user *) data);
191                 break;
192         }
193
194         /* Read the word at location addr in the USER area. */
195         case PTRACE_PEEKUSR: {
196                 struct pt_regs *regs;
197                 unsigned long tmp = 0;
198
199                 regs = task_pt_regs(child);
200                 ret = 0;  /* Default return value. */
201
202                 switch (addr) {
203                 case 0 ... 31:
204                         tmp = regs->regs[addr];
205                         break;
206                 case FPR_BASE ... FPR_BASE + 31:
207                         if (tsk_used_math(child)) {
208                                 fpureg_t *fregs = get_fpu_regs(child);
209
210 #ifdef CONFIG_32BIT
211                                 /*
212                                  * The odd registers are actually the high
213                                  * order bits of the values stored in the even
214                                  * registers - unless we're using r2k_switch.S.
215                                  */
216                                 if (addr & 1)
217                                         tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
218                                 else
219                                         tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
220 #endif
221 #ifdef CONFIG_64BIT
222                                 tmp = fregs[addr - FPR_BASE];
223 #endif
224                         } else {
225                                 tmp = -1;       /* FP not yet used  */
226                         }
227                         break;
228                 case PC:
229                         tmp = regs->cp0_epc;
230                         break;
231                 case CAUSE:
232                         tmp = regs->cp0_cause;
233                         break;
234                 case BADVADDR:
235                         tmp = regs->cp0_badvaddr;
236                         break;
237                 case MMHI:
238                         tmp = regs->hi;
239                         break;
240                 case MMLO:
241                         tmp = regs->lo;
242                         break;
243                 case FPC_CSR:
244                         tmp = child->thread.fpu.fcr31;
245                         break;
246                 case FPC_EIR: { /* implementation / version register */
247                         unsigned int flags;
248 #ifdef CONFIG_MIPS_MT_SMTC
249                         unsigned int irqflags;
250                         unsigned int mtflags;
251 #endif /* CONFIG_MIPS_MT_SMTC */
252
253                         preempt_disable();
254                         if (!cpu_has_fpu) {
255                                 preempt_enable();
256                                 break;
257                         }
258
259 #ifdef CONFIG_MIPS_MT_SMTC
260                         /* Read-modify-write of Status must be atomic */
261                         local_irq_save(irqflags);
262                         mtflags = dmt();
263 #endif /* CONFIG_MIPS_MT_SMTC */
264                         if (cpu_has_mipsmt) {
265                                 unsigned int vpflags = dvpe();
266                                 flags = read_c0_status();
267                                 __enable_fpu();
268                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
269                                 write_c0_status(flags);
270                                 evpe(vpflags);
271                         } else {
272                                 flags = read_c0_status();
273                                 __enable_fpu();
274                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
275                                 write_c0_status(flags);
276                         }
277 #ifdef CONFIG_MIPS_MT_SMTC
278                         emt(mtflags);
279                         local_irq_restore(irqflags);
280 #endif /* CONFIG_MIPS_MT_SMTC */
281                         preempt_enable();
282                         break;
283                 }
284                 case DSP_BASE ... DSP_BASE + 5: {
285                         dspreg_t *dregs;
286
287                         if (!cpu_has_dsp) {
288                                 tmp = 0;
289                                 ret = -EIO;
290                                 goto out;
291                         }
292                         dregs = __get_dsp_regs(child);
293                         tmp = (unsigned long) (dregs[addr - DSP_BASE]);
294                         break;
295                 }
296                 case DSP_CONTROL:
297                         if (!cpu_has_dsp) {
298                                 tmp = 0;
299                                 ret = -EIO;
300                                 goto out;
301                         }
302                         tmp = child->thread.dsp.dspcontrol;
303                         break;
304                 default:
305                         tmp = 0;
306                         ret = -EIO;
307                         goto out;
308                 }
309                 ret = put_user(tmp, (unsigned long __user *) data);
310                 break;
311         }
312
313         /* when I and D space are separate, this will have to be fixed. */
314         case PTRACE_POKETEXT: /* write the word at location addr. */
315         case PTRACE_POKEDATA:
316                 ret = 0;
317                 if (access_process_vm(child, addr, &data, sizeof(data), 1)
318                     == sizeof(data))
319                         break;
320                 ret = -EIO;
321                 break;
322
323         case PTRACE_POKEUSR: {
324                 struct pt_regs *regs;
325                 ret = 0;
326                 regs = task_pt_regs(child);
327
328                 switch (addr) {
329                 case 0 ... 31:
330                         regs->regs[addr] = data;
331                         break;
332                 case FPR_BASE ... FPR_BASE + 31: {
333                         fpureg_t *fregs = get_fpu_regs(child);
334
335                         if (!tsk_used_math(child)) {
336                                 /* FP not yet used  */
337                                 memset(&child->thread.fpu, ~0,
338                                        sizeof(child->thread.fpu));
339                                 child->thread.fpu.fcr31 = 0;
340                         }
341 #ifdef CONFIG_32BIT
342                         /*
343                          * The odd registers are actually the high order bits
344                          * of the values stored in the even registers - unless
345                          * we're using r2k_switch.S.
346                          */
347                         if (addr & 1) {
348                                 fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
349                                 fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
350                         } else {
351                                 fregs[addr - FPR_BASE] &= ~0xffffffffLL;
352                                 fregs[addr - FPR_BASE] |= data;
353                         }
354 #endif
355 #ifdef CONFIG_64BIT
356                         fregs[addr - FPR_BASE] = data;
357 #endif
358                         break;
359                 }
360                 case PC:
361                         regs->cp0_epc = data;
362                         break;
363                 case MMHI:
364                         regs->hi = data;
365                         break;
366                 case MMLO:
367                         regs->lo = data;
368                         break;
369                 case FPC_CSR:
370                         child->thread.fpu.fcr31 = data;
371                         break;
372                 case DSP_BASE ... DSP_BASE + 5: {
373                         dspreg_t *dregs;
374
375                         if (!cpu_has_dsp) {
376                                 ret = -EIO;
377                                 break;
378                         }
379
380                         dregs = __get_dsp_regs(child);
381                         dregs[addr - DSP_BASE] = data;
382                         break;
383                 }
384                 case DSP_CONTROL:
385                         if (!cpu_has_dsp) {
386                                 ret = -EIO;
387                                 break;
388                         }
389                         child->thread.dsp.dspcontrol = data;
390                         break;
391                 default:
392                         /* The rest are not allowed. */
393                         ret = -EIO;
394                         break;
395                 }
396                 break;
397                 }
398
399         case PTRACE_GETREGS:
400                 ret = ptrace_getregs (child, (__u64 __user *) data);
401                 break;
402
403         case PTRACE_SETREGS:
404                 ret = ptrace_setregs (child, (__u64 __user *) data);
405                 break;
406
407         case PTRACE_GETFPREGS:
408                 ret = ptrace_getfpregs (child, (__u32 __user *) data);
409                 break;
410
411         case PTRACE_SETFPREGS:
412                 ret = ptrace_setfpregs (child, (__u32 __user *) data);
413                 break;
414
415         case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
416         case PTRACE_CONT: { /* restart after signal. */
417                 ret = -EIO;
418                 if (!valid_signal(data))
419                         break;
420                 if (request == PTRACE_SYSCALL) {
421                         set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
422                 }
423                 else {
424                         clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
425                 }
426                 child->exit_code = data;
427                 wake_up_process(child);
428                 ret = 0;
429                 break;
430         }
431
432         /*
433          * make the child exit.  Best I can do is send it a sigkill.
434          * perhaps it should be put in the status that it wants to
435          * exit.
436          */
437         case PTRACE_KILL:
438                 ret = 0;
439                 if (child->exit_state == EXIT_ZOMBIE)   /* already dead */
440                         break;
441                 child->exit_code = SIGKILL;
442                 wake_up_process(child);
443                 break;
444
445         case PTRACE_DETACH: /* detach a process that was attached. */
446                 ret = ptrace_detach(child, data);
447                 break;
448
449         case PTRACE_GET_THREAD_AREA:
450                 ret = put_user(task_thread_info(child)->tp_value,
451                                 (unsigned long __user *) data);
452                 break;
453
454         default:
455                 ret = ptrace_request(child, request, addr, data);
456                 break;
457         }
458  out:
459         return ret;
460 }
461
462 static inline int audit_arch(void)
463 {
464         int arch = EM_MIPS;
465 #ifdef CONFIG_64BIT
466         arch |=  __AUDIT_ARCH_64BIT;
467 #endif
468 #if defined(__LITTLE_ENDIAN)
469         arch |=  __AUDIT_ARCH_LE;
470 #endif
471         return arch;
472 }
473
474 /*
475  * Notification of system call entry/exit
476  * - triggered by current->work.syscall_trace
477  */
478 asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
479 {
480         if (unlikely(current->audit_context) && entryexit)
481                 audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
482                                    regs->regs[2]);
483
484         if (test_thread_flag(TIF_SYSCALL_TRACE))
485                 tracehook_report_syscall(regs, entryexit);
486
487         if (unlikely(current->audit_context) && !entryexit)
488                 audit_syscall_entry(audit_arch(), regs->regs[2],
489                                     regs->regs[4], regs->regs[5],
490                                     regs->regs[6], regs->regs[7]);
491 }