2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * Setting up the clock on the MIPS boards.
21 #include <linux/types.h>
22 #include <linux/config.h>
23 #include <linux/init.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sched.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/time.h>
29 #include <linux/timex.h>
30 #include <linux/mc146818rtc.h>
32 #include <asm/mipsregs.h>
33 #include <asm/ptrace.h>
34 #include <asm/hardirq.h>
35 #include <asm/div64.h>
38 #include <asm/mc146818-time.h>
40 #include <asm/mips-boards/generic.h>
41 #include <asm/mips-boards/prom.h>
43 unsigned long cpu_khz;
45 #if defined(CONFIG_MIPS_SEAD)
46 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5)
48 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
51 #if defined(CONFIG_MIPS_ATLAS)
52 static char display_string[] = " LINUX ON ATLAS ";
54 #if defined(CONFIG_MIPS_MALTA)
55 static char display_string[] = " LINUX ON MALTA ";
57 #if defined(CONFIG_MIPS_SEAD)
58 static char display_string[] = " LINUX ON SEAD ";
60 static unsigned int display_count = 0;
61 #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
63 #define MIPS_CPU_TIMER_IRQ (NR_IRQS-1)
65 static unsigned int timer_tick_count=0;
67 void mips_timer_interrupt(struct pt_regs *regs)
69 if ((timer_tick_count++ % HZ) == 0) {
70 mips_display_message(&display_string[display_count++]);
71 if (display_count == MAX_DISPLAY_COUNT)
76 ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs);
80 * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect
82 static unsigned int __init estimate_cpu_frequency(void)
84 unsigned int prid = read_c0_prid() & 0xffff00;
87 #ifdef CONFIG_MIPS_SEAD
89 * The SEAD board doesn't have a real time clock, so we can't
90 * really calculate the timer frequency
91 * For now we hardwire the SEAD board frequency to 12MHz.
94 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
95 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
100 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
103 local_irq_save(flags);
105 /* Start counter exactly on falling edge of update flag */
106 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
107 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
109 /* Start r4k counter. */
112 /* Read counter exactly on falling edge of update flag */
113 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
114 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
116 count = read_c0_count();
118 /* restore interrupts */
119 local_irq_restore(flags);
122 mips_hpt_frequency = count;
123 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
124 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
127 count += 5000; /* round */
128 count -= count%10000;
133 unsigned long __init mips_rtc_get_time(void)
135 return mc146818_get_cmos_time();
138 void __init mips_time_init(void)
140 unsigned int est_freq, flags;
142 local_irq_save(flags);
144 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
145 /* Set Data mode - binary. */
146 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
149 est_freq = estimate_cpu_frequency ();
151 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
152 (est_freq%1000000)*100/1000000);
154 cpu_khz = est_freq / 1000;
156 local_irq_restore(flags);
159 void __init mips_timer_setup(struct irqaction *irq)
161 /* we are using the cpu counter for timer interrupts */
162 irq->handler = no_action; /* we use our own handler */
163 setup_irq(MIPS_CPU_TIMER_IRQ, irq);
165 /* to generate the first timer interrupt */
166 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
167 set_c0_status(ALLINTS);