arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cacheops.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/io.h>
  23 #include <asm/page.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/r4kcache.h>
  26 #include <asm/system.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/war.h>
  29
  30 static unsigned long icache_size, dcache_size, scache_size;
  31
  32 /*
  33  * Dummy cache handling routines for machines without boardcaches
  34  */
  35 static void no_sc_noop(void) {}
  36
  37 static struct bcache_ops no_sc_ops = {
  38         .bc_enable = (void *)no_sc_noop,
  39         .bc_disable = (void *)no_sc_noop,
  40         .bc_wback_inv = (void *)no_sc_noop,
  41         .bc_inv = (void *)no_sc_noop
  42 };
  43
  44 struct bcache_ops *bcops = &no_sc_ops;
  45
  46 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x2010)
  47 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x2020)
  48
  49 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  50 do {                                                                    \
  51         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  52                 *(volatile unsigned long *)KSEG1;                       \
  53         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  54                 __asm__ __volatile__("nop;nop;nop;nop");                \
  55 } while (0)
  56
  57 static void (*r4k_blast_dcache_page)(unsigned long addr);
  58
  59 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  60 {
  61         R4600_HIT_CACHEOP_WAR_IMPL;
  62         blast_dcache32_page(addr);
  63 }
  64
  65 static inline void r4k_blast_dcache_page_setup(void)
  66 {
  67         unsigned long  dc_lsize = cpu_dcache_line_size();
  68
  69         if (dc_lsize == 16)
  70                 r4k_blast_dcache_page = blast_dcache16_page;
  71         else if (dc_lsize == 32)
  72                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  73 }
  74
  75 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  76
  77 static inline void r4k_blast_dcache_page_indexed_setup(void)
  78 {
  79         unsigned long dc_lsize = cpu_dcache_line_size();
  80
  81         if (dc_lsize == 16)
  82                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  83         else if (dc_lsize == 32)
  84                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  85 }
  86
  87 static void (* r4k_blast_dcache)(void);
  88
  89 static void r4k_blast_dcache_setup(void)
  90 {
  91         unsigned long dc_lsize = cpu_dcache_line_size();
  92
  93         if (dc_lsize == 16)
  94                 r4k_blast_dcache = blast_dcache16;
  95         else if (dc_lsize == 32)
  96                 r4k_blast_dcache = blast_dcache32;
  97 }
  98
  99 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 100 #define JUMP_TO_ALIGN(order) \
 101         __asm__ __volatile__( \
 102                 "b\t1f\n\t" \
 103                 ".align\t" #order "\n\t" \
 104                 "1:\n\t" \
 105                 )
 106 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 107 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 108
 109 static inline void blast_r4600_v1_icache32(void)
 110 {
 111         unsigned long flags;
 112
 113         local_irq_save(flags);
 114         blast_icache32();
 115         local_irq_restore(flags);
 116 }
 117
 118 static inline void tx49_blast_icache32(void)
 119 {
 120         unsigned long start = INDEX_BASE;
 121         unsigned long end = start + current_cpu_data.icache.waysize;
 122         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 123         unsigned long ws_end = current_cpu_data.icache.ways <<
 124                                current_cpu_data.icache.waybit;
 125         unsigned long ws, addr;
 126
 127         CACHE32_UNROLL32_ALIGN2;
 128         /* I'm in even chunk.  blast odd chunks */
 129         for (ws = 0; ws < ws_end; ws += ws_inc)
 130                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 131                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 132         CACHE32_UNROLL32_ALIGN;
 133         /* I'm in odd chunk.  blast even chunks */
 134         for (ws = 0; ws < ws_end; ws += ws_inc)
 135                 for (addr = start; addr < end; addr += 0x400 * 2)
 136                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 137 }
 138
 139 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 140 {
 141         unsigned long flags;
 142
 143         local_irq_save(flags);
 144         blast_icache32_page_indexed(page);
 145         local_irq_restore(flags);
 146 }
 147
 148 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 149 {
 150         unsigned long start = page;
 151         unsigned long end = start + PAGE_SIZE;
 152         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 153         unsigned long ws_end = current_cpu_data.icache.ways <<
 154                                current_cpu_data.icache.waybit;
 155         unsigned long ws, addr;
 156
 157         CACHE32_UNROLL32_ALIGN2;
 158         /* I'm in even chunk.  blast odd chunks */
 159         for (ws = 0; ws < ws_end; ws += ws_inc)
 160                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 161                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 162         CACHE32_UNROLL32_ALIGN;
 163         /* I'm in odd chunk.  blast even chunks */
 164         for (ws = 0; ws < ws_end; ws += ws_inc)
 165                 for (addr = start; addr < end; addr += 0x400 * 2)
 166                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 167 }
 168
 169 static void (* r4k_blast_icache_page)(unsigned long addr);
 170
 171 static inline void r4k_blast_icache_page_setup(void)
 172 {
 173         unsigned long ic_lsize = cpu_icache_line_size();
 174
 175         if (ic_lsize == 16)
 176                 r4k_blast_icache_page = blast_icache16_page;
 177         else if (ic_lsize == 32)
 178                 r4k_blast_icache_page = blast_icache32_page;
 179         else if (ic_lsize == 64)
 180                 r4k_blast_icache_page = blast_icache64_page;
 181 }
 182
 183
 184 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 185
 186 static inline void r4k_blast_icache_page_indexed_setup(void)
 187 {
 188         unsigned long ic_lsize = cpu_icache_line_size();
 189
 190         if (ic_lsize == 16)
 191                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 192         else if (ic_lsize == 32) {
 193                 if (TX49XX_ICACHE_INDEX_INV_WAR)
 194                         r4k_blast_icache_page_indexed =
 195                                 tx49_blast_icache32_page_indexed;
 196                 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 197                         r4k_blast_icache_page_indexed =
 198                                 blast_icache32_r4600_v1_page_indexed;
 199                 else
 200                         r4k_blast_icache_page_indexed =
 201                                 blast_icache32_page_indexed;
 202         } else if (ic_lsize == 64)
 203                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 204 }
 205
 206 static void (* r4k_blast_icache)(void);
 207
 208 static inline void r4k_blast_icache_setup(void)
 209 {
 210         unsigned long ic_lsize = cpu_icache_line_size();
 211
 212         if (ic_lsize == 16)
 213                 r4k_blast_icache = blast_icache16;
 214         else if (ic_lsize == 32) {
 215                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 216                         r4k_blast_icache = blast_r4600_v1_icache32;
 217                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 218                         r4k_blast_icache = tx49_blast_icache32;
 219                 else
 220                         r4k_blast_icache = blast_icache32;
 221         } else if (ic_lsize == 64)
 222                 r4k_blast_icache = blast_icache64;
 223 }
 224
 225 static void (* r4k_blast_scache_page)(unsigned long addr);
 226
 227 static inline void r4k_blast_scache_page_setup(void)
 228 {
 229         unsigned long sc_lsize = cpu_scache_line_size();
 230
 231         if (sc_lsize == 16)
 232                 r4k_blast_scache_page = blast_scache16_page;
 233         else if (sc_lsize == 32)
 234                 r4k_blast_scache_page = blast_scache32_page;
 235         else if (sc_lsize == 64)
 236                 r4k_blast_scache_page = blast_scache64_page;
 237         else if (sc_lsize == 128)
 238                 r4k_blast_scache_page = blast_scache128_page;
 239 }
 240
 241 static void (* r4k_blast_scache)(void);
 242
 243 static inline void r4k_blast_scache_setup(void)
 244 {
 245         unsigned long sc_lsize = cpu_scache_line_size();
 246
 247         if (sc_lsize == 16)
 248                 r4k_blast_scache = blast_scache16;
 249         else if (sc_lsize == 32)
 250                 r4k_blast_scache = blast_scache32;
 251         else if (sc_lsize == 64)
 252                 r4k_blast_scache = blast_scache64;
 253         else if (sc_lsize == 128)
 254                 r4k_blast_scache = blast_scache128;
 255 }
 256
 257 static void r4k_flush_cache_all(void)
 258 {
 259         if (!cpu_has_dc_aliases)
 260                 return;
 261
 262         r4k_blast_dcache();
 263         r4k_blast_icache();
 264 }
 265
 266 static void r4k___flush_cache_all(void)
 267 {
 268         r4k_blast_dcache();
 269         r4k_blast_icache();
 270
 271         switch (current_cpu_data.cputype) {
 272         case CPU_R4000SC:
 273         case CPU_R4000MC:
 274         case CPU_R4400SC:
 275         case CPU_R4400MC:
 276         case CPU_R10000:
 277         case CPU_R12000:
 278                 r4k_blast_scache();
 279         }
 280 }
 281
 282 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 283         unsigned long start, unsigned long end)
 284 {
 285         int exec;
 286
 287         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 288                 return;
 289
 290         exec = vma->vm_flags & VM_EXEC;
 291         if (cpu_has_dc_aliases || exec)
 292                 r4k_blast_dcache();
 293         if (exec)
 294                 r4k_blast_icache();
 295 }
 296
 297 static void r4k_flush_cache_mm(struct mm_struct *mm)
 298 {
 299         if (!cpu_has_dc_aliases)
 300                 return;
 301
 302         if (!cpu_context(smp_processor_id(), mm))
 303                 return;
 304
 305         r4k_blast_dcache();
 306         r4k_blast_icache();
 307
 308         /*
 309          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 310          * only flush the primary caches but R10000 and R12000 behave sane ...
 311          */
 312         if (current_cpu_data.cputype == CPU_R4000SC ||
 313             current_cpu_data.cputype == CPU_R4000MC ||
 314             current_cpu_data.cputype == CPU_R4400SC ||
 315             current_cpu_data.cputype == CPU_R4400MC)
 316                 r4k_blast_scache();
 317 }
 318
 319 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 320                                         unsigned long page)
 321 {
 322         int exec = vma->vm_flags & VM_EXEC;
 323         struct mm_struct *mm = vma->vm_mm;
 324         pgd_t *pgdp;
 325         pmd_t *pmdp;
 326         pte_t *ptep;
 327
 328         /*
 329          * If ownes no valid ASID yet, cannot possibly have gotten
 330          * this page into the cache.
 331          */
 332         if (cpu_context(smp_processor_id(), mm) == 0)
 333                 return;
 334
 335         page &= PAGE_MASK;
 336         pgdp = pgd_offset(mm, page);
 337         pmdp = pmd_offset(pgdp, page);
 338         ptep = pte_offset(pmdp, page);
 339
 340         /*
 341          * If the page isn't marked valid, the page cannot possibly be
 342          * in the cache.
 343          */
 344         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 345                 return;
 346
 347         /*
 348          * Doing flushes for another ASID than the current one is
 349          * too difficult since stupid R4k caches do a TLB translation
 350          * for every cache flush operation.  So we do indexed flushes
 351          * in that case, which doesn't overly flush the cache too much.
 352          */
 353         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 354                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 355                         r4k_blast_dcache_page(page);
 356                 if (exec)
 357                         r4k_blast_icache_page(page);
 358
 359                 return;
 360         }
 361
 362         /*
 363          * Do indexed flush, too much work to get the (possible) TLB refills
 364          * to work correctly.
 365          */
 366         page = INDEX_BASE + (page & (dcache_size - 1));
 367         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 368                 r4k_blast_dcache_page_indexed(page);
 369         if (exec) {
 370                 if (cpu_has_vtag_icache) {
 371                         int cpu = smp_processor_id();
 372
 373                         if (cpu_context(cpu, vma->vm_mm) != 0)
 374                                 drop_mmu_context(vma->vm_mm, cpu);
 375                 } else
 376                         r4k_blast_icache_page_indexed(page);
 377         }
 378 }
 379
 380 static void r4k_flush_data_cache_page(unsigned long addr)
 381 {
 382         r4k_blast_dcache_page(addr);
 383 }
 384
 385 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 386 {
 387         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 388         unsigned long addr, aend;
 389
 390         if (!cpu_has_ic_fills_f_dc) {
 391                 if (end - start > dcache_size)
 392                         r4k_blast_dcache();
 393                 else {
 394                         addr = start & ~(dc_lsize - 1);
 395                         aend = (end - 1) & ~(dc_lsize - 1);
 396
 397                         while (1) {
 398                                 /* Hit_Writeback_Inv_D */
 399                                 protected_writeback_dcache_line(addr);
 400                                 if (addr == aend)
 401                                         break;
 402                                 addr += dc_lsize;
 403                         }
 404                 }
 405         }
 406
 407         if (end - start > icache_size)
 408                 r4k_blast_icache();
 409         else {
 410                 addr = start & ~(dc_lsize - 1);
 411                 aend = (end - 1) & ~(dc_lsize - 1);
 412                 while (1) {
 413                         /* Hit_Invalidate_I */
 414                         protected_flush_icache_line(addr);
 415                         if (addr == aend)
 416                                 break;
 417                         addr += dc_lsize;
 418                 }
 419         }
 420 }
 421
 422 /*
 423  * Ok, this seriously sucks.  We use them to flush a user page but don't
 424  * know the virtual address, so we have to blast away the whole icache
 425  * which is significantly more expensive than the real thing.  Otoh we at
 426  * least know the kernel address of the page so we can flush it
 427  * selectivly.
 428  */
 429 static void r4k_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 430 {
 431         /*
 432          * If there's no context yet, or the page isn't executable, no icache
 433          * flush is needed.
 434          */
 435         if (!(vma->vm_flags & VM_EXEC))
 436                 return;
 437
 438         /*
 439          * Tricky ...  Because we don't know the virtual address we've got the
 440          * choice of either invalidating the entire primary and secondary
 441          * caches or invalidating the secondary caches also.  With the subset
 442          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 443          * secondary cache will result in any entries in the primary caches
 444          * also getting invalidated which hopefully is a bit more economical.
 445          */
 446         if (cpu_has_subset_pcaches) {
 447                 unsigned long addr = (unsigned long) page_address(page);
 448
 449                 r4k_blast_scache_page(addr);
 450                 ClearPageDcacheDirty(page);
 451
 452                 return;
 453         }
 454
 455         if (!cpu_has_ic_fills_f_dc) {
 456                 unsigned long addr = (unsigned long) page_address(page);
 457                 r4k_blast_dcache_page(addr);
 458                 ClearPageDcacheDirty(page);
 459         }
 460
 461         /*
 462          * We're not sure of the virtual address(es) involved here, so
 463          * we have to flush the entire I-cache.
 464          */
 465         if (cpu_has_vtag_icache) {
 466                 int cpu = smp_processor_id();
 467
 468                 if (cpu_context(cpu, vma->vm_mm) != 0)
 469                         drop_mmu_context(vma->vm_mm, cpu);
 470         } else
 471                 r4k_blast_icache();
 472 }
 473
 474 #ifdef CONFIG_DMA_NONCOHERENT
 475
 476 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 477 {
 478         unsigned long end, a;
 479
 480         /* Catch bad driver code */
 481         BUG_ON(size == 0);
 482
 483         if (cpu_has_subset_pcaches) {
 484                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 485
 486                 if (size >= scache_size) {
 487                         r4k_blast_scache();
 488                         return;
 489                 }
 490
 491                 a = addr & ~(sc_lsize - 1);
 492                 end = (addr + size - 1) & ~(sc_lsize - 1);
 493                 while (1) {
 494                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 495                         if (a == end)
 496                                 break;
 497                         a += sc_lsize;
 498                 }
 499                 return;
 500         }
 501
 502         /*
 503          * Either no secondary cache or the available caches don't have the
 504          * subset property so we have to flush the primary caches
 505          * explicitly
 506          */
 507         if (size >= dcache_size) {
 508                 r4k_blast_dcache();
 509         } else {
 510                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 511
 512                 R4600_HIT_CACHEOP_WAR_IMPL;
 513                 a = addr & ~(dc_lsize - 1);
 514                 end = (addr + size - 1) & ~(dc_lsize - 1);
 515                 while (1) {
 516                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 517                         if (a == end)
 518                                 break;
 519                         a += dc_lsize;
 520                 }
 521         }
 522
 523         bc_wback_inv(addr, size);
 524 }
 525
 526 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 527 {
 528         unsigned long end, a;
 529
 530         /* Catch bad driver code */
 531         BUG_ON(size == 0);
 532
 533         if (cpu_has_subset_pcaches) {
 534                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 535
 536                 if (size >= scache_size) {
 537                         r4k_blast_scache();
 538                         return;
 539                 }
 540
 541                 a = addr & ~(sc_lsize - 1);
 542                 end = (addr + size - 1) & ~(sc_lsize - 1);
 543                 while (1) {
 544                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 545                         if (a == end)
 546                                 break;
 547                         a += sc_lsize;
 548                 }
 549                 return;
 550         }
 551
 552         if (size >= dcache_size) {
 553                 r4k_blast_dcache();
 554         } else {
 555                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 556
 557                 R4600_HIT_CACHEOP_WAR_IMPL;
 558                 a = addr & ~(dc_lsize - 1);
 559                 end = (addr + size - 1) & ~(dc_lsize - 1);
 560                 while (1) {
 561                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 562                         if (a == end)
 563                                 break;
 564                         a += dc_lsize;
 565                 }
 566         }
 567
 568         bc_inv(addr, size);
 569 }
 570 #endif /* CONFIG_DMA_NONCOHERENT */
 571
 572 /*
 573  * While we're protected against bad userland addresses we don't care
 574  * very much about what happens in that case.  Usually a segmentation
 575  * fault will dump the process later on anyway ...
 576  */
 577 static void r4k_flush_cache_sigtramp(unsigned long addr)
 578 {
 579         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 580         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 581
 582         R4600_HIT_CACHEOP_WAR_IMPL;
 583         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 584         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 585         if (MIPS4K_ICACHE_REFILL_WAR) {
 586                 __asm__ __volatile__ (
 587                         ".set push\n\t"
 588                         ".set noat\n\t"
 589                         ".set mips3\n\t"
 590 #if CONFIG_MIPS32
 591                         "la     $at,1f\n\t"
 592 #endif
 593 #if CONFIG_MIPS64
 594                         "dla    $at,1f\n\t"
 595 #endif
 596                         "cache  %0,($at)\n\t"
 597                         "nop; nop; nop\n"
 598                         "1:\n\t"
 599                         ".set pop"
 600                         :
 601                         : "i" (Hit_Invalidate_I));
 602         }
 603         if (MIPS_CACHE_SYNC_WAR)
 604                 __asm__ __volatile__ ("sync");
 605 }
 606
 607 static void r4k_flush_icache_all(void)
 608 {
 609         if (cpu_has_vtag_icache)
 610                 r4k_blast_icache();
 611 }
 612
 613 static inline void rm7k_erratum31(void)
 614 {
 615         const unsigned long ic_lsize = 32;
 616         unsigned long addr;
 617
 618         /* RM7000 erratum #31. The icache is screwed at startup. */
 619         write_c0_taglo(0);
 620         write_c0_taghi(0);
 621
 622         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 623                 __asm__ __volatile__ (
 624                         ".set noreorder\n\t"
 625                         ".set mips3\n\t"
 626                         "cache\t%1, 0(%0)\n\t"
 627                         "cache\t%1, 0x1000(%0)\n\t"
 628                         "cache\t%1, 0x2000(%0)\n\t"
 629                         "cache\t%1, 0x3000(%0)\n\t"
 630                         "cache\t%2, 0(%0)\n\t"
 631                         "cache\t%2, 0x1000(%0)\n\t"
 632                         "cache\t%2, 0x2000(%0)\n\t"
 633                         "cache\t%2, 0x3000(%0)\n\t"
 634                         "cache\t%1, 0(%0)\n\t"
 635                         "cache\t%1, 0x1000(%0)\n\t"
 636                         "cache\t%1, 0x2000(%0)\n\t"
 637                         "cache\t%1, 0x3000(%0)\n\t"
 638                         ".set\tmips0\n\t"
 639                         ".set\treorder\n\t"
 640                         :
 641                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 642         }
 643 }
 644
 645 static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way",
 646         "5-way", "6-way", "7-way", "8-way"
 647 };
 648
 649 static void __init probe_pcache(void)
 650 {
 651         struct cpuinfo_mips *c = &current_cpu_data;
 652         unsigned int config = read_c0_config();
 653         unsigned int prid = read_c0_prid();
 654         unsigned long config1;
 655         unsigned int lsize;
 656
 657         switch (c->cputype) {
 658         case CPU_R4600:                 /* QED style two way caches? */
 659         case CPU_R4700:
 660         case CPU_R5000:
 661         case CPU_NEVADA:
 662                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 663                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 664                 c->icache.ways = 2;
 665                 c->icache.waybit = ffs(icache_size/2) - 1;
 666
 667                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 668                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 669                 c->dcache.ways = 2;
 670                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 671
 672                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 673                 break;
 674
 675         case CPU_R5432:
 676         case CPU_R5500:
 677                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 678                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 679                 c->icache.ways = 2;
 680                 c->icache.waybit= 0;
 681
 682                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 683                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 684                 c->dcache.ways = 2;
 685                 c->dcache.waybit = 0;
 686
 687                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 688                 break;
 689
 690         case CPU_TX49XX:
 691                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 692                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 693                 c->icache.ways = 4;
 694                 c->icache.waybit= 0;
 695
 696                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 697                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 698                 c->dcache.ways = 4;
 699                 c->dcache.waybit = 0;
 700
 701                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 702                 break;
 703
 704         case CPU_R4000PC:
 705         case CPU_R4000SC:
 706         case CPU_R4000MC:
 707         case CPU_R4400PC:
 708         case CPU_R4400SC:
 709         case CPU_R4400MC:
 710         case CPU_R4300:
 711                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 712                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 713                 c->icache.ways = 1;
 714                 c->icache.waybit = 0;   /* doesn't matter */
 715
 716                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 717                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 718                 c->dcache.ways = 1;
 719                 c->dcache.waybit = 0;   /* does not matter */
 720
 721                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 722                 break;
 723
 724         case CPU_R10000:
 725         case CPU_R12000:
 726                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 727                 c->icache.linesz = 64;
 728                 c->icache.ways = 2;
 729                 c->icache.waybit = 0;
 730
 731                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 732                 c->dcache.linesz = 32;
 733                 c->dcache.ways = 2;
 734                 c->dcache.waybit = 0;
 735
 736                 c->options |= MIPS_CPU_PREFETCH;
 737                 break;
 738
 739         case CPU_VR4133:
 740                 write_c0_config(config & ~CONF_EB);
 741         case CPU_VR4131:
 742                 /* Workaround for cache instruction bug of VR4131 */
 743                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 744                     c->processor_id == 0x0c82U) {
 745                         config &= ~0x00000030U;
 746                         config |= 0x00410000U;
 747                         write_c0_config(config);
 748                 }
 749                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 750                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 751                 c->icache.ways = 2;
 752                 c->icache.waybit = ffs(icache_size/2) - 1;
 753
 754                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 755                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 756                 c->dcache.ways = 2;
 757                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 758
 759                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 760                 break;
 761
 762         case CPU_VR41XX:
 763         case CPU_VR4111:
 764         case CPU_VR4121:
 765         case CPU_VR4122:
 766         case CPU_VR4181:
 767         case CPU_VR4181A:
 768                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 769                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 770                 c->icache.ways = 1;
 771                 c->icache.waybit = 0;   /* doesn't matter */
 772
 773                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 774                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 775                 c->dcache.ways = 1;
 776                 c->dcache.waybit = 0;   /* does not matter */
 777
 778                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 779                 break;
 780
 781         case CPU_RM7000:
 782                 rm7k_erratum31();
 783
 784         case CPU_RM9000:
 785                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 786                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 787                 c->icache.ways = 4;
 788                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 789
 790                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 791                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 792                 c->dcache.ways = 4;
 793                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 794
 795 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 796                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 797 #endif
 798                 c->options |= MIPS_CPU_PREFETCH;
 799                 break;
 800
 801         default:
 802                 if (!(config & MIPS_CONF_M))
 803                         panic("Don't know how to probe P-caches on this cpu.");
 804
 805                 /*
 806                  * So we seem to be a MIPS32 or MIPS64 CPU
 807                  * So let's probe the I-cache ...
 808                  */
 809                 config1 = read_c0_config1();
 810
 811                 if ((lsize = ((config1 >> 19) & 7)))
 812                         c->icache.linesz = 2 << lsize;
 813                 else
 814                         c->icache.linesz = lsize;
 815                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 816                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 817
 818                 icache_size = c->icache.sets *
 819                               c->icache.ways *
 820                               c->icache.linesz;
 821                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 822
 823                 if (config & 0x8)               /* VI bit */
 824                         c->icache.flags |= MIPS_CACHE_VTAG;
 825
 826                 /*
 827                  * Now probe the MIPS32 / MIPS64 data cache.
 828                  */
 829                 c->dcache.flags = 0;
 830
 831                 if ((lsize = ((config1 >> 10) & 7)))
 832                         c->dcache.linesz = 2 << lsize;
 833                 else
 834                         c->dcache.linesz= lsize;
 835                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 836                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 837
 838                 dcache_size = c->dcache.sets *
 839                               c->dcache.ways *
 840                               c->dcache.linesz;
 841                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 842
 843                 c->options |= MIPS_CPU_PREFETCH;
 844                 break;
 845         }
 846
 847         /*
 848          * Processor configuration sanity check for the R4000SC erratum
 849          * #5.  With page sizes larger than 32kB there is no possibility
 850          * to get a VCE exception anymore so we don't care about this
 851          * misconfiguration.  The case is rather theoretical anyway;
 852          * presumably no vendor is shipping his hardware in the "bad"
 853          * configuration.
 854          */
 855         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
 856             !(config & CONF_SC) && c->icache.linesz != 16 &&
 857             PAGE_SIZE <= 0x8000)
 858                 panic("Improper R4000SC processor configuration detected");
 859
 860         /* compute a couple of other cache variables */
 861         c->icache.waysize = icache_size / c->icache.ways;
 862         c->dcache.waysize = dcache_size / c->dcache.ways;
 863
 864         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
 865         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
 866
 867         /*
 868          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
 869          * 2-way virtually indexed so normally would suffer from aliases.  So
 870          * normally they'd suffer from aliases but magic in the hardware deals
 871          * with that for us so we don't need to take care ourselves.
 872          */
 873         if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000)
 874                 if (c->dcache.waysize > PAGE_SIZE)
 875                         c->dcache.flags |= MIPS_CACHE_ALIASES;
 876
 877         switch (c->cputype) {
 878         case CPU_20KC:
 879                 /*
 880                  * Some older 20Kc chips doesn't have the 'VI' bit in
 881                  * the config register.
 882                  */
 883                 c->icache.flags |= MIPS_CACHE_VTAG;
 884                 break;
 885
 886         case CPU_AU1500:
 887                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
 888                 break;
 889         }
 890
 891         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
 892                icache_size >> 10,
 893                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
 894                way_string[c->icache.ways], c->icache.linesz);
 895
 896         printk("Primary data cache %ldkB %s, linesize %d bytes.\n",
 897                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
 898 }
 899
 900 /*
 901  * If you even _breathe_ on this function, look at the gcc output and make sure
 902  * it does not pop things on and off the stack for the cache sizing loop that
 903  * executes in KSEG1 space or else you will crash and burn badly.  You have
 904  * been warned.
 905  */
 906 static int __init probe_scache(void)
 907 {
 908         extern unsigned long stext;
 909         unsigned long flags, addr, begin, end, pow2;
 910         unsigned int config = read_c0_config();
 911         struct cpuinfo_mips *c = &current_cpu_data;
 912         int tmp;
 913
 914         if (config & CONF_SC)
 915                 return 0;
 916
 917         begin = (unsigned long) &stext;
 918         begin &= ~((4 * 1024 * 1024) - 1);
 919         end = begin + (4 * 1024 * 1024);
 920
 921         /*
 922          * This is such a bitch, you'd think they would make it easy to do
 923          * this.  Away you daemons of stupidity!
 924          */
 925         local_irq_save(flags);
 926
 927         /* Fill each size-multiple cache line with a valid tag. */
 928         pow2 = (64 * 1024);
 929         for (addr = begin; addr < end; addr = (begin + pow2)) {
 930                 unsigned long *p = (unsigned long *) addr;
 931                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
 932                 pow2 <<= 1;
 933         }
 934
 935         /* Load first line with zero (therefore invalid) tag. */
 936         write_c0_taglo(0);
 937         write_c0_taghi(0);
 938         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
 939         cache_op(Index_Store_Tag_I, begin);
 940         cache_op(Index_Store_Tag_D, begin);
 941         cache_op(Index_Store_Tag_SD, begin);
 942
 943         /* Now search for the wrap around point. */
 944         pow2 = (128 * 1024);
 945         tmp = 0;
 946         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
 947                 cache_op(Index_Load_Tag_SD, addr);
 948                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
 949                 if (!read_c0_taglo())
 950                         break;
 951                 pow2 <<= 1;
 952         }
 953         local_irq_restore(flags);
 954         addr -= begin;
 955
 956         scache_size = addr;
 957         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
 958         c->scache.ways = 1;
 959         c->dcache.waybit = 0;           /* does not matter */
 960
 961         return 1;
 962 }
 963
 964 typedef int (*probe_func_t)(unsigned long);
 965 extern int r5k_sc_init(void);
 966 extern int rm7k_sc_init(void);
 967
 968 static void __init setup_scache(void)
 969 {
 970         struct cpuinfo_mips *c = &current_cpu_data;
 971         unsigned int config = read_c0_config();
 972         probe_func_t probe_scache_kseg1;
 973         int sc_present = 0;
 974
 975         /*
 976          * Do the probing thing on R4000SC and R4400SC processors.  Other
 977          * processors don't have a S-cache that would be relevant to the
 978          * Linux memory managment.
 979          */
 980         switch (c->cputype) {
 981         case CPU_R4000SC:
 982         case CPU_R4000MC:
 983         case CPU_R4400SC:
 984         case CPU_R4400MC:
 985                 probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
 986                 sc_present = probe_scache_kseg1(config);
 987                 if (sc_present)
 988                         c->options |= MIPS_CPU_CACHE_CDEX_S;
 989                 break;
 990
 991         case CPU_R10000:
 992         case CPU_R12000:
 993                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
 994                 c->scache.linesz = 64 << ((config >> 13) & 1);
 995                 c->scache.ways = 2;
 996                 c->scache.waybit= 0;
 997                 sc_present = 1;
 998                 break;
 999
1000         case CPU_R5000:
1001         case CPU_NEVADA:
1002 #ifdef CONFIG_R5000_CPU_SCACHE
1003                 r5k_sc_init();
1004 #endif
1005                 return;
1006
1007         case CPU_RM7000:
1008         case CPU_RM9000:
1009 #ifdef CONFIG_RM7000_CPU_SCACHE
1010                 rm7k_sc_init();
1011 #endif
1012                 return;
1013
1014         default:
1015                 sc_present = 0;
1016         }
1017
1018         if (!sc_present)
1019                 return;
1020
1021         if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1022              c->isa_level == MIPS_CPU_ISA_M64) &&
1023             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1024                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1025
1026         /* compute a couple of other cache variables */
1027         c->scache.waysize = scache_size / c->scache.ways;
1028
1029         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1030
1031         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1032                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1033
1034         c->options |= MIPS_CPU_SUBSET_CACHES;
1035 }
1036
1037 static inline void coherency_setup(void)
1038 {
1039         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1040
1041         /*
1042          * c0_status.cu=0 specifies that updates by the sc instruction use
1043          * the coherency mode specified by the TLB; 1 means cachable
1044          * coherent update on write will be used.  Not all processors have
1045          * this bit and; some wire it to zero, others like Toshiba had the
1046          * silly idea of putting something else there ...
1047          */
1048         switch (current_cpu_data.cputype) {
1049         case CPU_R4000PC:
1050         case CPU_R4000SC:
1051         case CPU_R4000MC:
1052         case CPU_R4400PC:
1053         case CPU_R4400SC:
1054         case CPU_R4400MC:
1055                 clear_c0_config(CONF_CU);
1056                 break;
1057         }
1058 }
1059
1060 void __init ld_mmu_r4xx0(void)
1061 {
1062         extern void build_clear_page(void);
1063         extern void build_copy_page(void);
1064         extern char except_vec2_generic;
1065         struct cpuinfo_mips *c = &current_cpu_data;
1066
1067         /* Default cache error handler for R4000 and R5000 family */
1068         memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_generic, 0x80);
1069         memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1070
1071         probe_pcache();
1072         setup_scache();
1073
1074         if (c->dcache.sets * c->dcache.ways > PAGE_SIZE)
1075                 c->dcache.flags |= MIPS_CACHE_ALIASES;
1076
1077         r4k_blast_dcache_page_setup();
1078         r4k_blast_dcache_page_indexed_setup();
1079         r4k_blast_dcache_setup();
1080         r4k_blast_icache_page_setup();
1081         r4k_blast_icache_page_indexed_setup();
1082         r4k_blast_icache_setup();
1083         r4k_blast_scache_page_setup();
1084         r4k_blast_scache_setup();
1085
1086         /*
1087          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1088          * This code supports virtually indexed processors and will be
1089          * unnecessarily inefficient on physically indexed processors.
1090          */
1091         shm_align_mask = max_t( unsigned long,
1092                                 c->dcache.sets * c->dcache.linesz - 1,
1093                                 PAGE_SIZE - 1);
1094
1095         flush_cache_all         = r4k_flush_cache_all;
1096         __flush_cache_all       = r4k___flush_cache_all;
1097         flush_cache_mm          = r4k_flush_cache_mm;
1098         flush_cache_page        = r4k_flush_cache_page;
1099         flush_icache_page       = r4k_flush_icache_page;
1100         flush_cache_range       = r4k_flush_cache_range;
1101
1102         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1103         flush_icache_all        = r4k_flush_icache_all;
1104         flush_data_cache_page   = r4k_flush_data_cache_page;
1105         flush_icache_range      = r4k_flush_icache_range;
1106
1107 #ifdef CONFIG_DMA_NONCOHERENT
1108         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1109         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1110         _dma_cache_inv          = r4k_dma_cache_inv;
1111 #endif
1112
1113         __flush_cache_all();
1114         coherency_setup();
1115
1116         build_clear_page();
1117         build_copy_page();
1118 }