2 * TLB exception handling code for r4k.
4 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse
6 * Multi-cpu abstraction and reworking:
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
9 * Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
12 #include <linux/init.h>
13 #include <linux/config.h>
16 #include <asm/offset.h>
17 #include <asm/cachectl.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
21 #include <asm/pgtable-bits.h>
22 #include <asm/regdef.h>
23 #include <asm/stackframe.h>
26 #define TLB_OPTIMIZE /* If you are paranoid, disable this. */
28 #ifdef CONFIG_64BIT_PHYS_ADDR
34 #define PTEP_INDX_MSK 0xff0
35 #define PTE_INDX_MSK 0xff8
36 #define PTE_INDX_SHIFT 9
43 #define PTEP_INDX_MSK 0xff8
44 #define PTE_INDX_MSK 0xffc
45 #define PTE_INDX_SHIFT 10
49 * ABUSE of CPP macros 101.
51 * After this macro runs, the pte faulted on is
52 * in register PTE, a ptr into the table in which
53 * the pte belongs is in PTR.
57 #define GET_PGD(scratch, ptr) \
58 mfc0 ptr, CP0_CONTEXT; \
59 la scratch, pgd_current;\
62 addu ptr, scratch, ptr; \
65 #define GET_PGD(scratch, ptr) \
69 #define LOAD_PTE(pte, ptr) \
71 mfc0 pte, CP0_BADVADDR; \
72 srl pte, pte, _PGDIR_SHIFT; \
75 mfc0 pte, CP0_BADVADDR; \
77 srl pte, pte, PTE_INDX_SHIFT; \
78 and pte, pte, PTE_INDX_MSK; \
82 /* This places the even/odd pte pair in the page
83 * table at PTR into ENTRYLO0 and ENTRYLO1 using
84 * TMP as a scratch register.
86 #define PTE_RELOAD(ptr, tmp) \
87 ori ptr, ptr, PTE_SIZE; \
88 xori ptr, ptr, PTE_SIZE; \
89 PTE_L tmp, PTE_SIZE(ptr); \
91 PTE_SRL tmp, tmp, 6; \
92 P_MTC0 tmp, CP0_ENTRYLO1; \
93 PTE_SRL ptr, ptr, 6; \
94 P_MTC0 ptr, CP0_ENTRYLO0;
96 #define DO_FAULT(write) \
99 mfc0 a2, CP0_BADVADDR; \
105 j ret_from_exception; \
109 /* Check is PTE is present, if not then jump to LABEL.
110 * PTR points to the page table where this PTE is located,
111 * when the macro is done executing PTE will be restored
112 * with it's original value.
114 #define PTE_PRESENT(pte, ptr, label) \
115 andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
116 xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \
120 /* Make PTE valid, store result in PTR. */
121 #define PTE_MAKEVALID(pte, ptr) \
122 ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \
125 /* Check if PTE can be written to, if not branch to LABEL.
126 * Regardless restore PTE with value from PTR when done.
128 #define PTE_WRITABLE(pte, ptr, label) \
129 andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
130 xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \
134 /* Make PTE writable, update software status bits as well,
137 #define PTE_MAKEWRITE(pte, ptr) \
138 ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \
139 _PAGE_VALID | _PAGE_DIRTY); \
146 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
147 * 2. A timing hazard exists for the TLBP instruction.
149 * stalling_instruction
152 * The JTLB is being read for the TLBP throughout the stall generated by the
153 * previous instruction. This is not really correct as the stalling instruction
154 * can modify the address used to access the JTLB. The failure symptom is that
155 * the TLBP instruction will use an address created for the stalling instruction
156 * and not the address held in C0_ENHI and thus report the wrong results.
158 * The software work-around is to not allow the instruction preceding the TLBP
159 * to stall - make it an NOP or some other instruction guaranteed not to stall.
161 * Errata 2 will not be fixed. This errata is also on the R5000.
163 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
165 #define R5K_HAZARD nop
168 * Note for many R4k variants tlb probes cannot be executed out
169 * of the instruction cache else you get bogus results.
172 NESTED(handle_tlbl, PT_SIZE, sp)
175 mfc0 k0, CP0_BADVADDR
178 srl k0, k0, PAGE_SHIFT+1
189 /* Test present bit in entry. */
193 PTE_PRESENT(k0, k1, nopage_tlbl)
194 PTE_MAKEVALID(k0, k1)
210 NESTED(handle_tlbs, PT_SIZE, sp)
217 tlbp # find faulting entry
218 PTE_WRITABLE(k0, k1, nopage_tlbs)
219 PTE_MAKEWRITE(k0, k1)
235 NESTED(handle_mod, PT_SIZE, sp)
241 tlbp # find faulting entry
242 andi k0, k0, _PAGE_WRITE
246 /* Present and writable bits set, set accessed and dirty bits. */
247 PTE_MAKEWRITE(k0, k1)
249 /* Now reload the entry into the tlb. */