4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
7 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
12 * Author: Matthew Dharm, Momentum Computer
15 * Author: RidgeRun, Inc.
16 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 * Copyright 2001 MontaVista Software Inc.
19 * Author: jsun@mvista.com or jsun@junsun.net
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
26 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
29 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
32 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * You should have received a copy of the GNU General Public License along
38 * with this program; if not, write to the Free Software Foundation, Inc.,
39 * 675 Mass Ave, Cambridge, MA 02139, USA.
42 #include <linux/config.h>
43 #include <linux/init.h>
44 #include <linux/kernel.h>
45 #include <linux/types.h>
47 #include <linux/swap.h>
48 #include <linux/ioport.h>
49 #include <linux/sched.h>
50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/timex.h>
53 #include <linux/vmalloc.h>
55 #include <asm/bootinfo.h>
60 #include <asm/processor.h>
61 #include <asm/ptrace.h>
62 #include <asm/reboot.h>
63 #include <linux/bootmem.h>
64 #include <linux/blkdev.h>
66 #include "ocelot_pld.h"
68 #ifdef CONFIG_GALILLEO_GT64240_ETH
69 extern unsigned char prom_mac_addr_base[6];
72 unsigned long gt64240_base;
74 /* These functions are used for rebooting or halting the machine*/
75 extern void momenco_ocelot_restart(char *command);
76 extern void momenco_ocelot_halt(void);
77 extern void momenco_ocelot_power_off(void);
79 extern void gt64240_time_init(void);
80 extern void momenco_ocelot_irq_setup(void);
82 static char reset_reason;
84 static unsigned long ENTRYLO(unsigned long paddr)
86 return ((paddr & PAGE_MASK) |
87 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
88 _CACHE_UNCACHED)) >> 6;
91 static void __init setup_l3cache(unsigned long size);
93 /* setup code for a handoff from a version 2 PMON 2000 PROM */
94 void PMON_v2_setup(void)
96 /* A wired TLB entry for the GT64240 and the serial port. The
97 GT64240 is going to be hit on every IRQ anyway - there's
98 absolutely no point in letting it be a random TLB entry, as
99 it'll just cause needless churning of the TLB. And we use
100 the other half for the serial port, which is just a PITA
103 Device Physical Virtual
104 GT64240 Internal Regs 0xf4000000 0xe0000000
105 UARTs (CS2) 0xfd000000 0xe0001000
107 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
108 add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), 0xfd000000, PM_4K);
110 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
111 in the CS[012] region. We can't use ioremap() yet. The NVRAM
112 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
114 Ocelot PLD (CS0) 0xfc000000 0xe0020000
115 NVRAM (CS1) 0xfc800000 0xe0030000
117 add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), 0xfc000000, PM_64K);
118 add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), 0xfc800000, PM_64K);
120 gt64240_base = 0xf4000000;
123 static void __init momenco_ocelot_g_setup(void)
125 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
126 unsigned int tmpword;
128 board_time_init = gt64240_time_init;
130 _machine_restart = momenco_ocelot_restart;
131 _machine_halt = momenco_ocelot_halt;
132 _machine_power_off = momenco_ocelot_power_off;
135 * initrd_start = (ulong)ocelot_initrd_start;
136 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
137 * initrd_below_start_ok = 1;
140 /* do handoff reconfiguration */
143 #ifdef CONFIG_GALILLEO_GT64240_ETH
144 /* get the mac addr */
145 memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
148 /* Turn off the Bit-Error LED */
149 OCELOT_PLD_WRITE(0x80, INTCLR);
151 tmpword = OCELOT_PLD_READ(BOARDREV);
153 printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
155 printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
157 tmpword = OCELOT_PLD_READ(PLD1_ID);
158 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
159 tmpword = OCELOT_PLD_READ(PLD2_ID);
160 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
161 tmpword = OCELOT_PLD_READ(RESET_STATUS);
162 printk("Reset reason: 0x%x\n", tmpword);
163 reset_reason = tmpword;
164 OCELOT_PLD_WRITE(0xff, RESET_STATUS);
166 tmpword = OCELOT_PLD_READ(BOARD_STATUS);
167 printk("Board Status register: 0x%02x\n", tmpword);
168 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
169 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
170 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
171 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
172 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
175 l3func((1<<(((tmpword&12) >> 2)+20)));
179 /* 512MiB -- two banks of 256MiB */
180 add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM);
182 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
186 /* 256MiB -- two banks of 128MiB */
187 add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
188 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
191 /* 128MiB -- 64MiB per bank */
192 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
193 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
197 add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
201 /* FIXME: Fix up the DiskOnChip mapping */
202 GT_WRITE(0x468, 0xfef73);
205 early_initcall(momenco_ocelot_g_setup);
207 extern int rm7k_tcache_enabled;
209 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
211 #define Page_Invalidate_T 0x16
212 static void __init setup_l3cache(unsigned long size)
217 printk("Enabling L3 cache...");
219 /* Enable the L3 cache in the GT64120A's CPU Configuration register */
221 GT_WRITE(0, tmp | (1<<14));
223 /* Enable the L3 cache in the CPU */
224 set_c0_config(1<<12 /* CONF_TE */);
226 /* Clear the cache */
230 for (i=0; i < size; i+= 4096) {
231 __asm__ __volatile__ (
238 : "r" (KSEG0ADDR(i)),
239 "i" (Page_Invalidate_T));
242 /* Let the RM7000 MM code know that the tertiary cache is enabled */
243 rm7k_tcache_enabled = 1;
249 /* This needs to be one of the first initcalls, because no I/O port access
250 can work before this */
252 static int io_base_ioremap(void)
254 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
255 void *io_remap_range = ioremap(0xc0000000, 0x30000000);
257 if (!io_remap_range) {
258 panic("Could not ioremap I/O port range");
260 printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
261 set_io_port_base(io_remap_range - 0xc0000000);
266 module_init(io_base_ioremap);