arch/mips/vr41xx/common/icu.c

   1 /*
   2  *  icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
   3  *
   4  *  Copyright (C) 2001-2002  MontaVista Software Inc.
   5  *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
   6  *  Copyright (C) 2003-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 /*
  23  * Changes:
  24  *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
  25  *  - New creation, NEC VR4122 and VR4131 are supported.
  26  *  - Added support for NEC VR4111 and VR4121.
  27  *
  28  *  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  29  *  - Coped with INTASSIGN of NEC VR4133.
  30  */
  31 #include <linux/config.h>
  32 #include <linux/errno.h>
  33 #include <linux/init.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/irq.h>
  36 #include <linux/module.h>
  37 #include <linux/smp.h>
  38 #include <linux/types.h>
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/irq_cpu.h>
  44 #include <asm/vr41xx/vr41xx.h>
  45
  46 extern asmlinkage void vr41xx_handle_interrupt(void);
  47
  48 extern void init_vr41xx_giuint_irq(void);
  49 extern void giuint_irq_dispatch(struct pt_regs *regs);
  50
  51 static uint32_t icu1_base;
  52 static uint32_t icu2_base;
  53
  54 static unsigned char sysint1_assign[16] = {
  55         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  56 static unsigned char sysint2_assign[16] = {
  57         2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
  58
  59 #define SYSINT1REG_TYPE1        KSEG1ADDR(0x0b000080)
  60 #define SYSINT2REG_TYPE1        KSEG1ADDR(0x0b000200)
  61
  62 #define SYSINT1REG_TYPE2        KSEG1ADDR(0x0f000080)
  63 #define SYSINT2REG_TYPE2        KSEG1ADDR(0x0f0000a0)
  64
  65 #define SYSINT1REG      0x00
  66 #define PIUINTREG       0x02
  67 #define INTASSIGN0      0x04
  68 #define INTASSIGN1      0x06
  69 #define GIUINTLREG      0x08
  70 #define DSIUINTREG      0x0a
  71 #define MSYSINT1REG     0x0c
  72 #define MPIUINTREG      0x0e
  73 #define MAIUINTREG      0x10
  74 #define MKIUINTREG      0x12
  75 #define MGIUINTLREG     0x14
  76 #define MDSIUINTREG     0x16
  77 #define NMIREG          0x18
  78 #define SOFTREG         0x1a
  79 #define INTASSIGN2      0x1c
  80 #define INTASSIGN3      0x1e
  81
  82 #define SYSINT2REG      0x00
  83 #define GIUINTHREG      0x02
  84 #define FIRINTREG       0x04
  85 #define MSYSINT2REG     0x06
  86 #define MGIUINTHREG     0x08
  87 #define MFIRINTREG      0x0a
  88 #define PCIINTREG       0x0c
  89  #define PCIINT0        0x0001
  90 #define SCUINTREG       0x0e
  91  #define SCUINT0        0x0001
  92 #define CSIINTREG       0x10
  93 #define MPCIINTREG      0x12
  94 #define MSCUINTREG      0x14
  95 #define MCSIINTREG      0x16
  96 #define BCUINTREG       0x18
  97  #define BCUINTR        0x0001
  98 #define MBCUINTREG      0x1a
  99
 100 #define SYSINT1_IRQ_TO_PIN(x)   ((x) - SYSINT1_IRQ_BASE)        /* Pin 0-15 */
 101 #define SYSINT2_IRQ_TO_PIN(x)   ((x) - SYSINT2_IRQ_BASE)        /* Pin 0-15 */
 102
 103 #define read_icu1(offset)       readw(icu1_base + (offset))
 104 #define write_icu1(val, offset) writew((val), icu1_base + (offset))
 105
 106 #define read_icu2(offset)       readw(icu2_base + (offset))
 107 #define write_icu2(val, offset) writew((val), icu2_base + (offset))
 108
 109 #define INTASSIGN_MAX   4
 110 #define INTASSIGN_MASK  0x0007
 111
 112 static inline uint16_t set_icu1(uint8_t offset, uint16_t set)
 113 {
 114         uint16_t res;
 115
 116         res = read_icu1(offset);
 117         res |= set;
 118         write_icu1(res, offset);
 119
 120         return res;
 121 }
 122
 123 static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear)
 124 {
 125         uint16_t res;
 126
 127         res = read_icu1(offset);
 128         res &= ~clear;
 129         write_icu1(res, offset);
 130
 131         return res;
 132 }
 133
 134 static inline uint16_t set_icu2(uint8_t offset, uint16_t set)
 135 {
 136         uint16_t res;
 137
 138         res = read_icu2(offset);
 139         res |= set;
 140         write_icu2(res, offset);
 141
 142         return res;
 143 }
 144
 145 static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear)
 146 {
 147         uint16_t res;
 148
 149         res = read_icu2(offset);
 150         res &= ~clear;
 151         write_icu2(res, offset);
 152
 153         return res;
 154 }
 155
 156 /*=======================================================================*/
 157
 158 void vr41xx_enable_piuint(uint16_t mask)
 159 {
 160         irq_desc_t *desc = irq_desc + PIU_IRQ;
 161         unsigned long flags;
 162         uint16_t val;
 163
 164         spin_lock_irqsave(&desc->lock, flags);
 165         val = read_icu1(MPIUINTREG);
 166         val |= mask;
 167         write_icu1(val, MPIUINTREG);
 168         spin_unlock_irqrestore(&desc->lock, flags);
 169 }
 170
 171 void vr41xx_disable_piuint(uint16_t mask)
 172 {
 173         irq_desc_t *desc = irq_desc + PIU_IRQ;
 174         unsigned long flags;
 175         uint16_t val;
 176
 177         spin_lock_irqsave(&desc->lock, flags);
 178         val = read_icu1(MPIUINTREG);
 179         val &= ~mask;
 180         write_icu1(val, MPIUINTREG);
 181         spin_unlock_irqrestore(&desc->lock, flags);
 182 }
 183
 184 void vr41xx_enable_aiuint(uint16_t mask)
 185 {
 186         irq_desc_t *desc = irq_desc + AIU_IRQ;
 187         unsigned long flags;
 188         uint16_t val;
 189
 190         spin_lock_irqsave(&desc->lock, flags);
 191         val = read_icu1(MAIUINTREG);
 192         val |= mask;
 193         write_icu1(val, MAIUINTREG);
 194         spin_unlock_irqrestore(&desc->lock, flags);
 195 }
 196
 197 void vr41xx_disable_aiuint(uint16_t mask)
 198 {
 199         irq_desc_t *desc = irq_desc + AIU_IRQ;
 200         unsigned long flags;
 201         uint16_t val;
 202
 203         spin_lock_irqsave(&desc->lock, flags);
 204         val = read_icu1(MAIUINTREG);
 205         val &= ~mask;
 206         write_icu1(val, MAIUINTREG);
 207         spin_unlock_irqrestore(&desc->lock, flags);
 208 }
 209
 210 void vr41xx_enable_kiuint(uint16_t mask)
 211 {
 212         irq_desc_t *desc = irq_desc + KIU_IRQ;
 213         unsigned long flags;
 214         uint16_t val;
 215
 216         spin_lock_irqsave(&desc->lock, flags);
 217         val = read_icu1(MKIUINTREG);
 218         val |= mask;
 219         write_icu1(val, MKIUINTREG);
 220         spin_unlock_irqrestore(&desc->lock, flags);
 221 }
 222
 223 void vr41xx_disable_kiuint(uint16_t mask)
 224 {
 225         irq_desc_t *desc = irq_desc + KIU_IRQ;
 226         unsigned long flags;
 227         uint16_t val;
 228
 229         spin_lock_irqsave(&desc->lock, flags);
 230         val = read_icu1(MKIUINTREG);
 231         val &= ~mask;
 232         write_icu1(val, MKIUINTREG);
 233         spin_unlock_irqrestore(&desc->lock, flags);
 234 }
 235
 236 void vr41xx_enable_dsiuint(uint16_t mask)
 237 {
 238         irq_desc_t *desc = irq_desc + DSIU_IRQ;
 239         unsigned long flags;
 240         uint16_t val;
 241
 242         spin_lock_irqsave(&desc->lock, flags);
 243         val = read_icu1(MDSIUINTREG);
 244         val |= mask;
 245         write_icu1(val, MDSIUINTREG);
 246         spin_unlock_irqrestore(&desc->lock, flags);
 247 }
 248
 249 void vr41xx_disable_dsiuint(uint16_t mask)
 250 {
 251         irq_desc_t *desc = irq_desc + DSIU_IRQ;
 252         unsigned long flags;
 253         uint16_t val;
 254
 255         spin_lock_irqsave(&desc->lock, flags);
 256         val = read_icu1(MDSIUINTREG);
 257         val &= ~mask;
 258         write_icu1(val, MDSIUINTREG);
 259         spin_unlock_irqrestore(&desc->lock, flags);
 260 }
 261
 262 void vr41xx_enable_firint(uint16_t mask)
 263 {
 264         irq_desc_t *desc = irq_desc + FIR_IRQ;
 265         unsigned long flags;
 266         uint16_t val;
 267
 268         spin_lock_irqsave(&desc->lock, flags);
 269         val = read_icu2(MFIRINTREG);
 270         val |= mask;
 271         write_icu2(val, MFIRINTREG);
 272         spin_unlock_irqrestore(&desc->lock, flags);
 273 }
 274
 275 void vr41xx_disable_firint(uint16_t mask)
 276 {
 277         irq_desc_t *desc = irq_desc + FIR_IRQ;
 278         unsigned long flags;
 279         uint16_t val;
 280
 281         spin_lock_irqsave(&desc->lock, flags);
 282         val = read_icu2(MFIRINTREG);
 283         val &= ~mask;
 284         write_icu2(val, MFIRINTREG);
 285         spin_unlock_irqrestore(&desc->lock, flags);
 286 }
 287
 288 void vr41xx_enable_pciint(void)
 289 {
 290         irq_desc_t *desc = irq_desc + PCI_IRQ;
 291         unsigned long flags;
 292
 293         spin_lock_irqsave(&desc->lock, flags);
 294         write_icu2(PCIINT0, MPCIINTREG);
 295         spin_unlock_irqrestore(&desc->lock, flags);
 296 }
 297
 298 void vr41xx_disable_pciint(void)
 299 {
 300         irq_desc_t *desc = irq_desc + PCI_IRQ;
 301         unsigned long flags;
 302
 303         spin_lock_irqsave(&desc->lock, flags);
 304         write_icu2(0, MPCIINTREG);
 305         spin_unlock_irqrestore(&desc->lock, flags);
 306 }
 307
 308 void vr41xx_enable_scuint(void)
 309 {
 310         irq_desc_t *desc = irq_desc + SCU_IRQ;
 311         unsigned long flags;
 312
 313         spin_lock_irqsave(&desc->lock, flags);
 314         write_icu2(SCUINT0, MSCUINTREG);
 315         spin_unlock_irqrestore(&desc->lock, flags);
 316 }
 317
 318 void vr41xx_disable_scuint(void)
 319 {
 320         irq_desc_t *desc = irq_desc + SCU_IRQ;
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&desc->lock, flags);
 324         write_icu2(0, MSCUINTREG);
 325         spin_unlock_irqrestore(&desc->lock, flags);
 326 }
 327
 328 void vr41xx_enable_csiint(uint16_t mask)
 329 {
 330         irq_desc_t *desc = irq_desc + CSI_IRQ;
 331         unsigned long flags;
 332         uint16_t val;
 333
 334         spin_lock_irqsave(&desc->lock, flags);
 335         val = read_icu2(MCSIINTREG);
 336         val |= mask;
 337         write_icu2(val, MCSIINTREG);
 338         spin_unlock_irqrestore(&desc->lock, flags);
 339 }
 340
 341 void vr41xx_disable_csiint(uint16_t mask)
 342 {
 343         irq_desc_t *desc = irq_desc + CSI_IRQ;
 344         unsigned long flags;
 345         uint16_t val;
 346
 347         spin_lock_irqsave(&desc->lock, flags);
 348         val = read_icu2(MCSIINTREG);
 349         val &= ~mask;
 350         write_icu2(val, MCSIINTREG);
 351         spin_unlock_irqrestore(&desc->lock, flags);
 352 }
 353
 354 void vr41xx_enable_bcuint(void)
 355 {
 356         irq_desc_t *desc = irq_desc + BCU_IRQ;
 357         unsigned long flags;
 358
 359         spin_lock_irqsave(&desc->lock, flags);
 360         write_icu2(BCUINTR, MBCUINTREG);
 361         spin_unlock_irqrestore(&desc->lock, flags);
 362 }
 363
 364 void vr41xx_disable_bcuint(void)
 365 {
 366         irq_desc_t *desc = irq_desc + BCU_IRQ;
 367         unsigned long flags;
 368
 369         spin_lock_irqsave(&desc->lock, flags);
 370         write_icu2(0, MBCUINTREG);
 371         spin_unlock_irqrestore(&desc->lock, flags);
 372 }
 373
 374 /*=======================================================================*/
 375
 376 static unsigned int startup_sysint1_irq(unsigned int irq)
 377 {
 378         set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
 379
 380         return 0; /* never anything pending */
 381 }
 382
 383 static void shutdown_sysint1_irq(unsigned int irq)
 384 {
 385         clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
 386 }
 387
 388 static void enable_sysint1_irq(unsigned int irq)
 389 {
 390         set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
 391 }
 392
 393 #define disable_sysint1_irq     shutdown_sysint1_irq
 394 #define ack_sysint1_irq         shutdown_sysint1_irq
 395
 396 static void end_sysint1_irq(unsigned int irq)
 397 {
 398         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 399                 set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq));
 400 }
 401
 402 static struct hw_interrupt_type sysint1_irq_type = {
 403         .typename       = "SYSINT1",
 404         .startup        = startup_sysint1_irq,
 405         .shutdown       = shutdown_sysint1_irq,
 406         .enable         = enable_sysint1_irq,
 407         .disable        = disable_sysint1_irq,
 408         .ack            = ack_sysint1_irq,
 409         .end            = end_sysint1_irq,
 410 };
 411
 412 /*=======================================================================*/
 413
 414 static unsigned int startup_sysint2_irq(unsigned int irq)
 415 {
 416         set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
 417
 418         return 0; /* never anything pending */
 419 }
 420
 421 static void shutdown_sysint2_irq(unsigned int irq)
 422 {
 423         clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
 424 }
 425
 426 static void enable_sysint2_irq(unsigned int irq)
 427 {
 428         set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
 429 }
 430
 431 #define disable_sysint2_irq     shutdown_sysint2_irq
 432 #define ack_sysint2_irq         shutdown_sysint2_irq
 433
 434 static void end_sysint2_irq(unsigned int irq)
 435 {
 436         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 437                 set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq));
 438 }
 439
 440 static struct hw_interrupt_type sysint2_irq_type = {
 441         .typename       = "SYSINT2",
 442         .startup        = startup_sysint2_irq,
 443         .shutdown       = shutdown_sysint2_irq,
 444         .enable         = enable_sysint2_irq,
 445         .disable        = disable_sysint2_irq,
 446         .ack            = ack_sysint2_irq,
 447         .end            = end_sysint2_irq,
 448 };
 449
 450 /*=======================================================================*/
 451
 452 static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
 453 {
 454         irq_desc_t *desc = irq_desc + irq;
 455         uint16_t intassign0, intassign1;
 456         unsigned int pin;
 457
 458         pin = SYSINT1_IRQ_TO_PIN(irq);
 459
 460         spin_lock_irq(&desc->lock);
 461
 462         intassign0 = read_icu1(INTASSIGN0);
 463         intassign1 = read_icu1(INTASSIGN1);
 464
 465         switch (pin) {
 466         case 0:
 467                 intassign0 &= ~INTASSIGN_MASK;
 468                 intassign0 |= (uint16_t)assign;
 469                 break;
 470         case 1:
 471                 intassign0 &= ~(INTASSIGN_MASK << 3);
 472                 intassign0 |= (uint16_t)assign << 3;
 473                 break;
 474         case 2:
 475                 intassign0 &= ~(INTASSIGN_MASK << 6);
 476                 intassign0 |= (uint16_t)assign << 6;
 477                 break;
 478         case 3:
 479                 intassign0 &= ~(INTASSIGN_MASK << 9);
 480                 intassign0 |= (uint16_t)assign << 9;
 481                 break;
 482         case 8:
 483                 intassign0 &= ~(INTASSIGN_MASK << 12);
 484                 intassign0 |= (uint16_t)assign << 12;
 485                 break;
 486         case 9:
 487                 intassign1 &= ~INTASSIGN_MASK;
 488                 intassign1 |= (uint16_t)assign;
 489                 break;
 490         case 11:
 491                 intassign1 &= ~(INTASSIGN_MASK << 6);
 492                 intassign1 |= (uint16_t)assign << 6;
 493                 break;
 494         case 12:
 495                 intassign1 &= ~(INTASSIGN_MASK << 9);
 496                 intassign1 |= (uint16_t)assign << 9;
 497                 break;
 498         default:
 499                 return -EINVAL;
 500         }
 501
 502         sysint1_assign[pin] = assign;
 503         write_icu1(intassign0, INTASSIGN0);
 504         write_icu1(intassign1, INTASSIGN1);
 505
 506         spin_unlock_irq(&desc->lock);
 507
 508         return 0;
 509 }
 510
 511 static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
 512 {
 513         irq_desc_t *desc = irq_desc + irq;
 514         uint16_t intassign2, intassign3;
 515         unsigned int pin;
 516
 517         pin = SYSINT2_IRQ_TO_PIN(irq);
 518
 519         spin_lock_irq(&desc->lock);
 520
 521         intassign2 = read_icu1(INTASSIGN2);
 522         intassign3 = read_icu1(INTASSIGN3);
 523
 524         switch (pin) {
 525         case 0:
 526                 intassign2 &= ~INTASSIGN_MASK;
 527                 intassign2 |= (uint16_t)assign;
 528                 break;
 529         case 1:
 530                 intassign2 &= ~(INTASSIGN_MASK << 3);
 531                 intassign2 |= (uint16_t)assign << 3;
 532                 break;
 533         case 3:
 534                 intassign2 &= ~(INTASSIGN_MASK << 6);
 535                 intassign2 |= (uint16_t)assign << 6;
 536                 break;
 537         case 4:
 538                 intassign2 &= ~(INTASSIGN_MASK << 9);
 539                 intassign2 |= (uint16_t)assign << 9;
 540                 break;
 541         case 5:
 542                 intassign2 &= ~(INTASSIGN_MASK << 12);
 543                 intassign2 |= (uint16_t)assign << 12;
 544                 break;
 545         case 6:
 546                 intassign3 &= ~INTASSIGN_MASK;
 547                 intassign3 |= (uint16_t)assign;
 548                 break;
 549         case 7:
 550                 intassign3 &= ~(INTASSIGN_MASK << 3);
 551                 intassign3 |= (uint16_t)assign << 3;
 552                 break;
 553         case 8:
 554                 intassign3 &= ~(INTASSIGN_MASK << 6);
 555                 intassign3 |= (uint16_t)assign << 6;
 556                 break;
 557         case 9:
 558                 intassign3 &= ~(INTASSIGN_MASK << 9);
 559                 intassign3 |= (uint16_t)assign << 9;
 560                 break;
 561         case 10:
 562                 intassign3 &= ~(INTASSIGN_MASK << 12);
 563                 intassign3 |= (uint16_t)assign << 12;
 564                 break;
 565         default:
 566                 return -EINVAL;
 567         }
 568
 569         sysint2_assign[pin] = assign;
 570         write_icu1(intassign2, INTASSIGN2);
 571         write_icu1(intassign3, INTASSIGN3);
 572
 573         spin_unlock_irq(&desc->lock);
 574
 575         return 0;
 576 }
 577
 578 int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
 579 {
 580         int retval = -EINVAL;
 581
 582         if (current_cpu_data.cputype != CPU_VR4133)
 583                 return -EINVAL;
 584
 585         if (intassign > INTASSIGN_MAX)
 586                 return -EINVAL;
 587
 588         if (irq >= SYSINT1_IRQ_BASE && irq <= SYSINT1_IRQ_LAST)
 589                 retval = set_sysint1_assign(irq, intassign);
 590         else if (irq >= SYSINT2_IRQ_BASE && irq <= SYSINT2_IRQ_LAST)
 591                 retval = set_sysint2_assign(irq, intassign);
 592
 593         return retval;
 594 }
 595
 596 EXPORT_SYMBOL(vr41xx_set_intassign);
 597
 598 /*=======================================================================*/
 599
 600 asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs)
 601 {
 602         uint16_t pend1, pend2;
 603         uint16_t mask1, mask2;
 604         int i;
 605
 606         pend1 = read_icu1(SYSINT1REG);
 607         mask1 = read_icu1(MSYSINT1REG);
 608
 609         pend2 = read_icu2(SYSINT2REG);
 610         mask2 = read_icu2(MSYSINT2REG);
 611
 612         mask1 &= pend1;
 613         mask2 &= pend2;
 614
 615         if (mask1) {
 616                 for (i = 0; i < 16; i++) {
 617                         if (intnum == sysint1_assign[i] &&
 618                             (mask1 & ((uint16_t)1 << i))) {
 619                                 if (i == 8)
 620                                         giuint_irq_dispatch(regs);
 621                                 else
 622                                         do_IRQ(SYSINT1_IRQ(i), regs);
 623                                 return;
 624                         }
 625                 }
 626         }
 627
 628         if (mask2) {
 629                 for (i = 0; i < 16; i++) {
 630                         if (intnum == sysint2_assign[i] &&
 631                             (mask2 & ((uint16_t)1 << i))) {
 632                                 do_IRQ(SYSINT2_IRQ(i), regs);
 633                                 return;
 634                         }
 635                 }
 636         }
 637
 638         printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
 639
 640         atomic_inc(&irq_err_count);
 641 }
 642
 643 /*=======================================================================*/
 644
 645 static int __init vr41xx_icu_init(void)
 646 {
 647         switch (current_cpu_data.cputype) {
 648         case CPU_VR4111:
 649         case CPU_VR4121:
 650                 icu1_base = SYSINT1REG_TYPE1;
 651                 icu2_base = SYSINT2REG_TYPE1;
 652                 break;
 653         case CPU_VR4122:
 654         case CPU_VR4131:
 655         case CPU_VR4133:
 656                 icu1_base = SYSINT1REG_TYPE2;
 657                 icu2_base = SYSINT2REG_TYPE2;
 658                 break;
 659         default:
 660                 printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
 661                 return -EINVAL;
 662         }
 663
 664         write_icu1(0, MSYSINT1REG);
 665         write_icu1(0xffff, MGIUINTLREG);
 666
 667         write_icu2(0, MSYSINT2REG);
 668         write_icu2(0xffff, MGIUINTHREG);
 669
 670         return 0;
 671 }
 672
 673 early_initcall(vr41xx_icu_init);
 674
 675 /*=======================================================================*/
 676
 677 static struct irqaction icu_cascade = {no_action, 0, 0, "cascade", NULL, NULL};
 678
 679 static inline void init_vr41xx_icu_irq(void)
 680 {
 681         int i;
 682
 683         for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
 684                 irq_desc[i].handler = &sysint1_irq_type;
 685
 686         for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
 687                 irq_desc[i].handler = &sysint2_irq_type;
 688
 689         setup_irq(INT0_CASCADE_IRQ, &icu_cascade);
 690         setup_irq(INT1_CASCADE_IRQ, &icu_cascade);
 691         setup_irq(INT2_CASCADE_IRQ, &icu_cascade);
 692         setup_irq(INT3_CASCADE_IRQ, &icu_cascade);
 693         setup_irq(INT4_CASCADE_IRQ, &icu_cascade);
 694 }
 695
 696 void __init init_IRQ(void)
 697 {
 698         memset(irq_desc, 0, sizeof(irq_desc));
 699
 700         init_generic_irq();
 701         mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
 702         init_vr41xx_icu_irq();
 703         init_vr41xx_giuint_irq();
 704
 705         set_except_vector(0, vr41xx_handle_interrupt);
 706 }