arch/parisc/kernel/cache.c

   1 /* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1999 Helge Deller (07-13-1999)
   8  * Copyright (C) 1999 SuSE GmbH Nuernberg
   9  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
  10  *
  11  * Cache and TLB management
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/pagemap.h>
  21
  22 #include <asm/pdc.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/system.h>
  27 #include <asm/page.h>
  28 #include <asm/pgalloc.h>
  29 #include <asm/processor.h>
  30
  31 int split_tlb;
  32 int dcache_stride;
  33 int icache_stride;
  34 EXPORT_SYMBOL(dcache_stride);
  35
  36 struct pdc_cache_info cache_info;
  37 #ifndef CONFIG_PA20
  38 static struct pdc_btlb_info btlb_info;
  39 #endif
  40
  41 #ifdef CONFIG_SMP
  42 void
  43 flush_data_cache(void)
  44 {
  45         on_each_cpu((void (*)(void *))flush_data_cache_local, NULL, 1, 1);
  46 }
  47 #endif
  48
  49 void
  50 flush_cache_all_local(void)
  51 {
  52         flush_instruction_cache_local();
  53         flush_data_cache_local();
  54 }
  55 EXPORT_SYMBOL(flush_cache_all_local);
  56
  57 /* flushes EVERYTHING (tlb & cache) */
  58
  59 void
  60 flush_all_caches(void)
  61 {
  62         flush_cache_all();
  63         flush_tlb_all();
  64 }
  65 EXPORT_SYMBOL(flush_all_caches);
  66
  67 void
  68 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  69 {
  70         struct page *page = pte_page(pte);
  71
  72         if (VALID_PAGE(page) && page_mapping(page) &&
  73             test_bit(PG_dcache_dirty, &page->flags)) {
  74
  75                 flush_kernel_dcache_page(page_address(page));
  76                 clear_bit(PG_dcache_dirty, &page->flags);
  77         }
  78 }
  79
  80 void
  81 show_cache_info(struct seq_file *m)
  82 {
  83         seq_printf(m, "I-cache\t\t: %ld KB\n",
  84                 cache_info.ic_size/1024 );
  85         seq_printf(m, "D-cache\t\t: %ld KB (%s)%s\n",
  86                 cache_info.dc_size/1024,
  87                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
  88                 (cache_info.dc_conf.cc_sh ? " - shared I/D":"")
  89         );
  90
  91         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
  92                 cache_info.it_size,
  93                 cache_info.dt_size,
  94                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
  95         );
  96
  97 #ifndef CONFIG_PA20
  98         /* BTLB - Block TLB */
  99         if (btlb_info.max_size==0) {
 100                 seq_printf(m, "BTLB\t\t: not supported\n" );
 101         } else {
 102                 seq_printf(m,
 103                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 104                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 105                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 106                 btlb_info.max_size, (int)4096,
 107                 btlb_info.max_size>>8,
 108                 btlb_info.fixed_range_info.num_i,
 109                 btlb_info.fixed_range_info.num_d,
 110                 btlb_info.fixed_range_info.num_comb,
 111                 btlb_info.variable_range_info.num_i,
 112                 btlb_info.variable_range_info.num_d,
 113                 btlb_info.variable_range_info.num_comb
 114                 );
 115         }
 116 #endif
 117 }
 118
 119 void __init
 120 parisc_cache_init(void)
 121 {
 122         if (pdc_cache_info(&cache_info) < 0)
 123                 panic("parisc_cache_init: pdc_cache_info failed");
 124
 125 #if 0
 126         printk(KERN_DEBUG "ic_size %lx dc_size %lx it_size %lx pdc_cache_info %d*long pdc_cache_cf %d\n",
 127             cache_info.ic_size,
 128             cache_info.dc_size,
 129             cache_info.it_size,
 130             sizeof (struct pdc_cache_info) / sizeof (long),
 131             sizeof (struct pdc_cache_cf)
 132         );
 133
 134         printk(KERN_DEBUG "dc base %x dc stride %x dc count %x dc loop %d\n",
 135             cache_info.dc_base,
 136             cache_info.dc_stride,
 137             cache_info.dc_count,
 138             cache_info.dc_loop);
 139
 140         printk(KERN_DEBUG "dc conf: alias %d block %d line %d wt %d sh %d cst %d assoc %d\n",
 141             cache_info.dc_conf.cc_alias,
 142             cache_info.dc_conf.cc_block,
 143             cache_info.dc_conf.cc_line,
 144             cache_info.dc_conf.cc_wt,
 145             cache_info.dc_conf.cc_sh,
 146             cache_info.dc_conf.cc_cst,
 147             cache_info.dc_conf.cc_assoc);
 148
 149         printk(KERN_DEBUG "ic conf: alias %d block %d line %d wt %d sh %d cst %d assoc %d\n",
 150             cache_info.ic_conf.cc_alias,
 151             cache_info.ic_conf.cc_block,
 152             cache_info.ic_conf.cc_line,
 153             cache_info.ic_conf.cc_wt,
 154             cache_info.ic_conf.cc_sh,
 155             cache_info.ic_conf.cc_cst,
 156             cache_info.ic_conf.cc_assoc);
 157
 158         printk(KERN_DEBUG "dt conf: sh %d page %d cst %d aid %d pad1 %d \n",
 159             cache_info.dt_conf.tc_sh,
 160             cache_info.dt_conf.tc_page,
 161             cache_info.dt_conf.tc_cst,
 162             cache_info.dt_conf.tc_aid,
 163             cache_info.dt_conf.tc_pad1);
 164
 165         printk(KERN_DEBUG "it conf: sh %d page %d cst %d aid %d pad1 %d \n",
 166             cache_info.it_conf.tc_sh,
 167             cache_info.it_conf.tc_page,
 168             cache_info.it_conf.tc_cst,
 169             cache_info.it_conf.tc_aid,
 170             cache_info.it_conf.tc_pad1);
 171 #endif
 172
 173         split_tlb = 0;
 174         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 175                 if (cache_info.dt_conf.tc_sh == 2)
 176                         printk(KERN_WARNING "Unexpected TLB configuration. "
 177                         "Will flush I/D separately (could be optimized).\n");
 178
 179                 split_tlb = 1;
 180         }
 181
 182         dcache_stride = (1 << (cache_info.dc_conf.cc_block + 3)) *
 183                                                 cache_info.dc_conf.cc_line;
 184         icache_stride = (1 << (cache_info.ic_conf.cc_block + 3)) *
 185                                                 cache_info.ic_conf.cc_line;
 186 #ifndef CONFIG_PA20
 187         if (pdc_btlb_info(&btlb_info) < 0) {
 188                 memset(&btlb_info, 0, sizeof btlb_info);
 189         }
 190 #endif
 191
 192         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 193                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 194                 printk(KERN_WARNING "Only equivalent aliasing supported\n");
 195 #ifndef CONFIG_SMP
 196                 panic("SMP kernel required to avoid non-equivalent aliasing");
 197 #endif
 198         }
 199 }
 200
 201 void disable_sr_hashing(void)
 202 {
 203         int srhash_type;
 204
 205         switch (boot_cpu_data.cpu_type) {
 206         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 207                 BUG();
 208                 return;
 209
 210         case pcxs:
 211         case pcxt:
 212         case pcxt_:
 213                 srhash_type = SRHASH_PCXST;
 214                 break;
 215
 216         case pcxl:
 217                 srhash_type = SRHASH_PCXL;
 218                 break;
 219
 220         case pcxl2: /* pcxl2 doesn't support space register hashing */
 221                 return;
 222
 223         default: /* Currently all PA2.0 machines use the same ins. sequence */
 224                 srhash_type = SRHASH_PA20;
 225                 break;
 226         }
 227
 228         disable_sr_hashing_asm(srhash_type);
 229 }
 230
 231 void __flush_dcache_page(struct page *page)
 232 {
 233         struct address_space *mapping = page_mapping(page);
 234         struct vm_area_struct *mpnt = NULL;
 235         struct prio_tree_iter iter;
 236         unsigned long offset;
 237         unsigned long addr;
 238         pgoff_t pgoff;
 239
 240         flush_kernel_dcache_page(page_address(page));
 241
 242         if (!mapping)
 243                 return;
 244
 245         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 246
 247         /* We have carefully arranged in arch_get_unmapped_area() that
 248          * *any* mappings of a file are always congruently mapped (whether
 249          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 250          * to flush one address here for them all to become coherent */
 251
 252         flush_dcache_mmap_lock(mapping);
 253         while ((mpnt = vma_prio_tree_next(mpnt, &mapping->i_mmap,
 254                                         &iter, pgoff, pgoff)) != NULL) {
 255                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 256                 addr = mpnt->vm_start + offset;
 257
 258                 /* Flush instructions produce non access tlb misses.
 259                  * On PA, we nullify these instructions rather than
 260                  * taking a page fault if the pte doesn't exist.
 261                  * This is just for speed.  If the page translation
 262                  * isn't there, there's no point exciting the
 263                  * nadtlb handler into a nullification frenzy */
 264
 265                 if (!translation_exists(mpnt, addr))
 266                         continue;
 267
 268                 __flush_cache_page(mpnt, addr);
 269
 270                 break;
 271         }
 272         flush_dcache_mmap_unlock(mapping);
 273 }
 274 EXPORT_SYMBOL(__flush_dcache_page);
 275
 276 /* Defined in arch/parisc/kernel/pacache.S */
 277 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 278 EXPORT_SYMBOL(flush_kernel_dcache_page);
 279 EXPORT_SYMBOL(flush_data_cache_local);
 280 EXPORT_SYMBOL(flush_kernel_icache_range_asm);