arch/parisc/kernel/perf_asm.S

   1
   2 /*    low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
   3  *
   4  *    Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/config.h>
  22 #include <asm/assembly.h>
  23
  24 #ifdef __LP64__
  25         .level          2.0w
  26 #endif /* __LP64__ */
  27
  28 #define MTDIAG_1(gr)    .word 0x14201840 + gr*0x10000
  29 #define MTDIAG_2(gr)    .word 0x14401840 + gr*0x10000
  30 #define MFDIAG_1(gr)    .word 0x142008A0 + gr
  31 #define MFDIAG_2(gr)    .word 0x144008A0 + gr
  32 #define STDIAG(dr)      .word 0x14000AA0 + dr*0x200000
  33 #define SFDIAG(dr)      .word 0x14000BA0 + dr*0x200000
  34 #define DR2_SLOW_RET    53
  35
  36
  37 ;
  38 ; Enable the performance counters
  39 ;
  40 ; The coprocessor only needs to be enabled when
  41 ; starting/stopping the coprocessor with the pmenb/pmdis.
  42 ;
  43         .text
  44         .align 32
  45
  46         .export perf_intrigue_enable_perf_counters,code
  47 perf_intrigue_enable_perf_counters:
  48         .proc
  49         .callinfo  frame=0,NO_CALLS
  50         .entry
  51
  52         ldi     0x20,%r25                ; load up perfmon bit
  53         mfctl   ccr,%r26                 ; get coprocessor register
  54         or      %r25,%r26,%r26             ; set bit
  55         mtctl   %r26,ccr                 ; turn on performance coprocessor
  56         pmenb                           ; enable performance monitor
  57         ssm     0,0                     ; dummy op to ensure completion
  58         sync                            ; follow ERS
  59         andcm   %r26,%r25,%r26             ; clear bit now
  60         mtctl   %r26,ccr                 ; turn off performance coprocessor
  61         nop                             ; NOPs as specified in ERS
  62         nop
  63         nop
  64         nop
  65         nop
  66         nop
  67         nop
  68         bve    (%r2)
  69         nop
  70         .exit
  71         .procend
  72
  73         .export perf_intrigue_disable_perf_counters,code
  74 perf_intrigue_disable_perf_counters:
  75         .proc
  76         .callinfo  frame=0,NO_CALLS
  77         .entry
  78         ldi     0x20,%r25                ; load up perfmon bit
  79         mfctl   ccr,%r26                 ; get coprocessor register
  80         or      %r25,%r26,%r26             ; set bit
  81         mtctl   %r26,ccr                 ; turn on performance coprocessor
  82         pmdis                           ; disable performance monitor
  83         ssm     0,0                     ; dummy op to ensure completion
  84         andcm   %r26,%r25,%r26             ; clear bit now
  85         bve    (%r2)
  86         mtctl   %r26,ccr                 ; turn off performance coprocessor
  87         .exit
  88         .procend
  89
  90 ;************************************************************************
  91 ;*                                                                                                                                              *
  92 ;* Name: perf_rdr_shift_in_W                                                                                            *
  93 ;*                                                                                                                                              *
  94 ;* Description:                                                                                                                 *
  95 ;*      This routine shifts data in from the RDR in arg0 and returns            *
  96 ;*      the result in ret0.  If the RDR is <= 64 bits in length, it                     *
  97 ;*      is shifted shifted backup immediately.  This is to compensate           *
  98 ;*      for RDR10 which has bits that preclude PDC stack operations                     *
  99 ;*      when they are in the wrong state.                                                                       *
 100 ;*                                                                                                                                              *
 101 ;* Arguments:                                                                                                                   *
 102 ;*      arg0 : rdr to be read                                                                                           *
 103 ;*      arg1 : bit length of rdr                                                                                        *
 104 ;*                                                                                                                                              *
 105 ;* Returns:                                                                                                                             *
 106 ;*      ret0 = next 64 bits of rdr data from staging register                           *
 107 ;*                                                                                                                                              *
 108 ;* Register usage:                                                                                                              *
 109 ;*      arg0 : rdr to be read                                                                                           *
 110 ;*      arg1 : bit length of rdr                                                                                        *
 111 ;*      %r24  - original DR2 value                                                                                      *
 112 ;*      %r1   - scratch                                                                                                         *
 113 ;*  %r29  - scratch                                                                                                             *
 114 ;*                                                                                                                                              *
 115 ;* Returns:                                                                                                                             *
 116 ;*      ret0 = RDR data (right justified)                                                                       *
 117 ;*                                                                                                                                              *
 118 ;************************************************************************
 119
 120         .export perf_rdr_shift_in_W,code
 121 perf_rdr_shift_in_W:
 122         .proc
 123         .callinfo frame=0,NO_CALLS
 124         .entry
 125 ;
 126 ; read(shift in) the RDR.
 127 ;
 128
 129 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
 130 ; shifting is done, from or to, remote diagnose registers.
 131 ;
 132
 133         depdi,z         1,DR2_SLOW_RET,1,%r29
 134         MFDIAG_2        (24)
 135         or                  %r24,%r29,%r29
 136         MTDIAG_2        (29)                    ; set DR2_SLOW_RET
 137
 138         nop
 139         nop
 140         nop
 141         nop
 142
 143 ;
 144 ; Cacheline start (32-byte cacheline)
 145 ;
 146         nop
 147         nop
 148         nop
 149         extrd,u         arg1,63,6,%r1    ; setup shift amount based on bits to move
 150
 151         mtsar           %r1
 152         shladd          arg0,2,%r0,%r1  ; %r1 = 4 * RDR number
 153         blr             %r1,%r0             ; branch to 8-instruction sequence
 154         nop
 155
 156 ;
 157 ; Cacheline start (32-byte cacheline)
 158 ;
 159
 160         ;
 161         ; RDR 0 sequence
 162         ;
 163         SFDIAG          (0)
 164         ssm                 0,0
 165         MFDIAG_1        (28)
 166         shrpd           ret0,%r0,%sar,%r1
 167         MTDIAG_1        (1)                                     ; mtdiag %dr1, %r1
 168         STDIAG          (0)
 169         ssm                 0,0
 170         b,n         perf_rdr_shift_in_W_leave
 171
 172         ;
 173         ; RDR 1 sequence
 174         ;
 175         sync
 176         ssm                 0,0
 177         SFDIAG          (1)
 178         ssm                 0,0
 179         MFDIAG_1        (28)
 180         ssm                 0,0
 181         b,n         perf_rdr_shift_in_W_leave
 182         nop
 183
 184         ;
 185         ; RDR 2 read sequence
 186         ;
 187         SFDIAG          (2)
 188         ssm                 0,0
 189         MFDIAG_1        (28)
 190         shrpd           ret0,%r0,%sar,%r1
 191         MTDIAG_1        (1)
 192         STDIAG          (2)
 193         ssm                 0,0
 194         b,n         perf_rdr_shift_in_W_leave
 195
 196         ;
 197         ; RDR 3 read sequence
 198         ;
 199         b,n         perf_rdr_shift_in_W_leave
 200         nop
 201         nop
 202         nop
 203         nop
 204         nop
 205         nop
 206         nop
 207
 208         ;
 209         ; RDR 4 read sequence
 210         ;
 211         sync
 212         ssm                     0,0
 213         SFDIAG          (4)
 214         ssm                     0,0
 215         MFDIAG_1        (28)
 216         b,n         perf_rdr_shift_in_W_leave
 217         ssm                     0,0
 218         nop
 219
 220         ;
 221         ; RDR 5 read sequence
 222         ;
 223         sync
 224         ssm                     0,0
 225         SFDIAG          (5)
 226         ssm                     0,0
 227         MFDIAG_1        (28)
 228         b,n         perf_rdr_shift_in_W_leave
 229         ssm                     0,0
 230         nop
 231
 232         ;
 233         ; RDR 6 read sequence
 234         ;
 235         sync
 236         ssm                     0,0
 237         SFDIAG          (6)
 238         ssm                     0,0
 239         MFDIAG_1        (28)
 240         b,n         perf_rdr_shift_in_W_leave
 241         ssm                     0,0
 242         nop
 243
 244         ;
 245         ; RDR 7 read sequence
 246         ;
 247         b,n         perf_rdr_shift_in_W_leave
 248         nop
 249         nop
 250         nop
 251         nop
 252         nop
 253         nop
 254         nop
 255
 256         ;
 257         ; RDR 8 read sequence
 258         ;
 259         b,n         perf_rdr_shift_in_W_leave
 260         nop
 261         nop
 262         nop
 263         nop
 264         nop
 265         nop
 266         nop
 267
 268         ;
 269         ; RDR 9 read sequence
 270         ;
 271         b,n         perf_rdr_shift_in_W_leave
 272         nop
 273         nop
 274         nop
 275         nop
 276         nop
 277         nop
 278         nop
 279
 280         ;
 281         ; RDR 10 read sequence
 282         ;
 283         SFDIAG          (10)
 284         ssm                     0,0
 285         MFDIAG_1        (28)
 286         shrpd           ret0,%r0,%sar,%r1
 287         MTDIAG_1        (1)
 288         STDIAG          (10)
 289         ssm                     0,0
 290         b,n         perf_rdr_shift_in_W_leave
 291
 292         ;
 293         ; RDR 11 read sequence
 294         ;
 295         SFDIAG          (11)
 296         ssm                     0,0
 297         MFDIAG_1        (28)
 298         shrpd           ret0,%r0,%sar,%r1
 299         MTDIAG_1        (1)
 300         STDIAG          (11)
 301         ssm                     0,0
 302         b,n         perf_rdr_shift_in_W_leave
 303
 304         ;
 305         ; RDR 12 read sequence
 306         ;
 307         b,n         perf_rdr_shift_in_W_leave
 308         nop
 309         nop
 310         nop
 311         nop
 312         nop
 313         nop
 314         nop
 315
 316         ;
 317         ; RDR 13 read sequence
 318         ;
 319         sync
 320         ssm                     0,0
 321         SFDIAG          (13)
 322         ssm                     0,0
 323         MFDIAG_1        (28)
 324         b,n         perf_rdr_shift_in_W_leave
 325         ssm                     0,0
 326         nop
 327
 328         ;
 329         ; RDR 14 read sequence
 330         ;
 331         SFDIAG          (14)
 332         ssm                     0,0
 333         MFDIAG_1        (28)
 334         shrpd           ret0,%r0,%sar,%r1
 335         MTDIAG_1        (1)
 336         STDIAG          (14)
 337         ssm                     0,0
 338         b,n         perf_rdr_shift_in_W_leave
 339
 340         ;
 341         ; RDR 15 read sequence
 342         ;
 343         sync                            ; RDR 15 read sequence
 344         ssm                     0,0
 345         SFDIAG          (15)
 346         ssm                     0,0
 347         MFDIAG_1        (28)
 348         ssm                     0,0
 349         b,n         perf_rdr_shift_in_W_leave
 350         nop
 351
 352         ;
 353         ; RDR 16 read sequence
 354         ;
 355         sync                            ; RDR 16 read sequence
 356         ssm                     0,0
 357         SFDIAG          (16)
 358         ssm                     0,0
 359         MFDIAG_1        (28)
 360         b,n         perf_rdr_shift_in_W_leave
 361         ssm                     0,0
 362         nop
 363
 364         ;
 365         ; RDR 17 read sequence
 366         ;
 367         SFDIAG          (17)
 368         ssm                     0,0
 369         MFDIAG_1        (28)
 370         shrpd           ret0,%r0,%sar,%r1
 371         MTDIAG_1        (1)
 372         STDIAG          (17)
 373         ssm                     0,0
 374         b,n         perf_rdr_shift_in_W_leave
 375
 376         ;
 377         ; RDR 18 read sequence
 378         ;
 379         SFDIAG          (18)
 380         ssm                     0,0
 381         MFDIAG_1        (28)
 382         shrpd           ret0,%r0,%sar,%r1
 383         MTDIAG_1        (1)
 384         STDIAG          (18)
 385         ssm                     0,0
 386         b,n         perf_rdr_shift_in_W_leave
 387
 388 ;
 389 ; RDR 19 read sequence
 390 ;
 391         b,n         perf_rdr_shift_in_W_leave
 392         nop
 393         nop
 394         nop
 395         nop
 396         nop
 397         nop
 398         nop
 399
 400         ;
 401         ; RDR 20 read sequence
 402         ;
 403         sync
 404         ssm                     0,0
 405         SFDIAG          (20)
 406         ssm                     0,0
 407         MFDIAG_1        (28)
 408         b,n         perf_rdr_shift_in_W_leave
 409         ssm                     0,0
 410         nop
 411
 412         ;
 413         ; RDR 21 read sequence
 414         ;
 415         sync
 416         ssm                     0,0
 417         SFDIAG          (21)
 418         ssm                     0,0
 419         MFDIAG_1        (28)
 420         b,n         perf_rdr_shift_in_W_leave
 421         ssm                     0,0
 422         nop
 423
 424         ;
 425         ; RDR 22 read sequence
 426         ;
 427         sync
 428         ssm                     0,0
 429         SFDIAG          (22)
 430         ssm                     0,0
 431         MFDIAG_1        (28)
 432         b,n         perf_rdr_shift_in_W_leave
 433         ssm                     0,0
 434         nop
 435
 436         ;
 437         ; RDR 23 read sequence
 438         ;
 439         sync
 440         ssm                     0,0
 441         SFDIAG          (23)
 442         ssm                     0,0
 443         MFDIAG_1        (28)
 444         b,n         perf_rdr_shift_in_W_leave
 445         ssm                     0,0
 446         nop
 447
 448         ;
 449         ; RDR 24 read sequence
 450         ;
 451         sync
 452         ssm                     0,0
 453         SFDIAG          (24)
 454         ssm                     0,0
 455         MFDIAG_1        (28)
 456         b,n         perf_rdr_shift_in_W_leave
 457         ssm                     0,0
 458         nop
 459
 460         ;
 461         ; RDR 25 read sequence
 462         ;
 463         sync
 464         ssm                     0,0
 465         SFDIAG          (25)
 466         ssm                     0,0
 467         MFDIAG_1        (28)
 468         b,n         perf_rdr_shift_in_W_leave
 469         ssm                     0,0
 470         nop
 471
 472         ;
 473         ; RDR 26 read sequence
 474         ;
 475         SFDIAG          (26)
 476         ssm                     0,0
 477         MFDIAG_1        (28)
 478         shrpd           ret0,%r0,%sar,%r1
 479         MTDIAG_1        (1)
 480         STDIAG          (26)
 481         ssm                     0,0
 482         b,n         perf_rdr_shift_in_W_leave
 483
 484         ;
 485         ; RDR 27 read sequence
 486         ;
 487         SFDIAG          (27)
 488         ssm                     0,0
 489         MFDIAG_1        (28)
 490         shrpd           ret0,%r0,%sar,%r1
 491         MTDIAG_1        (1)
 492         STDIAG          (27)
 493         ssm                     0,0
 494         b,n         perf_rdr_shift_in_W_leave
 495
 496         ;
 497         ; RDR 28 read sequence
 498         ;
 499         sync
 500         ssm                     0,0
 501         SFDIAG          (28)
 502         ssm                     0,0
 503         MFDIAG_1        (28)
 504         b,n         perf_rdr_shift_in_W_leave
 505         ssm                     0,0
 506         nop
 507
 508         ;
 509         ; RDR 29 read sequence
 510         ;
 511         sync
 512         ssm                     0,0
 513         SFDIAG          (29)
 514         ssm                     0,0
 515         MFDIAG_1        (28)
 516         b,n         perf_rdr_shift_in_W_leave
 517         ssm                     0,0
 518         nop
 519
 520         ;
 521         ; RDR 30 read sequence
 522         ;
 523         SFDIAG          (30)
 524         ssm                     0,0
 525         MFDIAG_1        (28)
 526         shrpd           ret0,%r0,%sar,%r1
 527         MTDIAG_1        (1)
 528         STDIAG          (30)
 529         ssm                     0,0
 530         b,n         perf_rdr_shift_in_W_leave
 531
 532         ;
 533         ; RDR 31 read sequence
 534         ;
 535         sync
 536         ssm                     0,0
 537         SFDIAG          (31)
 538         ssm                     0,0
 539         MFDIAG_1        (28)
 540         nop
 541         ssm                     0,0
 542         nop
 543
 544         ;
 545         ; Fallthrough
 546         ;
 547
 548 perf_rdr_shift_in_W_leave:
 549         bve                 (%r2)
 550         .exit
 551         MTDIAG_2        (24)                    ; restore DR2
 552         .procend
 553
 554
 555 ;************************************************************************
 556 ;*                                                                                                                                              *
 557 ;* Name: perf_rdr_shift_out_W                                                                                           *
 558 ;*                                                                                                                                              *
 559 ;* Description:                                                                                                                 *
 560 ;*      This routine moves data to the RDR's.  The double-word that                     *
 561 ;*      arg1 points to is loaded and moved into the staging register.           *
 562 ;*      Then the STDIAG instruction for the RDR # in arg0 is called                     *
 563 ;*      to move the data to the RDR.                                                                            *
 564 ;*                                                                                                                                              *
 565 ;* Arguments:                                                                                                                   *
 566 ;*      arg0 = rdr number                                                                                                       *
 567 ;*      arg1 = 64-bit value to write                                                                            *
 568 ;*      %r24 - DR2 | DR2_SLOW_RET                                                                                       *
 569 ;*      %r23 - original DR2 value                                                                                       *
 570 ;*                                                                                                                                              *
 571 ;* Returns:                                                                                                                             *
 572 ;*      None                                                                                                                            *
 573 ;*                                                                                                                                              *
 574 ;* Register usage:                                                                                                              *
 575 ;*                                                                                                                                              *
 576 ;************************************************************************
 577
 578         .export perf_rdr_shift_out_W,code
 579 perf_rdr_shift_out_W:
 580         .proc
 581         .callinfo frame=0,NO_CALLS
 582         .entry
 583 ;
 584 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
 585 ; shifting is done, from or to, the remote diagnose registers.
 586 ;
 587
 588         depdi,z         1,DR2_SLOW_RET,1,%r24
 589         MFDIAG_2        (23)
 590         or                   %r24,%r23,%r24
 591         MTDIAG_2        (24)                    ; set DR2_SLOW_RET
 592
 593         MTDIAG_1        (25)                    ; data to the staging register
 594         shladd          arg0,2,%r0,%r1  ; %r1 = 4 * RDR number
 595         blr                 %r1,%r0                 ; branch to 8-instruction sequence
 596         nop
 597
 598         ;
 599         ; RDR 0 write sequence
 600         ;
 601         sync                            ; RDR 0 write sequence
 602         ssm                     0,0
 603         STDIAG          (0)
 604         ssm                     0,0
 605         b,n         perf_rdr_shift_out_W_leave
 606         nop
 607         ssm                     0,0
 608         nop
 609
 610         ;
 611         ; RDR 1 write sequence
 612         ;
 613         sync
 614         ssm             0,0
 615         STDIAG          (1)
 616         ssm             0,0
 617         b,n         perf_rdr_shift_out_W_leave
 618         nop
 619         ssm             0,0
 620         nop
 621
 622         ;
 623         ; RDR 2 write sequence
 624         ;
 625         sync
 626         ssm             0,0
 627         STDIAG          (2)
 628         ssm             0,0
 629         b,n         perf_rdr_shift_out_W_leave
 630         nop
 631         ssm             0,0
 632         nop
 633
 634         ;
 635         ; RDR 3 write sequence
 636         ;
 637         sync
 638         ssm             0,0
 639         STDIAG          (3)
 640         ssm             0,0
 641         b,n         perf_rdr_shift_out_W_leave
 642         nop
 643         ssm             0,0
 644         nop
 645
 646         ;
 647         ; RDR 4 write sequence
 648         ;
 649         sync
 650         ssm             0,0
 651         STDIAG          (4)
 652         ssm             0,0
 653         b,n         perf_rdr_shift_out_W_leave
 654         nop
 655         ssm             0,0
 656         nop
 657
 658         ;
 659         ; RDR 5 write sequence
 660         ;
 661         sync
 662         ssm             0,0
 663         STDIAG          (5)
 664         ssm             0,0
 665         b,n         perf_rdr_shift_out_W_leave
 666         nop
 667         ssm             0,0
 668         nop
 669
 670         ;
 671         ; RDR 6 write sequence
 672         ;
 673         sync
 674         ssm             0,0
 675         STDIAG          (6)
 676         ssm             0,0
 677         b,n         perf_rdr_shift_out_W_leave
 678         nop
 679         ssm             0,0
 680         nop
 681
 682         ;
 683         ; RDR 7 write sequence
 684         ;
 685         sync
 686         ssm             0,0
 687         STDIAG          (7)
 688         ssm             0,0
 689         b,n         perf_rdr_shift_out_W_leave
 690         nop
 691         ssm             0,0
 692         nop
 693
 694         ;
 695         ; RDR 8 write sequence
 696         ;
 697         sync
 698         ssm             0,0
 699         STDIAG          (8)
 700         ssm             0,0
 701         b,n         perf_rdr_shift_out_W_leave
 702         nop
 703         ssm             0,0
 704         nop
 705
 706         ;
 707         ; RDR 9 write sequence
 708         ;
 709         sync
 710         ssm             0,0
 711         STDIAG          (9)
 712         ssm             0,0
 713         b,n         perf_rdr_shift_out_W_leave
 714         nop
 715         ssm             0,0
 716         nop
 717
 718         ;
 719         ; RDR 10 write sequence
 720         ;
 721         sync
 722         ssm             0,0
 723         STDIAG          (10)
 724         STDIAG          (26)
 725         ssm             0,0
 726         b,n         perf_rdr_shift_out_W_leave
 727         ssm             0,0
 728         nop
 729
 730         ;
 731         ; RDR 11 write sequence
 732         ;
 733         sync
 734         ssm             0,0
 735         STDIAG          (11)
 736         STDIAG          (27)
 737         ssm             0,0
 738         b,n         perf_rdr_shift_out_W_leave
 739         ssm             0,0
 740         nop
 741
 742         ;
 743         ; RDR 12 write sequence
 744         ;
 745         sync
 746         ssm             0,0
 747         STDIAG          (12)
 748         ssm             0,0
 749         b,n         perf_rdr_shift_out_W_leave
 750         nop
 751         ssm             0,0
 752         nop
 753
 754         ;
 755         ; RDR 13 write sequence
 756         ;
 757         sync
 758         ssm             0,0
 759         STDIAG          (13)
 760         ssm             0,0
 761         b,n         perf_rdr_shift_out_W_leave
 762         nop
 763         ssm             0,0
 764         nop
 765
 766         ;
 767         ; RDR 14 write sequence
 768         ;
 769         sync
 770         ssm             0,0
 771         STDIAG          (14)
 772         ssm             0,0
 773         b,n         perf_rdr_shift_out_W_leave
 774         nop
 775         ssm             0,0
 776         nop
 777
 778         ;
 779         ; RDR 15 write sequence
 780         ;
 781         sync
 782         ssm             0,0
 783         STDIAG          (15)
 784         ssm             0,0
 785         b,n         perf_rdr_shift_out_W_leave
 786         nop
 787         ssm             0,0
 788         nop
 789
 790         ;
 791         ; RDR 16 write sequence
 792         ;
 793         sync
 794         ssm             0,0
 795         STDIAG          (16)
 796         ssm             0,0
 797         b,n         perf_rdr_shift_out_W_leave
 798         nop
 799         ssm             0,0
 800         nop
 801
 802         ;
 803         ; RDR 17 write sequence
 804         ;
 805         sync
 806         ssm             0,0
 807         STDIAG          (17)
 808         ssm             0,0
 809         b,n         perf_rdr_shift_out_W_leave
 810         nop
 811         ssm             0,0
 812         nop
 813
 814         ;
 815         ; RDR 18 write sequence
 816         ;
 817         sync
 818         ssm             0,0
 819         STDIAG          (18)
 820         ssm             0,0
 821         b,n         perf_rdr_shift_out_W_leave
 822         nop
 823         ssm             0,0
 824         nop
 825
 826         ;
 827         ; RDR 19 write sequence
 828         ;
 829         sync
 830         ssm             0,0
 831         STDIAG          (19)
 832         ssm             0,0
 833         b,n         perf_rdr_shift_out_W_leave
 834         nop
 835         ssm             0,0
 836         nop
 837
 838         ;
 839         ; RDR 20 write sequence
 840         ;
 841         sync
 842         ssm             0,0
 843         STDIAG          (20)
 844         ssm             0,0
 845         b,n         perf_rdr_shift_out_W_leave
 846         nop
 847         ssm             0,0
 848         nop
 849
 850         ;
 851         ; RDR 21 write sequence
 852         ;
 853         sync
 854         ssm             0,0
 855         STDIAG          (21)
 856         ssm             0,0
 857         b,n         perf_rdr_shift_out_W_leave
 858         nop
 859         ssm             0,0
 860         nop
 861
 862         ;
 863         ; RDR 22 write sequence
 864         ;
 865         sync
 866         ssm             0,0
 867         STDIAG          (22)
 868         ssm             0,0
 869         b,n         perf_rdr_shift_out_W_leave
 870         nop
 871         ssm             0,0
 872         nop
 873
 874         ;
 875         ; RDR 23 write sequence
 876         ;
 877         sync
 878         ssm             0,0
 879         STDIAG          (23)
 880         ssm             0,0
 881         b,n         perf_rdr_shift_out_W_leave
 882         nop
 883         ssm             0,0
 884         nop
 885
 886         ;
 887         ; RDR 24 write sequence
 888         ;
 889         sync
 890         ssm             0,0
 891         STDIAG          (24)
 892         ssm             0,0
 893         b,n         perf_rdr_shift_out_W_leave
 894         nop
 895         ssm             0,0
 896         nop
 897
 898         ;
 899         ; RDR 25 write sequence
 900         ;
 901         sync
 902         ssm             0,0
 903         STDIAG          (25)
 904         ssm             0,0
 905         b,n         perf_rdr_shift_out_W_leave
 906         nop
 907         ssm             0,0
 908         nop
 909
 910         ;
 911         ; RDR 26 write sequence
 912         ;
 913         sync
 914         ssm             0,0
 915         STDIAG          (10)
 916         STDIAG          (26)
 917         ssm             0,0
 918         b,n         perf_rdr_shift_out_W_leave
 919         ssm             0,0
 920         nop
 921
 922         ;
 923         ; RDR 27 write sequence
 924         ;
 925         sync
 926         ssm             0,0
 927         STDIAG          (11)
 928         STDIAG          (27)
 929         ssm             0,0
 930         b,n         perf_rdr_shift_out_W_leave
 931         ssm             0,0
 932         nop
 933
 934         ;
 935         ; RDR 28 write sequence
 936         ;
 937         sync
 938         ssm             0,0
 939         STDIAG          (28)
 940         ssm             0,0
 941         b,n         perf_rdr_shift_out_W_leave
 942         nop
 943         ssm             0,0
 944         nop
 945
 946         ;
 947         ; RDR 29 write sequence
 948         ;
 949         sync
 950         ssm             0,0
 951         STDIAG          (29)
 952         ssm             0,0
 953         b,n         perf_rdr_shift_out_W_leave
 954         nop
 955         ssm             0,0
 956         nop
 957
 958         ;
 959         ; RDR 30 write sequence
 960         ;
 961         sync
 962         ssm             0,0
 963         STDIAG          (30)
 964         ssm             0,0
 965         b,n         perf_rdr_shift_out_W_leave
 966         nop
 967         ssm             0,0
 968         nop
 969
 970         ;
 971         ; RDR 31 write sequence
 972         ;
 973         sync
 974         ssm             0,0
 975         STDIAG          (31)
 976         ssm             0,0
 977         b,n         perf_rdr_shift_out_W_leave
 978         nop
 979         ssm             0,0
 980         nop
 981
 982 perf_rdr_shift_out_W_leave:
 983         bve             (%r2)
 984         .exit
 985         MTDIAG_2        (23)                    ; restore DR2
 986         .procend
 987
 988
 989 ;**************************** CHRIS ***********************************
 990
 991 ;************************************************************************
 992 ;*                                                                                                                                              *
 993 ;* Name: rdr_shift_in_U                                                                                                 *
 994 ;*                                                                                                                                              *
 995 ;* Description:                                                                                                                 *
 996 ;*      This routine shifts data in from the RDR in arg0 and returns            *
 997 ;*      the result in ret0.  If the RDR is <= 64 bits in length, it                     *
 998 ;*      is shifted shifted backup immediately.  This is to compensate           *
 999 ;*      for RDR10 which has bits that preclude PDC stack operations                     *
1000 ;*      when they are in the wrong state.                                                                       *
1001 ;*                                                                                                                                              *
1002 ;* Arguments:                                                                                                                   *
1003 ;*      arg0 : rdr to be read                                                                                           *
1004 ;*      arg1 : bit length of rdr                                                                                        *
1005 ;*                                                                                                                                              *
1006 ;* Returns:                                                                                                                             *
1007 ;*      ret0 = next 64 bits of rdr data from staging register                           *
1008 ;*                                                                                                                                              *
1009 ;* Register usage:                                                                                                              *
1010 ;*      arg0 : rdr to be read                                                                   *
1011 ;*      arg1 : bit length of rdr                                                                *
1012 ;*      %r24 - original DR2 value                                                                                       *
1013 ;*      %r23 - DR2 | DR2_SLOW_RET                                                                                       *
1014 ;*      %r1  - scratch                                                                                                          *
1015 ;*                                                                                                                                              *
1016 ;************************************************************************
1017
1018         .export perf_rdr_shift_in_U,code
1019 perf_rdr_shift_in_U:
1020         .proc
1021         .callinfo frame=0,NO_CALLS
1022         .entry
1023
1024 ; read(shift in) the RDR.
1025 ;
1026 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1027 ; shifting is done, from or to, remote diagnose registers.
1028
1029         depdi,z         1,DR2_SLOW_RET,1,%r29
1030         MFDIAG_2        (24)
1031         or                      %r24,%r29,%r29
1032         MTDIAG_2        (29)                    ; set DR2_SLOW_RET
1033
1034         nop
1035         nop
1036         nop
1037         nop
1038
1039 ;
1040 ; Start of next 32-byte cacheline
1041 ;
1042         nop
1043         nop
1044         nop
1045         extrd,u         arg1,63,6,%r1
1046
1047         mtsar           %r1
1048         shladd          arg0,2,%r0,%r1  ; %r1 = 4 * RDR number
1049         blr             %r1,%r0         ; branch to 8-instruction sequence
1050         nop
1051
1052 ;
1053 ; Start of next 32-byte cacheline
1054 ;
1055         SFDIAG          (0)             ; RDR 0 read sequence
1056         ssm                     0,0
1057         MFDIAG_1        (28)
1058         shrpd           ret0,%r0,%sar,%r1
1059         MTDIAG_1        (1)
1060         STDIAG          (0)
1061         ssm                     0,0
1062         b,n         perf_rdr_shift_in_U_leave
1063
1064         SFDIAG          (1)             ; RDR 1 read sequence
1065         ssm                     0,0
1066         MFDIAG_1        (28)
1067         shrpd           ret0,%r0,%sar,%r1
1068         MTDIAG_1        (1)
1069         STDIAG          (1)
1070         ssm                     0,0
1071         b,n         perf_rdr_shift_in_U_leave
1072
1073         sync                            ; RDR 2 read sequence
1074         ssm                     0,0
1075         SFDIAG          (4)
1076         ssm                     0,0
1077         MFDIAG_1        (28)
1078         b,n         perf_rdr_shift_in_U_leave
1079         ssm                     0,0
1080         nop
1081
1082         sync                            ; RDR 3 read sequence
1083         ssm                     0,0
1084         SFDIAG          (3)
1085         ssm                     0,0
1086         MFDIAG_1        (28)
1087         b,n         perf_rdr_shift_in_U_leave
1088         ssm                     0,0
1089         nop
1090
1091         sync                            ; RDR 4 read sequence
1092         ssm                     0,0
1093         SFDIAG          (4)
1094         ssm                     0,0
1095         MFDIAG_1        (28)
1096         b,n         perf_rdr_shift_in_U_leave
1097         ssm                     0,0
1098         nop
1099
1100         sync                            ; RDR 5 read sequence
1101         ssm                     0,0
1102         SFDIAG          (5)
1103         ssm                     0,0
1104         MFDIAG_1        (28)
1105         b,n         perf_rdr_shift_in_U_leave
1106         ssm                     0,0
1107         nop
1108
1109         sync                            ; RDR 6 read sequence
1110         ssm                     0,0
1111         SFDIAG          (6)
1112         ssm                     0,0
1113         MFDIAG_1        (28)
1114         b,n         perf_rdr_shift_in_U_leave
1115         ssm                     0,0
1116         nop
1117
1118         sync                            ; RDR 7 read sequence
1119         ssm                     0,0
1120         SFDIAG          (7)
1121         ssm                     0,0
1122         MFDIAG_1        (28)
1123         b,n         perf_rdr_shift_in_U_leave
1124         ssm                     0,0
1125         nop
1126
1127         b,n         perf_rdr_shift_in_U_leave
1128         nop
1129         nop
1130         nop
1131         nop
1132         nop
1133         nop
1134         nop
1135
1136         SFDIAG          (9)             ; RDR 9 read sequence
1137         ssm                     0,0
1138         MFDIAG_1        (28)
1139         shrpd           ret0,%r0,%sar,%r1
1140         MTDIAG_1        (1)
1141         STDIAG          (9)
1142         ssm                     0,0
1143         b,n         perf_rdr_shift_in_U_leave
1144
1145         SFDIAG          (10)            ; RDR 10 read sequence
1146         ssm                     0,0
1147         MFDIAG_1        (28)
1148         shrpd           ret0,%r0,%sar,%r1
1149         MTDIAG_1        (1)
1150         STDIAG          (10)
1151         ssm                     0,0
1152         b,n         perf_rdr_shift_in_U_leave
1153
1154         SFDIAG          (11)            ; RDR 11 read sequence
1155         ssm                     0,0
1156         MFDIAG_1        (28)
1157         shrpd           ret0,%r0,%sar,%r1
1158         MTDIAG_1        (1)
1159         STDIAG          (11)
1160         ssm                     0,0
1161         b,n         perf_rdr_shift_in_U_leave
1162
1163         SFDIAG          (12)            ; RDR 12 read sequence
1164         ssm                     0,0
1165         MFDIAG_1        (28)
1166         shrpd           ret0,%r0,%sar,%r1
1167         MTDIAG_1        (1)
1168         STDIAG          (12)
1169         ssm                     0,0
1170         b,n         perf_rdr_shift_in_U_leave
1171
1172         SFDIAG          (13)            ; RDR 13 read sequence
1173         ssm                     0,0
1174         MFDIAG_1        (28)
1175         shrpd           ret0,%r0,%sar,%r1
1176         MTDIAG_1        (1)
1177         STDIAG          (13)
1178         ssm                     0,0
1179         b,n         perf_rdr_shift_in_U_leave
1180
1181         SFDIAG          (14)            ; RDR 14 read sequence
1182         ssm                     0,0
1183         MFDIAG_1        (28)
1184         shrpd           ret0,%r0,%sar,%r1
1185         MTDIAG_1        (1)
1186         STDIAG          (14)
1187         ssm                     0,0
1188         b,n         perf_rdr_shift_in_U_leave
1189
1190         SFDIAG          (15)            ; RDR 15 read sequence
1191         ssm                     0,0
1192         MFDIAG_1        (28)
1193         shrpd           ret0,%r0,%sar,%r1
1194         MTDIAG_1        (1)
1195         STDIAG          (15)
1196         ssm                     0,0
1197         b,n         perf_rdr_shift_in_U_leave
1198
1199         sync                            ; RDR 16 read sequence
1200         ssm                     0,0
1201         SFDIAG          (16)
1202         ssm                     0,0
1203         MFDIAG_1        (28)
1204         b,n         perf_rdr_shift_in_U_leave
1205         ssm                     0,0
1206         nop
1207
1208         SFDIAG          (17)            ; RDR 17 read sequence
1209         ssm                     0,0
1210         MFDIAG_1        (28)
1211         shrpd           ret0,%r0,%sar,%r1
1212         MTDIAG_1        (1)
1213         STDIAG          (17)
1214         ssm                     0,0
1215         b,n         perf_rdr_shift_in_U_leave
1216
1217         SFDIAG          (18)            ; RDR 18 read sequence
1218         ssm                     0,0
1219         MFDIAG_1        (28)
1220         shrpd           ret0,%r0,%sar,%r1
1221         MTDIAG_1        (1)
1222         STDIAG          (18)
1223         ssm                     0,0
1224         b,n         perf_rdr_shift_in_U_leave
1225
1226         b,n         perf_rdr_shift_in_U_leave
1227         nop
1228         nop
1229         nop
1230         nop
1231         nop
1232         nop
1233         nop
1234
1235         sync                            ; RDR 20 read sequence
1236         ssm                     0,0
1237         SFDIAG          (20)
1238         ssm                     0,0
1239         MFDIAG_1        (28)
1240         b,n         perf_rdr_shift_in_U_leave
1241         ssm                     0,0
1242         nop
1243
1244         sync                            ; RDR 21 read sequence
1245         ssm                     0,0
1246         SFDIAG          (21)
1247         ssm                     0,0
1248         MFDIAG_1        (28)
1249         b,n         perf_rdr_shift_in_U_leave
1250         ssm                     0,0
1251         nop
1252
1253         sync                            ; RDR 22 read sequence
1254         ssm                     0,0
1255         SFDIAG          (22)
1256         ssm                     0,0
1257         MFDIAG_1        (28)
1258         b,n         perf_rdr_shift_in_U_leave
1259         ssm                     0,0
1260         nop
1261
1262         sync                            ; RDR 23 read sequence
1263         ssm                     0,0
1264         SFDIAG          (23)
1265         ssm                     0,0
1266         MFDIAG_1        (28)
1267         b,n         perf_rdr_shift_in_U_leave
1268         ssm                     0,0
1269         nop
1270
1271         sync                            ; RDR 24 read sequence
1272         ssm                     0,0
1273         SFDIAG          (24)
1274         ssm                     0,0
1275         MFDIAG_1        (28)
1276         b,n         perf_rdr_shift_in_U_leave
1277         ssm                     0,0
1278         nop
1279
1280         sync                            ; RDR 25 read sequence
1281         ssm                     0,0
1282         SFDIAG          (25)
1283         ssm                     0,0
1284         MFDIAG_1        (28)
1285         b,n         perf_rdr_shift_in_U_leave
1286         ssm                     0,0
1287         nop
1288
1289         SFDIAG          (26)            ; RDR 26 read sequence
1290         ssm                     0,0
1291         MFDIAG_1        (28)
1292         shrpd           ret0,%r0,%sar,%r1
1293         MTDIAG_1        (1)
1294         STDIAG          (26)
1295         ssm                     0,0
1296         b,n         perf_rdr_shift_in_U_leave
1297
1298         SFDIAG          (27)            ; RDR 27 read sequence
1299         ssm                     0,0
1300         MFDIAG_1        (28)
1301         shrpd           ret0,%r0,%sar,%r1
1302         MTDIAG_1        (1)
1303         STDIAG          (27)
1304         ssm                     0,0
1305         b,n         perf_rdr_shift_in_U_leave
1306
1307         sync                            ; RDR 28 read sequence
1308         ssm                     0,0
1309         SFDIAG          (28)
1310         ssm                     0,0
1311         MFDIAG_1        (28)
1312         b,n         perf_rdr_shift_in_U_leave
1313         ssm                     0,0
1314         nop
1315
1316         b,n         perf_rdr_shift_in_U_leave
1317         nop
1318         nop
1319         nop
1320         nop
1321         nop
1322         nop
1323         nop
1324
1325         SFDIAG          (30)            ; RDR 30 read sequence
1326         ssm                     0,0
1327         MFDIAG_1        (28)
1328         shrpd           ret0,%r0,%sar,%r1
1329         MTDIAG_1        (1)
1330         STDIAG          (30)
1331         ssm                     0,0
1332         b,n         perf_rdr_shift_in_U_leave
1333
1334         SFDIAG          (31)            ; RDR 31 read sequence
1335         ssm                     0,0
1336         MFDIAG_1        (28)
1337         shrpd           ret0,%r0,%sar,%r1
1338         MTDIAG_1        (1)
1339         STDIAG          (31)
1340         ssm                     0,0
1341         b,n         perf_rdr_shift_in_U_leave
1342         nop
1343
1344 perf_rdr_shift_in_U_leave:
1345         bve                 (%r2)
1346         .exit
1347         MTDIAG_2        (24)                    ; restore DR2
1348         .procend
1349
1350 ;************************************************************************
1351 ;*                                                                                                                                              *
1352 ;* Name: rdr_shift_out_U                                                                                                *
1353 ;*                                                                                                                                              *
1354 ;* Description:                                                                                                                 *
1355 ;*      This routine moves data to the RDR's.  The double-word that                     *
1356 ;*      arg1 points to is loaded and moved into the staging register.           *
1357 ;*      Then the STDIAG instruction for the RDR # in arg0 is called                     *
1358 ;*      to move the data to the RDR.                                                                            *
1359 ;*                                                                                                                                              *
1360 ;* Arguments:                                                                                                                   *
1361 ;*      arg0 = rdr target                                                                                                       *
1362 ;*      arg1 = buffer pointer                                                                                           *
1363 ;*                                                                                                                                              *
1364 ;* Returns:                                                                                                                             *
1365 ;*      None                                                                                                                            *
1366 ;*                                                                                                                                              *
1367 ;* Register usage:                                                                                                              *
1368 ;*      arg0 = rdr target                                                                                                       *
1369 ;*      arg1 = buffer pointer                                                                                           *
1370 ;*      %r24 - DR2 | DR2_SLOW_RET                                                                                       *
1371 ;*      %r23 - original DR2 value                                                                                       *
1372 ;*                                                                                                                                              *
1373 ;************************************************************************
1374
1375         .export perf_rdr_shift_out_U,code
1376 perf_rdr_shift_out_U:
1377         .proc
1378         .callinfo frame=0,NO_CALLS
1379         .entry
1380
1381 ;
1382 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1383 ; shifting is done, from or to, the remote diagnose registers.
1384 ;
1385
1386         depdi,z         1,DR2_SLOW_RET,1,%r24
1387         MFDIAG_2        (23)
1388         or              %r24,%r23,%r24
1389         MTDIAG_2        (24)                    ; set DR2_SLOW_RET
1390
1391         MTDIAG_1        (25)                    ; data to the staging register
1392         shladd           arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
1393         blr                 %r1,%r0                 ; branch to 8-instruction sequence
1394         nop
1395
1396 ;
1397 ; 32-byte cachline aligned
1398 ;
1399
1400         sync                            ; RDR 0 write sequence
1401         ssm                     0,0
1402         STDIAG          (0)
1403         ssm                     0,0
1404         b,n         perf_rdr_shift_out_U_leave
1405         nop
1406         ssm                     0,0
1407         nop
1408
1409         sync                            ; RDR 1 write sequence
1410         ssm                     0,0
1411         STDIAG          (1)
1412         ssm                     0,0
1413         b,n         perf_rdr_shift_out_U_leave
1414         nop
1415         ssm                     0,0
1416         nop
1417
1418         sync                            ; RDR 2 write sequence
1419         ssm                     0,0
1420         STDIAG          (2)
1421         ssm                     0,0
1422         b,n         perf_rdr_shift_out_U_leave
1423         nop
1424         ssm                     0,0
1425         nop
1426
1427         sync                            ; RDR 3 write sequence
1428         ssm                     0,0
1429         STDIAG          (3)
1430         ssm                     0,0
1431         b,n         perf_rdr_shift_out_U_leave
1432         nop
1433         ssm                     0,0
1434         nop
1435
1436         sync                            ; RDR 4 write sequence
1437         ssm                     0,0
1438         STDIAG          (4)
1439         ssm                     0,0
1440         b,n         perf_rdr_shift_out_U_leave
1441         nop
1442         ssm                     0,0
1443         nop
1444
1445         sync                            ; RDR 5 write sequence
1446         ssm                     0,0
1447         STDIAG          (5)
1448         ssm                     0,0
1449         b,n         perf_rdr_shift_out_U_leave
1450         nop
1451         ssm                     0,0
1452         nop
1453
1454         sync                            ; RDR 6 write sequence
1455         ssm                     0,0
1456         STDIAG          (6)
1457         ssm                     0,0
1458         b,n         perf_rdr_shift_out_U_leave
1459         nop
1460         ssm                     0,0
1461         nop
1462
1463         sync                            ; RDR 7 write sequence
1464         ssm                     0,0
1465         STDIAG          (7)
1466         ssm                     0,0
1467         b,n         perf_rdr_shift_out_U_leave
1468         nop
1469         ssm                     0,0
1470         nop
1471
1472         sync                            ; RDR 8 write sequence
1473         ssm                     0,0
1474         STDIAG          (8)
1475         ssm                     0,0
1476         b,n         perf_rdr_shift_out_U_leave
1477         nop
1478         ssm                     0,0
1479         nop
1480
1481         sync                            ; RDR 9 write sequence
1482         ssm                     0,0
1483         STDIAG          (9)
1484         ssm                     0,0
1485         b,n         perf_rdr_shift_out_U_leave
1486         nop
1487         ssm                     0,0
1488         nop
1489
1490         sync                            ; RDR 10 write sequence
1491         ssm                     0,0
1492         STDIAG          (10)
1493         ssm                     0,0
1494         b,n         perf_rdr_shift_out_U_leave
1495         nop
1496         ssm                     0,0
1497         nop
1498
1499         sync                            ; RDR 11 write sequence
1500         ssm                     0,0
1501         STDIAG          (11)
1502         ssm                     0,0
1503         b,n         perf_rdr_shift_out_U_leave
1504         nop
1505         ssm                     0,0
1506         nop
1507
1508         sync                            ; RDR 12 write sequence
1509         ssm                     0,0
1510         STDIAG          (12)
1511         ssm                     0,0
1512         b,n         perf_rdr_shift_out_U_leave
1513         nop
1514         ssm                     0,0
1515         nop
1516
1517         sync                            ; RDR 13 write sequence
1518         ssm                     0,0
1519         STDIAG          (13)
1520         ssm                     0,0
1521         b,n         perf_rdr_shift_out_U_leave
1522         nop
1523         ssm                     0,0
1524         nop
1525
1526         sync                            ; RDR 14 write sequence
1527         ssm                     0,0
1528         STDIAG          (14)
1529         ssm                     0,0
1530         b,n         perf_rdr_shift_out_U_leave
1531         nop
1532         ssm                     0,0
1533         nop
1534
1535         sync                            ; RDR 15 write sequence
1536         ssm                     0,0
1537         STDIAG          (15)
1538         ssm                     0,0
1539         b,n         perf_rdr_shift_out_U_leave
1540         nop
1541         ssm                     0,0
1542         nop
1543
1544         sync                            ; RDR 16 write sequence
1545         ssm                     0,0
1546         STDIAG          (16)
1547         ssm                     0,0
1548         b,n         perf_rdr_shift_out_U_leave
1549         nop
1550         ssm                     0,0
1551         nop
1552
1553         sync                            ; RDR 17 write sequence
1554         ssm                     0,0
1555         STDIAG          (17)
1556         ssm                     0,0
1557         b,n         perf_rdr_shift_out_U_leave
1558         nop
1559         ssm                     0,0
1560         nop
1561
1562         sync                            ; RDR 18 write sequence
1563         ssm                     0,0
1564         STDIAG          (18)
1565         ssm                     0,0
1566         b,n         perf_rdr_shift_out_U_leave
1567         nop
1568         ssm                     0,0
1569         nop
1570
1571         sync                            ; RDR 19 write sequence
1572         ssm                     0,0
1573         STDIAG          (19)
1574         ssm                     0,0
1575         b,n         perf_rdr_shift_out_U_leave
1576         nop
1577         ssm                     0,0
1578         nop
1579
1580         sync                            ; RDR 20 write sequence
1581         ssm                     0,0
1582         STDIAG          (20)
1583         ssm                     0,0
1584         b,n         perf_rdr_shift_out_U_leave
1585         nop
1586         ssm                     0,0
1587         nop
1588
1589         sync                            ; RDR 21 write sequence
1590         ssm                     0,0
1591         STDIAG          (21)
1592         ssm                     0,0
1593         b,n         perf_rdr_shift_out_U_leave
1594         nop
1595         ssm                     0,0
1596         nop
1597
1598         sync                            ; RDR 22 write sequence
1599         ssm                     0,0
1600         STDIAG          (22)
1601         ssm                     0,0
1602         b,n         perf_rdr_shift_out_U_leave
1603         nop
1604         ssm                     0,0
1605         nop
1606
1607         sync                            ; RDR 23 write sequence
1608         ssm                     0,0
1609         STDIAG          (23)
1610         ssm                     0,0
1611         b,n         perf_rdr_shift_out_U_leave
1612         nop
1613         ssm                     0,0
1614         nop
1615
1616         sync                            ; RDR 24 write sequence
1617         ssm                     0,0
1618         STDIAG          (24)
1619         ssm                     0,0
1620         b,n         perf_rdr_shift_out_U_leave
1621         nop
1622         ssm                     0,0
1623         nop
1624
1625         sync                            ; RDR 25 write sequence
1626         ssm                     0,0
1627         STDIAG          (25)
1628         ssm                     0,0
1629         b,n         perf_rdr_shift_out_U_leave
1630         nop
1631         ssm                     0,0
1632         nop
1633
1634         sync                            ; RDR 26 write sequence
1635         ssm                     0,0
1636         STDIAG          (26)
1637         ssm                     0,0
1638         b,n         perf_rdr_shift_out_U_leave
1639         nop
1640         ssm                     0,0
1641         nop
1642
1643         sync                            ; RDR 27 write sequence
1644         ssm                     0,0
1645         STDIAG          (27)
1646         ssm                     0,0
1647         b,n         perf_rdr_shift_out_U_leave
1648         nop
1649         ssm                     0,0
1650         nop
1651
1652         sync                            ; RDR 28 write sequence
1653         ssm                     0,0
1654         STDIAG          (28)
1655         ssm                     0,0
1656         b,n         perf_rdr_shift_out_U_leave
1657         nop
1658         ssm                     0,0
1659         nop
1660
1661         sync                            ; RDR 29 write sequence
1662         ssm                     0,0
1663         STDIAG          (29)
1664         ssm                     0,0
1665         b,n         perf_rdr_shift_out_U_leave
1666         nop
1667         ssm                     0,0
1668         nop
1669
1670         sync                            ; RDR 30 write sequence
1671         ssm                     0,0
1672         STDIAG          (30)
1673         ssm                     0,0
1674         b,n         perf_rdr_shift_out_U_leave
1675         nop
1676         ssm                     0,0
1677         nop
1678
1679         sync                            ; RDR 31 write sequence
1680         ssm                     0,0
1681         STDIAG          (31)
1682         ssm                     0,0
1683         b,n         perf_rdr_shift_out_U_leave
1684         nop
1685         ssm                     0,0
1686         nop
1687
1688 perf_rdr_shift_out_U_leave:
1689         bve             (%r2)
1690         .exit
1691         MTDIAG_2        (23)                    ; restore DR2
1692         .procend
1693