arch/powerpc/platforms/cell/cbe_regs.h

   1 /*
   2  * cbe_regs.h
   3  *
   4  * This file is intended to hold the various register definitions for CBE
   5  * on-chip system devices (memory controller, IO controller, etc...)
   6  *
   7  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
   8  */
   9
  10 #ifndef CBE_REGS_H
  11 #define CBE_REGS_H
  12
  13 /*
  14  *
  15  * Some HID register definitions
  16  *
  17  */
  18
  19 /* CBE specific HID0 bits */
  20 #define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
  21 #define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
  22 #define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
  23 #define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
  24
  25
  26 /*
  27  *
  28  * Pervasive unit register definitions
  29  *
  30  */
  31
  32 struct cbe_pmd_regs {
  33         u8 pad_0x0000_0x0800[0x0800 - 0x0000];                  /* 0x0000 */
  34
  35         /* Thermal Sensor Registers */
  36         u64  ts_ctsr1;                                          /* 0x0800 */
  37         u64  ts_ctsr2;                                          /* 0x0808 */
  38         u64  ts_mtsr1;                                          /* 0x0810 */
  39         u64  ts_mtsr2;                                          /* 0x0818 */
  40         u64  ts_itr1;                                           /* 0x0820 */
  41         u64  ts_itr2;                                           /* 0x0828 */
  42         u64  ts_gitr;                                           /* 0x0830 */
  43         u64  ts_isr;                                            /* 0x0838 */
  44         u64  ts_imr;                                            /* 0x0840 */
  45         u64  tm_cr1;                                            /* 0x0848 */
  46         u64  tm_cr2;                                            /* 0x0850 */
  47         u64  tm_simr;                                           /* 0x0858 */
  48         u64  tm_tpr;                                            /* 0x0860 */
  49         u64  tm_str1;                                           /* 0x0868 */
  50         u64  tm_str2;                                           /* 0x0870 */
  51         u64  tm_tsr;                                            /* 0x0878 */
  52
  53         /* Power Management */
  54         u64  pm_control;                                        /* 0x0880 */
  55 #define CBE_PMD_PAUSE_ZERO_CONTROL              0x10000
  56         u64  pm_status;                                         /* 0x0888 */
  57
  58         /* Time Base Register */
  59         u64  tbr;                                               /* 0x0890 */
  60
  61         u8   pad_0x0898_0x0c00 [0x0c00 - 0x0898];               /* 0x0898 */
  62
  63         /* Fault Isolation Registers */
  64         u64  checkstop_fir;                                     /* 0x0c00 */
  65         u64  recoverable_fir;
  66         u64  spec_att_mchk_fir;
  67         u64  fir_mode_reg;
  68         u64  fir_enable_mask;
  69
  70         u8   pad_0x0c28_0x1000 [0x1000 - 0x0c28];               /* 0x0c28 */
  71 };
  72
  73 extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
  74 extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
  75
  76 /*
  77  *
  78  * IIC unit register definitions
  79  *
  80  */
  81
  82 struct cbe_iic_pending_bits {
  83         u32 data;
  84         u8 flags;
  85         u8 class;
  86         u8 source;
  87         u8 prio;
  88 };
  89
  90 #define CBE_IIC_IRQ_VALID       0x80
  91 #define CBE_IIC_IRQ_IPI         0x40
  92
  93 struct cbe_iic_thread_regs {
  94         struct cbe_iic_pending_bits pending;
  95         struct cbe_iic_pending_bits pending_destr;
  96         u64 generate;
  97         u64 prio;
  98 };
  99
 100 struct cbe_iic_regs {
 101         u8      pad_0x0000_0x0400[0x0400 - 0x0000];             /* 0x0000 */
 102
 103         /* IIC interrupt registers */
 104         struct  cbe_iic_thread_regs thread[2];                  /* 0x0400 */
 105         u64     iic_ir;                                         /* 0x0440 */
 106         u64     iic_is;                                         /* 0x0448 */
 107
 108         u8      pad_0x0450_0x0500[0x0500 - 0x0450];             /* 0x0450 */
 109
 110         /* IOC FIR */
 111         u64     ioc_fir_reset;                                  /* 0x0500 */
 112         u64     ioc_fir_set;
 113         u64     ioc_checkstop_enable;
 114         u64     ioc_fir_error_mask;
 115         u64     ioc_syserr_enable;
 116         u64     ioc_fir;
 117
 118         u8      pad_0x0530_0x1000[0x1000 - 0x0530];             /* 0x0530 */
 119 };
 120
 121 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
 122 extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
 123
 124
 125 /* Init this module early */
 126 extern void cbe_regs_init(void);
 127
 128
 129 #endif /* CBE_REGS_H */