2 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
3 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 * This version of the driver is a combination of the 8xx fec and
6 * 8260 SCC Ethernet drivers. This version has some additional
7 * configuration options, which should probably be moved out of
8 * here. This driver currently works for the EST SBC8260,
9 * SBS Diablo/BCM, Embedded Planet RPX6, TQM8260, and others.
11 * Right now, I am very watseful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets. Since this is a cache coherent processor and CPM,
17 * I could also preallocate SKB's and use them directly on the interface.
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
38 #include <asm/immap_8260.h>
39 #include <asm/pgtable.h>
40 #include <asm/mpc8260.h>
42 #include <asm/bitops.h>
43 #include <asm/uaccess.h>
44 #include <asm/cpm_8260.h>
46 /* The transmitter timeout
48 #define TX_TIMEOUT (2*HZ)
50 #ifdef CONFIG_USE_MDIO
51 /* Forward declarations of some structures to support different PHYs */
55 void (*funct)(uint mii_reg, struct net_device *dev);
62 const phy_cmd_t *config;
63 const phy_cmd_t *startup;
64 const phy_cmd_t *ack_int;
65 const phy_cmd_t *shutdown;
68 /* Register definitions for the PHY. */
70 #define MII_REG_CR 0 /* Control Register */
71 #define MII_REG_SR 1 /* Status Register */
72 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
73 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
74 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
75 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
76 #define MII_REG_ANER 6 /* A-N Expansion Register */
77 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
78 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
80 /* values for phy_status */
82 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
83 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
84 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
85 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
86 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
87 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
88 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
90 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
91 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
92 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
93 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
94 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
95 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
96 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
97 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
98 #endif /* CONFIG_USE_MDIO */
100 /* The number of Tx and Rx buffers. These are allocated from the page
101 * pool. The code may assume these are power of two, so it is best
102 * to keep them that size.
103 * We don't need to allocate pages for the transmitter. We just use
104 * the skbuffer directly.
106 #define FCC_ENET_RX_PAGES 16
107 #define FCC_ENET_RX_FRSIZE 2048
108 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
109 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
110 #define TX_RING_SIZE 16 /* Must be power of two */
111 #define TX_RING_MOD_MASK 15 /* for this to work */
113 /* The FCC stores dest/src/type, data, and checksum for receive packets.
115 #define PKT_MAXBUF_SIZE 1518
116 #define PKT_MINBUF_SIZE 64
118 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
120 #define PKT_MAXDMA_SIZE 1520
122 /* Maximum input buffer size. Must be a multiple of 32.
124 #define PKT_MAXBLR_SIZE 1536
126 static int fcc_enet_open(struct net_device *dev);
127 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
128 static int fcc_enet_rx(struct net_device *dev);
129 static irqreturn_t fcc_enet_interrupt(int irq, void *dev_id, struct pt_regs *);
130 static int fcc_enet_close(struct net_device *dev);
131 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
132 static void set_multicast_list(struct net_device *dev);
133 static void fcc_restart(struct net_device *dev, int duplex);
134 static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
136 /* These will be configurable for the FCC choice.
137 * Multiple ports can be configured. There is little choice among the
138 * I/O pins to the PHY, except the clocks. We will need some board
139 * dependent clock selection.
140 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
141 * help show what pins are used for each device.
144 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
145 * but there is little variation among the choices.
147 #define PA1_COL ((uint)0x00000001)
148 #define PA1_CRS ((uint)0x00000002)
149 #define PA1_TXER ((uint)0x00000004)
150 #define PA1_TXEN ((uint)0x00000008)
151 #define PA1_RXDV ((uint)0x00000010)
152 #define PA1_RXER ((uint)0x00000020)
153 #define PA1_TXDAT ((uint)0x00003c00)
154 #define PA1_RXDAT ((uint)0x0003c000)
155 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
156 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
158 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
159 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
161 #ifdef CONFIG_SBC82xx
162 /* rx is clk9, tx is clk10
164 #define PC_F1RXCLK ((uint)0x00000100)
165 #define PC_F1TXCLK ((uint)0x00000200)
166 #define CMX1_CLK_ROUTE ((uint)0x25000000)
167 #define CMX1_CLK_MASK ((uint)0xff000000)
169 /* CLK12 is receive, CLK11 is transmit. These are board specific.
171 #define PC_F1RXCLK ((uint)0x00000800)
172 #define PC_F1TXCLK ((uint)0x00000400)
173 #define CMX1_CLK_ROUTE ((uint)0x3e000000)
174 #define CMX1_CLK_MASK ((uint)0xff000000)
175 #endif /* !CONFIG_SBC82xx */
177 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
178 * but there is little variation among the choices.
180 #define PB2_TXER ((uint)0x00000001)
181 #define PB2_RXDV ((uint)0x00000002)
182 #define PB2_TXEN ((uint)0x00000004)
183 #define PB2_RXER ((uint)0x00000008)
184 #define PB2_COL ((uint)0x00000010)
185 #define PB2_CRS ((uint)0x00000020)
186 #define PB2_TXDAT ((uint)0x000003c0)
187 #define PB2_RXDAT ((uint)0x00003c00)
188 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
189 PB2_RXER | PB2_RXDV | PB2_TXER)
190 #define PB2_PSORB1 (PB2_TXEN)
191 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
192 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
194 /* CLK13 is receive, CLK14 is transmit. These are board dependent.
196 #define PC_F2RXCLK ((uint)0x00001000)
197 #define PC_F2TXCLK ((uint)0x00002000)
198 #define CMX2_CLK_ROUTE ((uint)0x00250000)
199 #define CMX2_CLK_MASK ((uint)0x00ff0000)
201 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
202 * but there is little variation among the choices.
204 #define PB3_RXDV ((uint)0x00004000)
205 #define PB3_RXER ((uint)0x00008000)
206 #define PB3_TXER ((uint)0x00010000)
207 #define PB3_TXEN ((uint)0x00020000)
208 #define PB3_COL ((uint)0x00040000)
209 #define PB3_CRS ((uint)0x00080000)
210 #define PB3_TXDAT ((uint)0x0f000000)
211 #define PB3_RXDAT ((uint)0x00f00000)
212 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
213 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
214 #define PB3_PSORB1 (0)
215 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
216 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
218 /* CLK15 is receive, CLK16 is transmit. These are board dependent.
220 #define PC_F3RXCLK ((uint)0x00004000)
221 #define PC_F3TXCLK ((uint)0x00008000)
222 #define CMX3_CLK_ROUTE ((uint)0x00003700)
223 #define CMX3_CLK_MASK ((uint)0x0000ff00)
225 /* MII status/control serial interface.
227 #ifdef CONFIG_TQM8260
228 /* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
229 #define PC_MDIO ((uint)0x00000002)
230 #define PC_MDCK ((uint)0x00000001)
232 #define PC_MDIO ((uint)0x00000004)
233 #define PC_MDCK ((uint)0x00000020)
236 /* A table of information for supporting FCCs. This does two things.
237 * First, we know how many FCCs we have and they are always externally
238 * numbered from zero. Second, it holds control register and I/O
239 * information that could be different among board designs.
241 typedef struct fcc_info {
254 static fcc_info_t fcc_ports[] = {
255 #ifdef CONFIG_FCC1_ENET
256 { 0, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
257 (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
258 # if defined(CONFIG_TQM8260)
261 0x00000004, 0x00000100 },
264 #ifdef CONFIG_FCC2_ENET
265 { 1, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
266 (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
267 # if defined(CONFIG_TQM8260)
269 # elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260)
270 0x00400000, 0x00200000 },
272 0x00000002, 0x00000080 },
275 #ifdef CONFIG_FCC3_ENET
276 { 2, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
277 (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
278 # if defined(CONFIG_TQM8260)
281 0x00000001, 0x00000040 },
286 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
287 * tx_bd_base always point to the base of the buffer descriptors. The
288 * cur_rx and cur_tx point to the currently available buffer.
289 * The dirty_tx tracks the current buffer that is being sent by the
290 * controller. The cur_tx and dirty_tx are equal under both completely
291 * empty and completely full conditions. The empty/ready indicator in
292 * the buffer descriptor determines the actual condition.
294 struct fcc_enet_private {
295 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
296 struct sk_buff* tx_skbuff[TX_RING_SIZE];
300 atomic_t n_pkts; /* Number of packets in tx ring */
302 /* CPM dual port RAM relative addresses.
304 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
306 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
307 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
308 volatile fcc_t *fccp;
309 volatile fcc_enet_t *ep;
310 struct net_device_stats stats;
314 #ifdef CONFIG_USE_MDIO
319 struct tq_struct phy_task;
324 #endif /* CONFIG_USE_MDIO */
333 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
334 volatile immap_t *immap);
335 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
336 static void init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
337 volatile immap_t *immap);
338 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
339 volatile immap_t *immap);
341 #ifdef CONFIG_USE_MDIO
342 static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
343 static uint mii_send_receive(fcc_info_t *fip, uint cmd);
345 static void fcc_stop(struct net_device *dev);
347 /* Make MII read/write commands for the FCC.
349 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
350 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
353 #endif /* CONFIG_USE_MDIO */
357 fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
359 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
364 /* Link is down or autonegotiation is in progress. */
368 /* Fill in a Tx ring entry */
371 #ifndef final_version
372 if (bdp->cbd_sc & BD_ENET_TX_READY) {
373 /* Ooops. All transmit buffers are full. Bail out.
374 * This should not happen, since cep->tx_full should be set.
376 printk("%s: tx queue full!.\n", dev->name);
381 /* Clear all of the status flags. */
382 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
384 /* If the frame is short, tell CPM to pad it. */
385 if (skb->len <= ETH_ZLEN)
386 bdp->cbd_sc |= BD_ENET_TX_PAD;
388 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
390 /* Set buffer length and buffer pointer. */
391 bdp->cbd_datlen = skb->len;
392 bdp->cbd_bufaddr = __pa(skb->data);
394 spin_lock_irq(&cep->lock);
396 /* Save skb pointer. */
397 idx = cep->skb_cur & TX_RING_MOD_MASK;
398 if (cep->tx_skbuff[idx]) {
399 /* This should never happen (any more).
400 Leave the sanity check in for now... */
401 printk(KERN_ERR "EEP. cep->tx_skbuff[%d] is %p not NULL in %s\n",
402 idx, cep->tx_skbuff[idx], __func__);
403 printk(KERN_ERR "Expect to lose %d bytes of sock space",
404 cep->tx_skbuff[idx]->truesize);
406 cep->tx_skbuff[idx] = skb;
408 cep->stats.tx_bytes += skb->len;
411 atomic_inc(&cep->n_pkts);
413 /* Send it on its way. Tell CPM its ready, interrupt when done,
414 * its the last BD of the frame, and to put the CRC on the end.
416 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
419 /* Errata says don't do this. */
420 cep->fccp->fcc_ftodr = 0x8000;
422 dev->trans_start = jiffies;
424 /* If this was the last BD in the ring, start at the beginning again. */
425 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
426 bdp = cep->tx_bd_base;
431 /* If the tx_ring is full, stop the queue */
432 if (atomic_read(&cep->n_pkts) >= (TX_RING_SIZE-1)) {
433 if (!netif_queue_stopped(dev)) {
434 netif_stop_queue(dev);
439 cep->cur_tx = (cbd_t *)bdp;
441 spin_unlock_irq(&cep->lock);
448 fcc_enet_timeout(struct net_device *dev)
450 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
452 printk("%s: transmit timed out.\n", dev->name);
453 cep->stats.tx_errors++;
454 #ifndef final_version
458 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
459 cep->cur_tx, cep->tx_full ? " (full)" : "",
461 bdp = cep->tx_bd_base;
462 printk(" Tx @base %p :\n", bdp);
463 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
464 printk("%04x %04x %08x\n",
468 bdp = cep->rx_bd_base;
469 printk(" Rx @base %p :\n", bdp);
470 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
471 printk("%04x %04x %08x\n",
478 netif_wake_queue(dev);
481 /* The interrupt handler. */
483 fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
485 struct net_device *dev = dev_id;
486 volatile struct fcc_enet_private *cep;
492 cep = (struct fcc_enet_private *)dev->priv;
494 /* Get the interrupt events that caused us to be here.
496 int_events = cep->fccp->fcc_fcce;
497 cep->fccp->fcc_fcce = int_events;
500 /* Handle receive event in its own function.
502 if (int_events & FCC_ENET_RXF)
505 /* Check for a transmit error. The manual is a little unclear
506 * about this, so the debug code until I get it figured out. It
507 * appears that if TXE is set, then TXB is not set. However,
508 * if carrier sense is lost during frame transmission, the TXE
509 * bit is set, "and continues the buffer transmission normally."
510 * I don't know if "normally" implies TXB is set when the buffer
511 * descriptor is closed.....trial and error :-).
514 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
516 if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) {
517 spin_lock(&cep->lock);
519 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
520 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
523 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
524 cep->stats.tx_heartbeat_errors++;
525 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
526 cep->stats.tx_window_errors++;
527 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
528 cep->stats.tx_aborted_errors++;
529 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
530 cep->stats.tx_fifo_errors++;
531 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
532 cep->stats.tx_carrier_errors++;
535 /* No heartbeat or Lost carrier are not really bad errors.
536 * The others require a restart transmit command.
539 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
541 cep->stats.tx_errors++;
544 cep->stats.tx_packets++;
546 /* Deferred means some collisions occurred during transmit,
547 * but we eventually sent the packet OK.
549 if (bdp->cbd_sc & BD_ENET_TX_DEF)
550 cep->stats.collisions++;
552 /* Free the sk buffer associated with this last transmit. */
553 idx = cep->skb_dirty & TX_RING_MOD_MASK;
554 dev_kfree_skb_irq(cep->tx_skbuff[idx]);
555 cep->tx_skbuff[idx] = NULL;
558 atomic_dec(&cep->n_pkts);
560 /* Update pointer to next buffer descriptor to be transmitted. */
561 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
562 bdp = cep->tx_bd_base;
566 /* I don't know if we can be held off from processing these
567 * interrupts for more than one frame time. I really hope
568 * not. In such a case, we would now want to check the
569 * currently available BD (cur_tx) and determine if any
570 * buffers between the dirty_tx and cur_tx have also been
571 * sent. We would want to process anything in between that
572 * does not have BD_ENET_TX_READY set.
575 /* Since we have freed up a buffer, the ring is no longer
580 if (netif_queue_stopped(dev)) {
581 netif_wake_queue(dev);
585 cep->dirty_tx = (cbd_t *)bdp;
589 volatile cpm8260_t *cp;
591 /* Some transmit errors cause the transmitter to shut
592 * down. We now issue a restart transmit. Since the
593 * errors close the BD and update the pointers, the restart
594 * _should_ pick up without having to reset any of our
595 * pointers either. Also, To workaround 8260 device erratum
596 * CPM37, we must disable and then re-enable the transmitter
597 * following a Late Collision, Underrun, or Retry Limit error.
599 cep->fccp->fcc_gfmr &= ~FCC_GFMR_ENT;
600 udelay(10); /* wait a few microseconds just on principle */
601 cep->fccp->fcc_gfmr |= FCC_GFMR_ENT;
605 mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock,
606 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
607 while (cp->cp_cpcr & CPM_CR_FLG);
609 spin_unlock(&cep->lock);
612 /* Check for receive busy, i.e. packets coming but no place to
615 if (int_events & FCC_ENET_BSY) {
616 cep->stats.rx_dropped++;
621 /* During a receive, the cur_rx points to the current incoming buffer.
622 * When we update through the ring, if the next incoming buffer has
623 * not been given to the system, we just set the empty indicator,
624 * effectively tossing the packet.
627 fcc_enet_rx(struct net_device *dev)
629 struct fcc_enet_private *cep;
634 cep = (struct fcc_enet_private *)dev->priv;
636 /* First, grab all of the stats for the incoming packet.
637 * These get messed up if we get called due to a busy condition.
642 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
645 #ifndef final_version
646 /* Since we have allocated space to hold a complete frame, both
647 * the first and last indicators should be set.
649 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
650 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
651 printk("CPM ENET: rcv is not first+last\n");
654 /* Frame too long or too short. */
655 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
656 cep->stats.rx_length_errors++;
657 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
658 cep->stats.rx_frame_errors++;
659 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
660 cep->stats.rx_crc_errors++;
661 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
662 cep->stats.rx_crc_errors++;
663 if (bdp->cbd_sc & BD_ENET_RX_CL) /* Late Collision */
664 cep->stats.rx_frame_errors++;
667 (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR
668 | BD_ENET_RX_OV | BD_ENET_RX_CL)))
670 /* Process the incoming frame. */
671 cep->stats.rx_packets++;
673 /* Remove the FCS from the packet length. */
674 pkt_len = bdp->cbd_datlen - 4;
675 cep->stats.rx_bytes += pkt_len;
677 /* This does 16 byte alignment, much more than we need. */
678 skb = dev_alloc_skb(pkt_len);
681 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
682 cep->stats.rx_dropped++;
686 skb_put(skb,pkt_len); /* Make room */
687 eth_copy_and_sum(skb,
688 (unsigned char *)__va(bdp->cbd_bufaddr),
690 skb->protocol=eth_type_trans(skb,dev);
695 /* Clear the status flags for this buffer. */
696 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
698 /* Mark the buffer empty. */
699 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
701 /* Update BD pointer to next entry. */
702 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
703 bdp = cep->rx_bd_base;
708 cep->cur_rx = (cbd_t *)bdp;
714 fcc_enet_close(struct net_device *dev)
716 /* Don't know what to do yet. */
717 netif_stop_queue(dev);
722 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev)
724 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
729 #ifdef CONFIG_USE_MDIO
731 /* NOTE: Most of the following comes from the FEC driver for 860. The
732 * overall structure of MII code has been retained (as it's proved stable
733 * and well-tested), but actual transfer requests are processed "at once"
734 * instead of being queued (there's no interrupt-driven MII transfer
735 * mechanism, one has to toggle the data/clock bits manually).
738 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
740 struct fcc_enet_private *fep;
743 /* Add PHY address to register command. */
745 regval |= fep->phy_addr << 23;
749 tmp = mii_send_receive(fep->fip, regval);
756 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
763 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
764 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
767 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
769 volatile struct fcc_enet_private *fep = dev->priv;
770 uint s = fep->phy_status;
772 s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
774 if (mii_reg & 0x0004)
776 if (mii_reg & 0x0010)
778 if (mii_reg & 0x0020)
782 fep->link = (s & PHY_STAT_LINK) ? 1 : 0;
785 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
787 volatile struct fcc_enet_private *fep = dev->priv;
788 uint s = fep->phy_status;
790 s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
792 if (mii_reg & 0x1000)
794 if (mii_reg & 0x4000)
800 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
802 volatile struct fcc_enet_private *fep = dev->priv;
803 uint s = fep->phy_status;
805 s &= ~(PHY_CONF_SPMASK);
807 if (mii_reg & 0x0020)
809 if (mii_reg & 0x0040)
811 if (mii_reg & 0x0080)
812 s |= PHY_CONF_100HDX;
813 if (mii_reg & 0x00100)
814 s |= PHY_CONF_100FDX;
818 /* ------------------------------------------------------------------------- */
819 /* The Level one LXT970 is used by many boards */
821 #ifdef CONFIG_FCC_LXT970
823 #define MII_LXT970_MIRROR 16 /* Mirror register */
824 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
825 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
826 #define MII_LXT970_CONFIG 19 /* Configuration Register */
827 #define MII_LXT970_CSR 20 /* Chip Status Register */
829 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
831 volatile struct fcc_enet_private *fep = dev->priv;
832 uint s = fep->phy_status;
834 s &= ~(PHY_STAT_SPMASK);
836 if (mii_reg & 0x0800) {
837 if (mii_reg & 0x1000)
838 s |= PHY_STAT_100FDX;
840 s |= PHY_STAT_100HDX;
842 if (mii_reg & 0x1000)
851 static phy_info_t phy_info_lxt970 = {
855 (const phy_cmd_t []) { /* config */
857 // { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
859 /* Set default operation of 100-TX....for some reason
860 * some of these bits are set on power up, which is wrong.
862 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
864 { mk_mii_read(MII_REG_CR), mii_parse_cr },
865 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
868 (const phy_cmd_t []) { /* startup - enable interrupts */
869 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
870 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
873 (const phy_cmd_t []) { /* ack_int */
874 /* read SR and ISR to acknowledge */
876 { mk_mii_read(MII_REG_SR), mii_parse_sr },
877 { mk_mii_read(MII_LXT970_ISR), NULL },
879 /* find out the current status */
881 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
884 (const phy_cmd_t []) { /* shutdown - disable interrupts */
885 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
890 #endif /* CONFIG_FEC_LXT970 */
892 /* ------------------------------------------------------------------------- */
893 /* The Level one LXT971 is used on some of my custom boards */
895 #ifdef CONFIG_FCC_LXT971
897 /* register definitions for the 971 */
899 #define MII_LXT971_PCR 16 /* Port Control Register */
900 #define MII_LXT971_SR2 17 /* Status Register 2 */
901 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
902 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
903 #define MII_LXT971_LCR 20 /* LED Control Register */
904 #define MII_LXT971_TCR 30 /* Transmit Control Register */
907 * I had some nice ideas of running the MDIO faster...
908 * The 971 should support 8MHz and I tried it, but things acted really
909 * weird, so 2.5 MHz ought to be enough for anyone...
912 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
914 volatile struct fcc_enet_private *fep = dev->priv;
915 uint s = fep->phy_status;
917 s &= ~(PHY_STAT_SPMASK);
919 if (mii_reg & 0x4000) {
920 if (mii_reg & 0x0200)
921 s |= PHY_STAT_100FDX;
923 s |= PHY_STAT_100HDX;
925 if (mii_reg & 0x0200)
930 if (mii_reg & 0x0008)
936 static phy_info_t phy_info_lxt971 = {
940 (const phy_cmd_t []) { /* config */
941 // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
942 { mk_mii_read(MII_REG_CR), mii_parse_cr },
943 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
946 (const phy_cmd_t []) { /* startup - enable interrupts */
947 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
948 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
950 /* Somehow does the 971 tell me that the link is down
951 * the first read after power-up.
952 * read here to get a valid value in ack_int */
954 { mk_mii_read(MII_REG_SR), mii_parse_sr },
957 (const phy_cmd_t []) { /* ack_int */
958 /* find out the current status */
960 { mk_mii_read(MII_REG_SR), mii_parse_sr },
961 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
963 /* we only need to read ISR to acknowledge */
965 { mk_mii_read(MII_LXT971_ISR), NULL },
968 (const phy_cmd_t []) { /* shutdown - disable interrupts */
969 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
974 #endif /* CONFIG_FEC_LXT970 */
977 /* ------------------------------------------------------------------------- */
978 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
980 #ifdef CONFIG_FCC_QS6612
982 /* register definitions */
984 #define MII_QS6612_MCR 17 /* Mode Control Register */
985 #define MII_QS6612_FTR 27 /* Factory Test Register */
986 #define MII_QS6612_MCO 28 /* Misc. Control Register */
987 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
988 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
989 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
991 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
993 volatile struct fcc_enet_private *fep = dev->priv;
994 uint s = fep->phy_status;
996 s &= ~(PHY_STAT_SPMASK);
998 switch((mii_reg >> 2) & 7) {
999 case 1: s |= PHY_STAT_10HDX; break;
1000 case 2: s |= PHY_STAT_100HDX; break;
1001 case 5: s |= PHY_STAT_10FDX; break;
1002 case 6: s |= PHY_STAT_100FDX; break;
1005 fep->phy_status = s;
1008 static phy_info_t phy_info_qs6612 = {
1012 (const phy_cmd_t []) { /* config */
1013 // { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
1015 /* The PHY powers up isolated on the RPX,
1016 * so send a command to allow operation.
1019 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1021 /* parse cr and anar to get some info */
1023 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1024 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1027 (const phy_cmd_t []) { /* startup - enable interrupts */
1028 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1029 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1032 (const phy_cmd_t []) { /* ack_int */
1034 /* we need to read ISR, SR and ANER to acknowledge */
1036 { mk_mii_read(MII_QS6612_ISR), NULL },
1037 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1038 { mk_mii_read(MII_REG_ANER), NULL },
1040 /* read pcr to get info */
1042 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1045 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1046 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1052 #endif /* CONFIG_FEC_QS6612 */
1055 static phy_info_t *phy_info[] = {
1057 #ifdef CONFIG_FCC_LXT970
1059 #endif /* CONFIG_FEC_LXT970 */
1061 #ifdef CONFIG_FCC_LXT971
1063 #endif /* CONFIG_FEC_LXT971 */
1065 #ifdef CONFIG_FCC_QS6612
1067 #endif /* CONFIG_FEC_LXT971 */
1072 static void mii_display_status(struct net_device *dev)
1074 volatile struct fcc_enet_private *fep = dev->priv;
1075 uint s = fep->phy_status;
1077 if (!fep->link && !fep->old_link) {
1078 /* Link is still down - don't print anything */
1082 printk("%s: status: ", dev->name);
1085 printk("link down");
1089 switch(s & PHY_STAT_SPMASK) {
1090 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1091 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1092 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1093 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1095 printk(", Unknown speed/duplex");
1098 if (s & PHY_STAT_ANC)
1099 printk(", auto-negotiation complete");
1102 if (s & PHY_STAT_FAULT)
1103 printk(", remote fault");
1108 static void mii_display_config(struct net_device *dev)
1110 volatile struct fcc_enet_private *fep = dev->priv;
1111 uint s = fep->phy_status;
1113 printk("%s: config: auto-negotiation ", dev->name);
1115 if (s & PHY_CONF_ANE)
1120 if (s & PHY_CONF_100FDX)
1122 if (s & PHY_CONF_100HDX)
1124 if (s & PHY_CONF_10FDX)
1126 if (s & PHY_CONF_10HDX)
1128 if (!(s & PHY_CONF_SPMASK))
1129 printk(", No speed/duplex selected?");
1131 if (s & PHY_CONF_LOOP)
1132 printk(", loopback enabled");
1136 fep->sequence_done = 1;
1139 static void mii_relink(struct net_device *dev)
1141 struct fcc_enet_private *fep = dev->priv;
1144 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1145 mii_display_status(dev);
1146 fep->old_link = fep->link;
1151 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1153 fcc_restart(dev, duplex);
1159 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1161 struct fcc_enet_private *fep = dev->priv;
1163 fep->phy_task.routine = (void *)mii_relink;
1164 fep->phy_task.data = dev;
1165 schedule_task(&fep->phy_task);
1168 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1170 struct fcc_enet_private *fep = dev->priv;
1172 fep->phy_task.routine = (void *)mii_display_config;
1173 fep->phy_task.data = dev;
1174 schedule_task(&fep->phy_task);
1179 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1181 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1185 /* Read remainder of PHY ID.
1188 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1190 struct fcc_enet_private *fep;
1194 fep->phy_id |= (mii_reg & 0xffff);
1196 for(i = 0; phy_info[i]; i++)
1197 if(phy_info[i]->id == (fep->phy_id >> 4))
1201 panic("%s: PHY id 0x%08x is not supported!\n",
1202 dev->name, fep->phy_id);
1204 fep->phy = phy_info[i];
1206 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1207 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1210 /* Scan all of the MII PHY addresses looking for someone to respond
1211 * with a valid ID. This usually happens quickly.
1214 mii_discover_phy(uint mii_reg, struct net_device *dev)
1216 struct fcc_enet_private *fep;
1221 if ((phytype = (mii_reg & 0xfff)) != 0xfff) {
1223 /* Got first part of ID, now get remainder. */
1224 fep->phy_id = phytype << 16;
1225 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1228 if (fep->phy_addr < 32) {
1229 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1232 printk("fec: No PHY device found.\n");
1237 /* This interrupt occurs when the PHY detects a link change. */
1239 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1241 struct net_device *dev = dev_id;
1242 struct fcc_enet_private *fep = dev->priv;
1244 mii_do_cmd(dev, fep->phy->ack_int);
1245 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1249 #endif /* CONFIG_USE_MDIO */
1251 /* Set or clear the multicast filter for this adaptor.
1252 * Skeleton taken from sunlance driver.
1253 * The CPM Ethernet implementation allows Multicast as well as individual
1254 * MAC address filtering. Some of the drivers check to make sure it is
1255 * a group multicast address, and discard those that are not. I guess I
1256 * will do the same for now, but just remove the test if you want
1257 * individual filtering as well (do the upper net layers want or support
1258 * this kind of feature?).
1261 set_multicast_list(struct net_device *dev)
1263 struct fcc_enet_private *cep;
1264 struct dev_mc_list *dmi;
1265 u_char *mcptr, *tdptr;
1266 volatile fcc_enet_t *ep;
1269 cep = (struct fcc_enet_private *)dev->priv;
1272 /* Get pointer to FCC area in parameter RAM.
1274 ep = (fcc_enet_t *)dev->base_addr;
1276 if (dev->flags&IFF_PROMISC) {
1278 /* Log any net taps. */
1279 printk("%s: Promiscuous mode enabled.\n", dev->name);
1280 cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
1283 cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO;
1285 if (dev->flags & IFF_ALLMULTI) {
1286 /* Catch all multicast addresses, so set the
1287 * filter to all 1's.
1289 ep->fen_gaddrh = 0xffffffff;
1290 ep->fen_gaddrl = 0xffffffff;
1293 /* Clear filter and add the addresses in the list.
1300 for (i=0; i<dev->mc_count; i++) {
1302 /* Only support group multicast for now.
1304 if (!(dmi->dmi_addr[0] & 1))
1307 /* The address in dmi_addr is LSB first,
1308 * and taddr is MSB first. We have to
1309 * copy bytes MSB first from dmi_addr.
1311 mcptr = (u_char *)dmi->dmi_addr + 5;
1312 tdptr = (u_char *)&ep->fen_taddrh;
1314 *tdptr++ = *mcptr--;
1316 /* Ask CPM to run CRC and set bit in
1319 cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage,
1320 cep->fip->fc_cpmblock, 0x0c,
1321 CPM_CR_SET_GADDR) | CPM_CR_FLG;
1323 while (cpmp->cp_cpcr & CPM_CR_FLG);
1330 /* Set the individual MAC address.
1332 int fcc_enet_set_mac_address(struct net_device *dev, void *p)
1334 struct sockaddr *addr= (struct sockaddr *) p;
1335 struct fcc_enet_private *cep;
1336 volatile fcc_enet_t *ep;
1340 cep = (struct fcc_enet_private *)(dev->priv);
1343 if (netif_running(dev))
1346 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1348 eap = (unsigned char *) &(ep->fen_paddrh);
1349 for (i=5; i>=0; i--)
1350 *eap++ = addr->sa_data[i];
1356 /* Initialize the CPM Ethernet on FCC.
1358 static int __init fec_enet_init(void)
1360 struct net_device *dev;
1361 struct fcc_enet_private *cep;
1364 volatile immap_t *immap;
1365 volatile iop8260_t *io;
1367 immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
1368 io = &immap->im_ioport;
1370 np = sizeof(fcc_ports) / sizeof(fcc_info_t);
1374 /* Create an Ethernet device instance.
1376 dev = alloc_etherdev(sizeof(*cep));
1381 spin_lock_init(&cep->lock);
1384 init_fcc_shutdown(fip, cep, immap);
1385 init_fcc_ioports(fip, io, immap);
1386 init_fcc_param(fip, dev, immap);
1388 dev->base_addr = (unsigned long)(cep->ep);
1390 /* The CPM Ethernet specific entries in the device
1393 dev->open = fcc_enet_open;
1394 dev->hard_start_xmit = fcc_enet_start_xmit;
1395 dev->tx_timeout = fcc_enet_timeout;
1396 dev->watchdog_timeo = TX_TIMEOUT;
1397 dev->stop = fcc_enet_close;
1398 dev->get_stats = fcc_enet_get_stats;
1399 dev->set_multicast_list = set_multicast_list;
1400 dev->set_mac_address = fcc_enet_set_mac_address;
1402 init_fcc_startup(fip, dev);
1404 err = register_netdev(dev);
1410 printk("%s: FCC ENET Version 0.3, ", dev->name);
1412 printk("%02x:", dev->dev_addr[i]);
1413 printk("%02x\n", dev->dev_addr[5]);
1415 #ifdef CONFIG_USE_MDIO
1416 /* Queue up command to detect the PHY and initialize the
1417 * remainder of the interface.
1420 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1421 #endif /* CONFIG_USE_MDIO */
1428 module_init(fec_enet_init);
1430 /* Make sure the device is shut down during initialization.
1433 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
1434 volatile immap_t *immap)
1436 volatile fcc_enet_t *ep;
1437 volatile fcc_t *fccp;
1439 /* Get pointer to FCC area in parameter RAM.
1441 ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]);
1443 /* And another to the FCC register area.
1445 fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]);
1446 cep->fccp = fccp; /* Keep the pointers handy */
1449 /* Disable receive and transmit in case someone left it running.
1451 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1454 /* Initialize the I/O pins for the FCC Ethernet.
1457 init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
1458 volatile immap_t *immap)
1461 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1463 if (fip->fc_proff == PROFF_FCC1) {
1464 /* Configure port A and C pins for FCC1 Ethernet.
1466 io->iop_pdira &= ~PA1_DIRA0;
1467 io->iop_pdira |= PA1_DIRA1;
1468 io->iop_psora &= ~PA1_PSORA0;
1469 io->iop_psora |= PA1_PSORA1;
1470 io->iop_ppara |= (PA1_DIRA0 | PA1_DIRA1);
1472 if (fip->fc_proff == PROFF_FCC2) {
1473 /* Configure port B and C pins for FCC Ethernet.
1475 io->iop_pdirb &= ~PB2_DIRB0;
1476 io->iop_pdirb |= PB2_DIRB1;
1477 io->iop_psorb &= ~PB2_PSORB0;
1478 io->iop_psorb |= PB2_PSORB1;
1479 io->iop_pparb |= (PB2_DIRB0 | PB2_DIRB1);
1481 if (fip->fc_proff == PROFF_FCC3) {
1482 /* Configure port B and C pins for FCC Ethernet.
1484 io->iop_pdirb &= ~PB3_DIRB0;
1485 io->iop_pdirb |= PB3_DIRB1;
1486 io->iop_psorb &= ~PB3_PSORB0;
1487 io->iop_psorb |= PB3_PSORB1;
1488 io->iop_pparb |= (PB3_DIRB0 | PB3_DIRB1);
1491 /* Port C has clocks......
1493 io->iop_psorc &= ~(fip->fc_trxclocks);
1494 io->iop_pdirc &= ~(fip->fc_trxclocks);
1495 io->iop_pparc |= fip->fc_trxclocks;
1497 #ifdef CONFIG_USE_MDIO
1498 /* ....and the MII serial clock/data.
1500 io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck);
1501 io->iop_podrc &= ~(fip->fc_mdio | fip->fc_mdck);
1502 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1503 io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck);
1504 #endif /* CONFIG_USE_MDIO */
1506 /* Configure Serial Interface clock routing.
1507 * First, clear all FCC bits to zero,
1508 * then set the ones we want.
1510 immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask);
1511 immap->im_cpmux.cmx_fcr |= fip->fc_clockroute;
1515 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
1516 volatile immap_t *immap)
1519 unsigned long mem_addr;
1522 struct fcc_enet_private *cep;
1523 volatile fcc_enet_t *ep;
1524 volatile cbd_t *bdp;
1525 volatile cpm8260_t *cp;
1527 cep = (struct fcc_enet_private *)(dev->priv);
1533 /* Zero the whole thing.....I must have missed some individually.
1534 * It works when I do this.
1536 memset((char *)ep, 0, sizeof(fcc_enet_t));
1538 /* Allocate space for the buffer descriptors in the DP ram.
1539 * These are relative offsets in the DP ram address space.
1540 * Initialize base addresses for the buffer descriptors.
1543 /* I really want to do this, but for some reason it doesn't
1544 * work with the data cache enabled, so I allocate from the
1545 * main memory instead.
1547 i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1548 ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
1549 cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1551 i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1552 ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
1553 cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
1555 cep->rx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
1556 ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
1557 cep->tx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
1558 ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
1561 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
1562 cep->cur_rx = cep->rx_bd_base;
1564 ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1565 ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1567 /* Set maximum bytes per receive buffer.
1568 * It must be a multiple of 32.
1570 ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
1572 /* Allocate space in the reserved FCC area of DPRAM for the
1573 * internal buffers. No one uses this space (yet), so we
1574 * can do this. Later, we will add resource management for
1577 mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128);
1578 ep->fen_genfcc.fcc_riptr = mem_addr;
1579 ep->fen_genfcc.fcc_tiptr = mem_addr+32;
1580 ep->fen_padptr = mem_addr+64;
1581 memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
1583 ep->fen_genfcc.fcc_rbptr = 0;
1584 ep->fen_genfcc.fcc_tbptr = 0;
1585 ep->fen_genfcc.fcc_rcrc = 0;
1586 ep->fen_genfcc.fcc_tcrc = 0;
1587 ep->fen_genfcc.fcc_res1 = 0;
1588 ep->fen_genfcc.fcc_res2 = 0;
1590 ep->fen_camptr = 0; /* CAM isn't used in this driver */
1592 /* Set CRC preset and mask.
1594 ep->fen_cmask = 0xdebb20e3;
1595 ep->fen_cpres = 0xffffffff;
1597 ep->fen_crcec = 0; /* CRC Error counter */
1598 ep->fen_alec = 0; /* alignment error counter */
1599 ep->fen_disfc = 0; /* discard frame counter */
1600 ep->fen_retlim = 15; /* Retry limit threshold */
1601 ep->fen_pper = 0; /* Normal persistence */
1603 /* Clear hash filter tables.
1610 /* Clear the Out-of-sequence TxBD.
1612 ep->fen_tfcstat = 0;
1616 ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
1617 ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
1619 /* Set Ethernet station address.
1621 * This is supplied in the board information structure, so we
1622 * copy that into the controller.
1623 * So, far we have only been given one Ethernet address. We make
1624 * it unique by setting a few bits in the upper byte of the
1625 * non-static part of the address.
1627 eap = (unsigned char *)&(ep->fen_paddrh);
1628 for (i=5; i>=0; i--) {
1629 #ifdef CONFIG_SBC82xx
1631 /* bd->bi_enetaddr holds the SCC0 address; the FCC
1632 devices count up from there */
1633 dev->dev_addr[i] = bd->bi_enetaddr[i] & ~3;
1634 dev->dev_addr[i] += 1 + fip->fc_fccnum;
1635 *eap++ = dev->dev_addr[i];
1639 dev->dev_addr[i] = bd->bi_enetaddr[i];
1640 dev->dev_addr[i] |= (1 << (7 - fip->fc_fccnum));
1641 *eap++ = dev->dev_addr[i];
1645 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
1653 ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
1654 ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
1656 /* Clear stat counters, in case we ever enable RMON.
1673 ep->fen_rfthr = 0; /* Suggested by manual */
1677 /* Now allocate the host memory pages and initialize the
1678 * buffer descriptors.
1680 bdp = cep->tx_bd_base;
1681 for (i=0; i<TX_RING_SIZE; i++) {
1683 /* Initialize the BD for every fragment in the page.
1686 bdp->cbd_datlen = 0;
1687 bdp->cbd_bufaddr = 0;
1691 /* Set the last buffer to wrap.
1694 bdp->cbd_sc |= BD_SC_WRAP;
1696 bdp = cep->rx_bd_base;
1697 for (i=0; i<FCC_ENET_RX_PAGES; i++) {
1701 mem_addr = __get_free_page(GFP_KERNEL);
1703 /* Initialize the BD for every fragment in the page.
1705 for (j=0; j<FCC_ENET_RX_FRPPG; j++) {
1706 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
1707 bdp->cbd_datlen = 0;
1708 bdp->cbd_bufaddr = __pa(mem_addr);
1709 mem_addr += FCC_ENET_RX_FRSIZE;
1714 /* Set the last buffer to wrap.
1717 bdp->cbd_sc |= BD_SC_WRAP;
1719 /* Let's re-initialize the channel now. We have to do it later
1720 * than the manual describes because we have just now finished
1721 * the BD initialization.
1723 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c,
1724 CPM_CR_INIT_TRX) | CPM_CR_FLG;
1725 while (cp->cp_cpcr & CPM_CR_FLG);
1727 cep->skb_cur = cep->skb_dirty = 0;
1728 atomic_set(&cep->n_pkts, 0);
1734 init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
1736 volatile fcc_t *fccp;
1737 struct fcc_enet_private *cep;
1739 cep = (struct fcc_enet_private *)(dev->priv);
1742 fccp->fcc_fcce = 0xffff; /* Clear any pending events */
1744 /* Enable interrupts for transmit error, complete frame
1745 * received, and any transmit buffer we have also set the
1748 fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
1750 /* Install our interrupt handler.
1752 if (request_irq(fip->fc_interrupt, fcc_enet_interrupt, 0,
1754 printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
1756 #ifdef CONFIG_USE_MDIO
1757 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0,
1759 printk("Can't get MII IRQ %d\n", fip->fc_interrupt);
1760 #endif /* CONFIG_USE_MDIO */
1762 /* Set GFMR to enable Ethernet operating mode.
1764 fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
1766 /* Set sync/delimiters.
1768 fccp->fcc_fdsr = 0xd555;
1770 /* Set protocol specific processing mode for Ethernet.
1771 * This has to be adjusted for Full Duplex operation after we can
1772 * determine how to detect that.
1774 fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
1776 #ifdef CONFIG_ADS8260
1779 ads_csr_addr[1] |= BCSR1_FETH_RST; /* Remove reset */
1780 ads_csr_addr[1] &= ~BCSR1_FETHIEN; /* Enable */
1783 #if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260)
1784 /* start in full duplex mode, and negotiate speed
1786 fcc_restart (dev, 1);
1788 /* start in half duplex mode
1790 fcc_restart (dev, 0);
1794 #ifdef CONFIG_USE_MDIO
1795 /* MII command/status interface.
1796 * I'm not going to describe all of the details. You can find the
1797 * protocol definition in many other places, including the data sheet
1798 * of most PHY parts.
1799 * I wonder what "they" were thinking (maybe weren't) when they leave
1800 * the I2C in the CPM but I have to toggle these bits......
1803 #define FCC_PDATC_MDIO(bit) \
1805 io->iop_pdatc |= fip->fc_mdio; \
1807 io->iop_pdatc &= ~fip->fc_mdio;
1809 #define FCC_PDATC_MDC(bit) \
1811 io->iop_pdatc |= fip->fc_mdck; \
1813 io->iop_pdatc &= ~fip->fc_mdck;
1816 mii_send_receive(fcc_info_t *fip, uint cmd)
1819 int read_op, i, off;
1820 volatile immap_t *immap;
1821 volatile iop8260_t *io;
1823 immap = (immap_t *)IMAP_ADDR;
1824 io = &immap->im_ioport;
1826 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1828 read_op = ((cmd & 0xf0000000) == 0x60000000);
1832 for (i = 0; i < 32; i++)
1843 for (i = 0, off = 31; i < (read_op ? 14 : 32); i++, --off)
1846 FCC_PDATC_MDIO((cmd >> off) & 0x00000001);
1859 io->iop_pdirc &= ~fip->fc_mdio;
1866 for (i = 0, off = 15; i < 16; i++, off--)
1870 if (io->iop_pdatc & fip->fc_mdio)
1878 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1880 for (i = 0; i < 32; i++)
1893 fcc_stop(struct net_device *dev)
1895 volatile fcc_t *fccp;
1896 struct fcc_enet_private *fcp;
1898 fcp = (struct fcc_enet_private *)(dev->priv);
1901 /* Disable transmit/receive */
1902 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1904 #endif /* CONFIG_USE_MDIO */
1907 fcc_restart(struct net_device *dev, int duplex)
1909 volatile fcc_t *fccp;
1910 struct fcc_enet_private *fcp;
1912 fcp = (struct fcc_enet_private *)(dev->priv);
1916 fccp->fcc_fpsmr |= FCC_PSMR_FDE;
1918 fccp->fcc_fpsmr &= ~FCC_PSMR_FDE;
1920 /* Enable transmit/receive */
1921 fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT;
1925 fcc_enet_open(struct net_device *dev)
1927 struct fcc_enet_private *fep = dev->priv;
1929 #ifdef CONFIG_USE_MDIO
1930 fep->sequence_done = 0;
1934 mii_do_cmd(dev, fep->phy->ack_int);
1935 mii_do_cmd(dev, fep->phy->config);
1936 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1937 while(!fep->sequence_done)
1940 mii_do_cmd(dev, fep->phy->startup);
1941 netif_start_queue(dev);
1942 return 0; /* Success */
1944 return -ENODEV; /* No PHY we understand */
1947 netif_start_queue(dev);
1948 return 0; /* Always succeed */
1949 #endif /* CONFIG_USE_MDIO */