2 * arch/ppc/boot/spruce/misc.c
4 * Misc. bootloader code for IBM Spruce reference platform
6 * Authors: Johnnie Peters <jpeters@mvista.com>
7 * Matt Porter <mporter@mvista.com>
9 * Derived from arch/ppc/boot/prep/misc.c
11 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
17 #include <linux/types.h>
18 #include <linux/config.h>
19 #include <linux/pci.h>
21 #include <asm/bootinfo.h>
23 extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
26 /* Define some important locations of the Spruce. */
27 #define SPRUCE_PCI_CONFIG_ADDR 0xfec00000
28 #define SPRUCE_PCI_CONFIG_DATA 0xfec00004
29 #define SPRUCE_ISA_IO_BASE 0xf8000000
31 /* PCI configuration space access routines. */
32 unsigned int *pci_config_address = (unsigned int *)SPRUCE_PCI_CONFIG_ADDR;
33 unsigned char *pci_config_data = (unsigned char *)SPRUCE_PCI_CONFIG_DATA;
35 void cpc700_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
36 unsigned char offset, unsigned char *val)
38 out_le32(pci_config_address,
39 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
41 *val= (in_le32((unsigned *)pci_config_data) >> (8 * (offset & 3))) & 0xff;
44 void cpc700_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
45 unsigned char offset, unsigned char val)
47 out_le32(pci_config_address,
48 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
50 out_8(pci_config_data + (offset&3), val);
53 void cpc700_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
54 unsigned char offset, unsigned short *val)
56 out_le32(pci_config_address,
57 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
59 *val= in_le16((unsigned short *)(pci_config_data + (offset&3)));
62 void cpc700_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
63 unsigned char offset, unsigned short val)
65 out_le32(pci_config_address,
66 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
68 out_le16((unsigned short *)(pci_config_data + (offset&3)), val);
71 void cpc700_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
72 unsigned char offset, unsigned int *val)
74 out_le32(pci_config_address,
75 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
77 *val= in_le32((unsigned *)pci_config_data);
80 void cpc700_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
81 unsigned char offset, unsigned int val)
83 out_le32(pci_config_address,
84 (((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
86 out_le32((unsigned *)pci_config_data, val);
89 unsigned long isa_io_base = SPRUCE_ISA_IO_BASE;
91 #define PCNET32_WIO_RDP 0x10
92 #define PCNET32_WIO_RAP 0x12
93 #define PCNET32_WIO_RESET 0x14
95 #define PCNET32_DWIO_RDP 0x10
96 #define PCNET32_DWIO_RAP 0x14
97 #define PCNET32_DWIO_RESET 0x18
99 /* Processor interface config register access */
100 #define PIFCFGADDR 0xff500000
101 #define PIFCFGDATA 0xff500004
103 #define PLBMIFOPT 0x18 /* PLB Master Interface Options */
105 #define MEM_MBEN 0x24
106 #define MEM_TYPE 0x28
107 #define MEM_B1SA 0x3c
108 #define MEM_B1EA 0x5c
109 #define MEM_B2SA 0x40
110 #define MEM_B2EA 0x60
116 unsigned long mem_size = 0;
117 unsigned long mem_mben;
118 unsigned long mem_type;
119 unsigned long mem_start;
120 unsigned long mem_end;
121 volatile int *mem_addr = (int *)0xff500008;
122 volatile int *mem_data = (int *)0xff50000c;
124 /* Get the size of memory from the memory controller. */
125 *mem_addr = MEM_MBEN;
127 mem_mben = *mem_data;
129 for(loop = 0; loop < 1000; loop++);
131 *mem_addr = MEM_TYPE;
133 mem_type = *mem_data;
135 for(loop = 0; loop < 1000; loop++);
137 *mem_addr = MEM_TYPE;
138 /* Confirm bank 1 has DRAM memory */
139 if ((mem_mben & 0x40000000) &&
140 ((mem_type & 0x30000000) == 0x10000000)) {
141 *mem_addr = MEM_B1SA;
143 mem_start = *mem_data;
145 for(loop = 0; loop < 1000; loop++);
147 *mem_addr = MEM_B1EA;
151 for(loop = 0; loop < 1000; loop++);
153 mem_size = mem_end - mem_start + 0x100000;
156 /* Confirm bank 2 has DRAM memory */
157 if ((mem_mben & 0x20000000) &&
158 ((mem_type & 0xc000000) == 0x4000000)) {
159 *mem_addr = MEM_B2SA;
161 mem_start = *mem_data;
163 for(loop = 0; loop < 1000; loop++);
165 *mem_addr = MEM_B2EA;
169 for(loop = 0; loop < 1000; loop++);
171 mem_size += mem_end - mem_start + 0x100000;
177 load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
178 void *ign1, void *ign2)
184 unsigned short vendor;
185 unsigned short device;
186 unsigned short command;
187 unsigned char header_type;
189 volatile int *pif_addr = (int *)0xff500000;
190 volatile int *pif_data = (int *)0xff500004;
193 * Gah, these firmware guys need to learn that hardware
194 * byte swapping is evil! Disable all hardware byte
195 * swapping so it doesn't hurt anyone.
197 *pif_addr = PLBMIFOPT;
199 *pif_data = 0x00000000;
202 /* Search out and turn off the PcNet ethernet boot device. */
203 for (pci_devfn = 1; pci_devfn < 0xff; pci_devfn++) {
204 if (PCI_FUNC(pci_devfn) && !found_multi)
207 cpc700_pcibios_read_config_byte(0, pci_devfn,
208 PCI_HEADER_TYPE, &header_type);
210 if (!PCI_FUNC(pci_devfn))
211 found_multi = header_type & 0x80;
213 cpc700_pcibios_read_config_word(0, pci_devfn, PCI_VENDOR_ID,
216 if (vendor != 0xffff) {
217 cpc700_pcibios_read_config_word(0, pci_devfn,
218 PCI_DEVICE_ID, &device);
220 /* If this PCI device is the Lance PCNet board then turn it off */
221 if ((vendor == PCI_VENDOR_ID_AMD) &&
222 (device == PCI_DEVICE_ID_AMD_LANCE)) {
224 /* Turn on I/O Space on the board. */
225 cpc700_pcibios_read_config_word(0, pci_devfn,
226 PCI_COMMAND, &command);
228 cpc700_pcibios_write_config_word(0, pci_devfn,
229 PCI_COMMAND, command);
231 /* Get the I/O space address */
232 cpc700_pcibios_read_config_dword(0, pci_devfn,
233 PCI_BASE_ADDRESS_0, &bar0);
236 /* Reset the PCNet Board */
237 inl (bar0+PCNET32_DWIO_RESET);
238 inw (bar0+PCNET32_WIO_RESET);
240 /* First do a work oriented read of csr0. If the value is
241 * 4 then this is the correct mode to access the board.
242 * If not try a double word ortiented read.
244 outw(0, bar0 + PCNET32_WIO_RAP);
245 csr0 = inw(bar0 + PCNET32_WIO_RDP);
248 /* Check the Chip id register */
249 outw(88, bar0 + PCNET32_WIO_RAP);
250 csr_id = inw(bar0 + PCNET32_WIO_RDP);
253 /* This is the valid mode - set the stop bit */
254 outw(0, bar0 + PCNET32_WIO_RAP);
255 outw(csr0, bar0 + PCNET32_WIO_RDP);
258 outl(0, bar0 + PCNET32_DWIO_RAP);
259 csr0 = inl(bar0 + PCNET32_DWIO_RDP);
261 /* Check the Chip id register */
262 outl(88, bar0 + PCNET32_WIO_RAP);
263 csr_id = inl(bar0 + PCNET32_WIO_RDP);
266 /* This is the valid mode - set the stop bit*/
267 outl(0, bar0 + PCNET32_WIO_RAP);
268 outl(csr0, bar0 + PCNET32_WIO_RDP);
276 return decompress_kernel(load_addr, num_words, cksum);