arch/ppc/kernel/cputable.c

   1 /*
   2  *  arch/ppc/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/threads.h>
  16 #include <linux/init.h>
  17 #include <asm/cputable.h>
  18
  19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
  20
  21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
  35
  36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
  37                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4))
  38
  39 /* This table only contains "desktop" CPUs, it need to be filled with embedded
  40  * ones as well...
  41  */
  42 #define COMMON_PPC      (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  43                          PPC_FEATURE_HAS_MMU)
  44
  45 /* We only set the altivec features if the kernel was compiled with altivec
  46  * support
  47  */
  48 #ifdef CONFIG_ALTIVEC
  49 #define CPU_FTR_ALTIVEC_COMP            CPU_FTR_ALTIVEC
  50 #define PPC_FEATURE_ALTIVEC_COMP        PPC_FEATURE_HAS_ALTIVEC
  51 #else
  52 #define CPU_FTR_ALTIVEC_COMP            0
  53 #define PPC_FEATURE_ALTIVEC_COMP        0
  54 #endif
  55
  56 /* We need to mark all pages as being coherent if we're SMP or we
  57  * have a 754x and an MPC107 host bridge. */
  58 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
  59 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
  60 #else
  61 #define CPU_FTR_COMMON                  0
  62 #endif
  63
  64 struct cpu_spec cpu_specs[] = {
  65 #if CLASSIC_PPC
  66     {   /* 601 */
  67         0xffff0000, 0x00010000, "601",
  68         CPU_FTR_COMMON |
  69         CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
  70         COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE,
  71         32, 32,
  72         __setup_cpu_601
  73     },
  74     {   /* 603 */
  75         0xffff0000, 0x00030000, "603",
  76         CPU_FTR_COMMON |
  77         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  78         CPU_FTR_CAN_NAP,
  79         COMMON_PPC,
  80         32, 32,
  81         __setup_cpu_603
  82     },
  83     {   /* 603e */
  84         0xffff0000, 0x00060000, "603e",
  85         CPU_FTR_COMMON |
  86         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  87         CPU_FTR_CAN_NAP,
  88         COMMON_PPC,
  89         32, 32,
  90         __setup_cpu_603
  91     },
  92     {   /* 603ev */
  93         0xffff0000, 0x00070000, "603ev",
  94         CPU_FTR_COMMON |
  95         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
  96         CPU_FTR_CAN_NAP,
  97         COMMON_PPC,
  98         32, 32,
  99         __setup_cpu_603
 100     },
 101     {   /* 604 */
 102         0xffff0000, 0x00040000, "604",
 103         CPU_FTR_COMMON |
 104         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 105         CPU_FTR_HPTE_TABLE,
 106         COMMON_PPC,
 107         32, 32,
 108         __setup_cpu_604
 109     },
 110     {   /* 604e */
 111         0xfffff000, 0x00090000, "604e",
 112         CPU_FTR_COMMON |
 113         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 114         CPU_FTR_HPTE_TABLE,
 115         COMMON_PPC,
 116         32, 32,
 117         __setup_cpu_604
 118     },
 119     {   /* 604r */
 120         0xffff0000, 0x00090000, "604r",
 121         CPU_FTR_COMMON |
 122         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 123         CPU_FTR_HPTE_TABLE,
 124         COMMON_PPC,
 125         32, 32,
 126         __setup_cpu_604
 127     },
 128     {   /* 604ev */
 129         0xffff0000, 0x000a0000, "604ev",
 130         CPU_FTR_COMMON |
 131         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON |
 132         CPU_FTR_HPTE_TABLE,
 133         COMMON_PPC,
 134         32, 32,
 135         __setup_cpu_604
 136     },
 137     {   /* 740/750 (0x4202, don't support TAU ?) */
 138         0xffffffff, 0x00084202, "740/750",
 139         CPU_FTR_COMMON |
 140         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 141         CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 142         COMMON_PPC,
 143         32, 32,
 144         __setup_cpu_750
 145     },
 146     {   /* 745/755 */
 147         0xfffff000, 0x00083000, "745/755",
 148         CPU_FTR_COMMON |
 149         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 150         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 151         COMMON_PPC,
 152         32, 32,
 153         __setup_cpu_750
 154     },
 155     {   /* 750CX (80100 and 8010x?) */
 156         0xfffffff0, 0x00080100, "750CX",
 157         CPU_FTR_COMMON |
 158         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 159         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 160         COMMON_PPC,
 161         32, 32,
 162         __setup_cpu_750cx
 163     },
 164     {   /* 750CX (82201 and 82202) */
 165         0xfffffff0, 0x00082200, "750CX",
 166         CPU_FTR_COMMON |
 167         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 168         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 169         COMMON_PPC,
 170         32, 32,
 171         __setup_cpu_750cx
 172     },
 173     {   /* 750CXe (82214) */
 174         0xfffffff0, 0x00082210, "750CXe",
 175         CPU_FTR_COMMON |
 176         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 177         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 178         COMMON_PPC,
 179         32, 32,
 180         __setup_cpu_750cx
 181     },
 182     {   /* 750FX rev 1.x */
 183         0xffffff00, 0x70000100, "750FX",
 184         CPU_FTR_COMMON |
 185         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 186         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 187         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 188         COMMON_PPC,
 189         32, 32,
 190         __setup_cpu_750
 191     },
 192     {   /* 750FX rev 2.0 must disable HID0[DPM] */
 193         0xffffffff, 0x70000200, "750FX",
 194         CPU_FTR_COMMON |
 195         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 196         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 197         CPU_FTR_NO_DPM,
 198         COMMON_PPC,
 199         32, 32,
 200         __setup_cpu_750
 201     },
 202     {   /* 750FX (All revs except 2.0) */
 203         0xffff0000, 0x70000000, "750FX",
 204         CPU_FTR_COMMON |
 205         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 206         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 207         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 208         COMMON_PPC,
 209         32, 32,
 210         __setup_cpu_750fx
 211     },
 212     {   /* 750GX */
 213         0xffff0000, 0x70020000, "750GX",
 214         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 215         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
 216         CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 217         COMMON_PPC,
 218         32, 32,
 219         __setup_cpu_750fx
 220     },
 221     {   /* 740/750 (L2CR bit need fixup for 740) */
 222         0xffff0000, 0x00080000, "740/750",
 223         CPU_FTR_COMMON |
 224         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 225         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
 226         COMMON_PPC,
 227         32, 32,
 228         __setup_cpu_750
 229     },
 230     {   /* 7400 rev 1.1 ? (no TAU) */
 231         0xffffffff, 0x000c1101, "7400 (1.1)",
 232         CPU_FTR_COMMON |
 233         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 234         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 235         CPU_FTR_CAN_NAP,
 236         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 237         32, 32,
 238         __setup_cpu_7400
 239     },
 240     {   /* 7400 */
 241         0xffff0000, 0x000c0000, "7400",
 242         CPU_FTR_COMMON |
 243         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 244         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 245         CPU_FTR_CAN_NAP,
 246         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 247         32, 32,
 248         __setup_cpu_7400
 249     },
 250     {   /* 7410 */
 251         0xffff0000, 0x800c0000, "7410",
 252         CPU_FTR_COMMON |
 253         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
 254         CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 255         CPU_FTR_CAN_NAP,
 256         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 257         32, 32,
 258         __setup_cpu_7410
 259     },
 260     {   /* 7450 2.0 - no doze/nap */
 261         0xffffffff, 0x80000200, "7450",
 262         CPU_FTR_COMMON |
 263         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 264         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 265         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
 266         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 267         32, 32,
 268         __setup_cpu_745x
 269     },
 270     {   /* 7450 2.1 */
 271         0xffffffff, 0x80000201, "7450",
 272         CPU_FTR_COMMON |
 273         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 274         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 275         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 276         CPU_FTR_L3_DISABLE_NAP,
 277         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 278         32, 32,
 279         __setup_cpu_745x
 280     },
 281     {   /* 7450 2.3 and newer */
 282         0xffff0000, 0x80000000, "7450",
 283         CPU_FTR_COMMON |
 284         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 285         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 286         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
 287         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 288         32, 32,
 289         __setup_cpu_745x
 290     },
 291     {   /* 7455 rev 1.x */
 292         0xffffff00, 0x80010100, "7455",
 293         CPU_FTR_COMMON |
 294         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 295         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 296         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
 297         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 298         32, 32,
 299         __setup_cpu_745x
 300     },
 301     {   /* 7455 rev 2.0 */
 302         0xffffffff, 0x80010200, "7455",
 303         CPU_FTR_COMMON |
 304         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 305         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 306         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 307         CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
 308         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 309         32, 32,
 310         __setup_cpu_745x
 311     },
 312     {   /* 7455 others */
 313         0xffff0000, 0x80010000, "7455",
 314         CPU_FTR_COMMON |
 315         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 316         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 317         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 318         CPU_FTR_HAS_HIGH_BATS,
 319         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 320         32, 32,
 321         __setup_cpu_745x
 322     },
 323     {   /* 7457 */
 324         0xffff0000, 0x80020000, "7457",
 325         CPU_FTR_COMMON |
 326         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 327         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 328         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 329         CPU_FTR_HAS_HIGH_BATS,
 330         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 331         32, 32,
 332         __setup_cpu_745x
 333     },
 334     {   /* 7447A */
 335         0xffff0000, 0x80030000, "7447A",
 336         CPU_FTR_COMMON |
 337         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
 338         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 339         CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 340         CPU_FTR_HAS_HIGH_BATS,
 341         COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 342         32, 32,
 343         __setup_cpu_745x
 344     },
 345     {   /* 82xx (8240, 8245, 8260 are all 603e cores) */
 346         0x7fff0000, 0x00810000, "82xx",
 347         CPU_FTR_COMMON |
 348         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
 349         COMMON_PPC,
 350         32, 32,
 351         __setup_cpu_603
 352     },
 353     {   /* default match, we assume split I/D cache & TB (non-601)... */
 354         0x00000000, 0x00000000, "(generic PPC)",
 355         CPU_FTR_COMMON |
 356         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 357         COMMON_PPC,
 358         32, 32,
 359         __setup_cpu_generic
 360     },
 361 #endif /* CLASSIC_PPC */
 362 #ifdef CONFIG_PPC64BRIDGE
 363     {   /* Power3 */
 364         0xffff0000, 0x00400000, "Power3 (630)",
 365         CPU_FTR_COMMON |
 366         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 367         COMMON_PPC | PPC_FEATURE_64,
 368         128, 128,
 369         __setup_cpu_power3
 370     },
 371     {   /* Power3+ */
 372         0xffff0000, 0x00410000, "Power3 (630+)",
 373         CPU_FTR_COMMON |
 374         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 375         COMMON_PPC | PPC_FEATURE_64,
 376         128, 128,
 377         __setup_cpu_power3
 378     },
 379         {       /* I-star */
 380                 0xffff0000, 0x00360000, "I-star",
 381                 CPU_FTR_COMMON |
 382                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 383                 COMMON_PPC | PPC_FEATURE_64,
 384                 128, 128,
 385                 __setup_cpu_power3
 386         },
 387         {       /* S-star */
 388                 0xffff0000, 0x00370000, "S-star",
 389                 CPU_FTR_COMMON |
 390                 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 391                 COMMON_PPC | PPC_FEATURE_64,
 392                 128, 128,
 393                 __setup_cpu_power3
 394         },
 395 #endif /* CONFIG_PPC64BRIDGE */
 396 #ifdef CONFIG_POWER4
 397     {   /* Power4 */
 398         0xffff0000, 0x00350000, "Power4",
 399         CPU_FTR_COMMON |
 400         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 401         COMMON_PPC | PPC_FEATURE_64,
 402         128, 128,
 403         __setup_cpu_power4
 404     },
 405     {   /* PPC970 */
 406         0xffff0000, 0x00390000, "PPC970",
 407         CPU_FTR_COMMON |
 408         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 409         CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
 410         COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 411         128, 128,
 412         __setup_cpu_ppc970
 413     },
 414 #endif /* CONFIG_POWER4 */
 415 #ifdef CONFIG_8xx
 416     {   /* 8xx */
 417         0xffff0000, 0x00500000, "8xx",
 418                 /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
 419         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 420         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 421         16, 16,
 422         __setup_cpu_8xx /* Empty */
 423     },
 424 #endif /* CONFIG_8xx */
 425 #ifdef CONFIG_40x
 426     {   /* 403GC */
 427         0xffffff00, 0x00200200, "403GC",
 428         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 429         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 430         16, 16,
 431         0, /*__setup_cpu_403 */
 432     },
 433     {   /* 403GCX */
 434         0xffffff00, 0x00201400, "403GCX",
 435         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 436         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 437         16, 16,
 438         0, /*__setup_cpu_403 */
 439     },
 440     {   /* 403G ?? */
 441         0xffff0000, 0x00200000, "403G ??",
 442         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 443         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 444         16, 16,
 445         0, /*__setup_cpu_403 */
 446     },
 447     {   /* 405GP */
 448         0xffff0000, 0x40110000, "405GP",
 449         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 450         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 451         32, 32,
 452         0, /*__setup_cpu_405 */
 453     },
 454     {   /* STB 03xxx */
 455         0xffff0000, 0x40130000, "STB03xxx",
 456         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 457         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 458         32, 32,
 459         0, /*__setup_cpu_405 */
 460     },
 461     {   /* STB 04xxx */
 462         0xffff0000, 0x41810000, "STB04xxx",
 463         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 464         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 465         32, 32,
 466         0, /*__setup_cpu_405 */
 467     },
 468     {   /* NP405L */
 469         0xffff0000, 0x41610000, "NP405L",
 470         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 471         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 472         32, 32,
 473         0, /*__setup_cpu_405 */
 474     },
 475     {   /* NP4GS3 */
 476         0xffff0000, 0x40B10000, "NP4GS3",
 477         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 478         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 479         32, 32,
 480         0, /*__setup_cpu_405 */
 481     },
 482     {   /* NP405H */
 483         0xffff0000, 0x41410000, "NP405H",
 484         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 485         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 486         32, 32,
 487         0, /*__setup_cpu_405 */
 488      },
 489      {  /* 405GPr */
 490         0xffff0000, 0x50910000, "405GPr",
 491         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 492         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 493         32, 32,
 494         0, /*__setup_cpu_405 */
 495     },
 496     {   /* STBx25xx */
 497         0xffff0000, 0x51510000, "STBx25xx",
 498         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 499         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 500         32, 32,
 501         0, /*__setup_cpu_405 */
 502      },
 503      {  /* 405LP */
 504         0xffff0000, 0x41F10000, "405LP",
 505         CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
 506         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 507         32, 32,
 508         0, /*__setup_cpu_405 */
 509      },
 510      {  /* Xilinx Virtex-II Pro  */
 511         0xffff0000, 0x20010000, "Virtex-II Pro",
 512         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 513         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
 514         32, 32,
 515         0, /*__setup_cpu_405 */
 516      },
 517
 518 #endif /* CONFIG_40x */
 519 #ifdef CONFIG_44x
 520     { /* 440GP Rev. B */
 521         0xf0000fff, 0x40000440, "440GP Rev. B",
 522         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 523         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 524         32, 32,
 525         0, /*__setup_cpu_440 */
 526     },
 527     { /* 440GP Rev. C */
 528         0xf0000fff, 0x40000481, "440GP Rev. C",
 529         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 530         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 531         32, 32,
 532         0, /*__setup_cpu_440 */
 533     },
 534     { /* 440GX Rev. A */
 535         0xf0000fff, 0x50000850, "440GX Rev. A",
 536         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 537         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 538         32, 32,
 539         0, /*__setup_cpu_440 */
 540     },
 541     { /* 440GX Rev. B */
 542         0xf0000fff, 0x50000851, "440GX Rev. B",
 543         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 544         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 545         32, 32,
 546         0, /*__setup_cpu_440 */
 547     },
 548     { /* 440GX Rev. C */
 549         0xf0000fff, 0x50000892, "440GX Rev. C",
 550         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 551         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
 552         32, 32,
 553         0, /*__setup_cpu_440 */
 554     },
 555 #endif /* CONFIG_44x */
 556 #if !CLASSIC_PPC
 557     {   /* default match */
 558         0x00000000, 0x00000000, "(generic PPC)",
 559         CPU_FTR_COMMON,
 560         PPC_FEATURE_32,
 561         32, 32,
 562         0,
 563     }
 564 #endif /* !CLASSIC_PPC */
 565 };